ATMEL FCD4B14CC

Features
•
•
•
•
•
•
•
•
•
•
•
•
Sensitive Layer Over a 0.8 µm CMOS Array
Image Zone: 0.4 x 14 mm = 0.02" x 0.55"
Image Array: 8 x 280 = 2240 pixels
Pixel Pitch: 50 µm x 50 µm = 500 dpi
Pixel Clock: up to 2 MHz Enabling up to 1780 Frames per Second
Die Size: 1.7 x 17.3 mm
Operating Voltage: 3V to 5.5V
Naturally Protected Against ESD: > 16 kV Air Discharge
Power Consumption: 20 mW at 3.3V, 1 MHz, 25°C
Operating Temperature Range: 0°C to +70°C: C suffix
Resistant to Abrasion: >1 Million Finger Sweeps
Chip-On-Board (COB) package or 20-lead Ceramic DIP available for development, with
Specific Protective Layer
Applications
•
•
•
•
•
•
•
•
•
PDA (Access Control, Data Protection)
Cellular Phones, SmartPhone (Access e-business)
Notebook, PC-add on (Access Control, e-business)
PIN Code Replacement
Automated Teller Machine, POS
Building Access
Electronic Keys (Cars, Home,...)
Portable Fingerprint Imaging for Law Enforcement
TV Access
Figure 1. Fingerchip Packages
Step for easy
integration
Chip-on-Board Package
(COB)
Sensing area
Wire protection
(not drawn)
Thermal
Fingerprint
Sensor with
0.4 mm x 14 mm
(0.02" x 0.55")
Sensing Area
and
Digital Output
(On-chip ADC)
FCD4B14
FingerChip™
20-pin, 0.3" Dual-Inline
Ceramic Package
(DIP20)
Rev. 1962C–01/02
1
Table 1. Pin Description For DIP Ceramic Package
Pin Number
Name
Type
1
GND
GND
2
AVE
Analog output
3
TPP
Power
4
VCC
Power
5
RST
Digital input
6
OE
Digital input
7
De0
Digital output
8
De1
Digital output
9
De2
Digital output
10
De3
Digital output
11
FPL
GND
12
Do3
Digital output
13
Do2
Digital output
14
Do1
Digital output
15
Do0
Digital output
16
GND
GND
17
ACKN
Digital output
18
PCLK
Digital input
19
TPE
Digital input
20
AVO
Analog output
Die Attach is connected to pin 1 and 16, and must be grounded. FPL pin must be
grounded.
GND
AVE
TPP
VCC
RST
OE
De0
De1
De2
De3
2
1
22
33
4
55
66
77
8
99
10
20
19
18
17
16
15
14
13
12
11
AVO
TPE
PCLK
ACKN
GND
Do0
Do1
Do2
Do3
FPL
FCD4B14
1962C–01/02
FCD4B14
Table 2. Pin Description For Chip-On-Board Package
Pin Number
Name
Type
1
GND
GND
2
AVE
Analog output
3
AVO
Analog output
4
TPP
Power
5
TPE
Digital input
6
VCC
Power
7
GND
GND
8
RST
Digital input
9
PCLK
Digital input
10
OE
Digital input
11
ACKN
Digital output
12
De0
Digital output
13
Do0
Digital output
14
De1
Digital output
15
Do1
Digital output
16
De2
Digital output
17
Do2
Digital output
18
De3
Digital output
19
Do3
Digital output
20
FPL
GND
21
GND
GND
Die Attach is connected to pin 1, 7 and 21, and must be grounded. FPL pin must be
grounded.
GND
AVE
AVO
TPP
TPE
VCC
GND
RST
PCLK
OE
ACKN
De0
Do0
De1
Do1
De2
Do2
De3
Do3
FPL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
GND
21
3
1962C–01/02
Description
FCD4B14 is part of the FingerChip Atmel monolithic fingerprint sensor family for which
no optics, no prism and no light source are required.
FCD4B14 is a single chip, high performance, low cost sensor based on temperature
physical effects for fingerprint sensing.
FCD4B14 has a linear shape, allowing for the capture of a fingerprint image by sweeping the finger across the sensing area. After capturing several images, Atmel proprietary
software can reconstruct a full 8-bit fingerprint image, if needed.
FCD4B14 has a small surface combined with CMOS technology, and a Chip-On-Board
or ceramic dual-in-line package assembly. These facts contribute to a low-cost device.
FCD4B14 delivers a programmable number of images per second, while an integrated
Analog to Digital Converter delivers a digital signal adapted to interfaces such as an
EPP parallel port, USB microcontroller or directly to micro-processors. Thus, no frame
grabber or glue interface is necessary to send the frames. These facts make FCD4B14
an easy device to include in any system for identification or verification applications.
Table 3. Absolute Maximum Ratings(1)
Parameter
Symbol
Comments
Value
Unit
Positive supply voltage
VCC
GND to 6.5
V
Temperature stabilization power
TPP
GND to 6.5
V
Front plane
FPL
GND to VCC
V
Digital input voltage
RST PCLK
GND to VCC
V
Storage temperature
Tstg
-50 to +85
°C
Do not solder
Forbidden
°C
DIP: socket mandatory
1. Absolute maximum ratings are limiting values, to be applied individually, while other parameters are within specified operating conditions. Long exposure to maximum ratings may affect device reliability.
Lead temperature (soldering, 10 seconds.)
Note:
Tleads
Table 4. Recommended Conditions Of Use
Parameter
Symbol
Positive supply voltage
VCC
Front plane
FPL
Comments
Min
Typ
Max
Unit
3V
5V
5.5V
V
Must be grounded
GND
V
Digital input voltage
CMOS levels
V
Digital output voltage
CMOS levels
V
Digital load
CL
Analog load
CA
RA
Not connected
Operating temperature range
Tamb
Civil: “C” grade
Maximum current on TPP
ITPP
4
50
pF
pF
kΩ
0 to +70
0
°C
100
mA
FCD4B14
1962C–01/02
FCD4B14
Table 5. Resistance
Parameter
Min Value
Standard Method
On pins. HBM (Human Body Model) CMOS I/O
2 kV
MIL-STD-883- method 3015.7
On die surface (Zapgun)
Air discharge
±16 kV
NF EN 6100-4-2
200 000
MIL E 12397B
4 hours
Internal method
ESD
MECHANICAL ABRASION
Number of cycles without lubricant multiply by a
factor of 20 for correlation with a real finger
CHEMICAL RESISTANCE
Cleaning agent, acid, grease, alcohol, diluted
acetone
Table 6. Specifications
Explanation Of Test Levels
I
100% production tested at +25°C
II
100% production tested at +25°C, and sample tested at specified temperatures (AC testing done on sample)
III
Sample tested only
IV
Parameter is guaranteed by design and/or characterization testing
V
Parameter is a typical value only
VI
100% production tested at temperature extremes
D
100% probe tested on wafer at Tamb = +25°C
Parameter
Symbol
Test Level
Min
Typ
Max
Unit
Resolution
IV
50
micron
Size
IV
8x280
pixel
Yield: number of bad pixels
I
Equivalent resistance on TPP pin
I
23
30
15
bad pixels
47
Ω
5
1962C–01/02
Table 7. 5V. Power supply = +5V; Tamb = 25°C; FPCLK = 1 MHz; Duty cycle = 50%;
Cload 120 pF on digital outputs, analog outputs disconnected otherwise specified.
Parameter
Symbol
Test Level
Min
Typ
Max
Unit
4.5
5
5.5
V
Power Requirements
Positive supply voltage
VCC
Digital positive supply current on VCC pin
Cload = 0
ICC
I
IV
7
5
10
6
mA
mA
PCC
I
IV
35
25
50
30
mW
mW
ICCNAP
I
10
µA
VAVx
I
2.9
V
Power dissipation on VCC
Cload = 0
Current on VCC in NAP mode
Analog Output
Voltage range
0
Digital Inputs
Logic compatibility
CMOS
Logic “0” voltage
VIL
I
0
1.2
V
Logic “1” voltage
VIH
I
3.6
VCC
V
Logic “0” current
IIL
I
-10
0
µA
Logic “1”current
IIH
I
0
10
µA
1.5
V
Digital Outputs
Logic compatibility
Logic “0” voltage
VOL
I
(1)
VOH
I
Logic “1” voltage
Note:
1. With IOL = 1 mA and IOH = -1 mA
6
CMOS
(1)
3.5
V
FCD4B14
1962C–01/02
FCD4B14
.
Table 8. 3.3V. Power supply = +3.3V; Tamb = 25°C; FPCLK = 1 MHz; Duty cycle = 50%;
Cload 120 pF on digital outputs, analog outputs disconnected otherwise specified
Parameter
Symbol
Test Level
Min
Typ
Max
Unit
3.0
3.3
3.6
V
Power Requirements
Positive supply voltage
VCC
Digital positive supply current on VCC pin
Cload= 0
ICC
I
IV
6
5
10
6
mA
mA
Power dissipation on VCC
Cload = 0
PCC
I
IV
20
17
33
20
mW
mW
ICCNAP
I
10
µA
VAVx
I
2.9
V
Current on VCC in NAP mode
Analog Output
Voltage range
0
Digital Inputs
Logic compatibility
CMOS
Logic “0” voltage
VIL
I
0
0.8
V
Logic “1” voltage
VIH
I
2.3
VCC
V
Logic “0” current
IIL
I
-10
0
µA
Logic “1”current
IIH
I
0
10
µA
0.6
V
Digital Outputs
Logic compatibility
Logic “0” voltage
CMOS
(1)
VOL
I
(1)
VOH
I
Logic “1” voltage
Note:
1. With IOL = 1 mA and IOH = -1 mA
2.4
V
7
1962C–01/02
.
Table 9. Switching Performances. Tamb = 25°C; FPCLK = 1 MHz; Duty cycle = 50%;
Cload 120 pF on digital and analog outputs otherwise specified
Parameter
Symbol
Test level
Min
Typ
Max
Unit
Clock frequency
fPCLK
I
0.5
1
2
MHz
Clock pulse width (high)
tHCLK
I
250
ns
Clock pulse width (low)
tLCLK
I
250
ns
Clock setup time (high)/reset falling edge
tSetup
I
No data change
tNOOE
IV
100
Parameter
Symbol
Test level
Min
Output delay from PCLK to ACKN rising edge
tPLHACKN
Output delay from PCLK to ACKN falling edge
0
ns
ns
Table 10. 5.0V. All power supplies = +5 V
Max
Unit
I
85
ns
tPHLACKN
I
80
ns
tPDATA
I
70
ns
tPAVIDEO
I
170
ns
Output delay from OE to data high-Z
tDATAZ
IV
25
ns
Output delay from OE to data output
tZDATA
IV
29
ns
Parameter
Symbol
Test level
Output delay from PCLK to ACKN rising edge
tPLHACKN
Output delay from PCLK to ACKN falling edge
Output delay from PCLK to Data output Dxi
Output delay from PCLK to Analog output Avx
Typ
Table 11. 3.3V. All power supplies = +3.3 V
Max
Unit
I
110
ns
tPHLACKN
I
95
ns
tPDATA
I
85
ns
tPAVIDEO
I
190
ns
Output delay from OE to data high-Z
tDATAZ
IV
34
ns
Output delay from OE to data output
tZDATA
IV
47
ns
Output delay from PCLK to Data output Dxi
Output delay from PCLK to Analog output AVx
8
Min
Typ
FCD4B14
1962C–01/02
FCD4B14
Figure 2. Reset
tHRST
Reset RST
Clock PCLK
tSETUP
Figure 3. Read One Byte/Two Pixels
FPCLK
tHCLK
Clock
PCLK
Acknowledge
tLCLK
tPLHACK
tPHLACKN
ACKN
Data output
Data # N-1
Data # N
Video analog output
AVO, AVE
Data # N+1
tPDATA
Do0-3, De0 -3
Data #N+1
Data #N
Data #N+2
tPAVIDEO
9
1962C–01/02
Figure 4. Output Enable
Output Enable
OE
Data output
Do0-3, De0 -3
Hi-Z
tZDATA
tDATAZ
Data output
Hi-Z
Figure 5. No data change
tNOOE
PCLK
OE
Note:
10
OE must not change during TNOOE after the PCLK falls. This is to ensure that the output drivers of the data is not driving current, to reduce the noise level on the power supply.
FCD4B14
1962C–01/02
FCD4B14
Figure 6. FCD4B14 Block Diagram
clock
PCLK
ACKN
reset
RST
line sel
column selection
even
4-bit
ADC
1 dummy column
1
8 lines of 280 columns of pixels
Functional Description
chip
temperature
sensor
TPE
TPP
8
latches
8
4-bit
ADC
odd
chip temperature
stabilization
De0-3
amp
2240
8
4
Do0-3
4
output
enable
analog
output
AVE AVO
OE
The circuit is divided into two main sections: sensor and data conversion. One particular
column among 280+1 is selected in the sensor array (1), then each pixel of the selected
column sends its electrical information to amplifiers (2) (one per line), then two lines at a
time are selected (odd and even) so that two particular pixels send their information to
the input of two 4-bit Analog-to-Digital Converters (3), so 2 pixels can be read for each
clock pulse (4).
Figure 7. Functional Description
1
2
column selection
line sel
8 lines of 280 columns of pixels
3
even
4-bit
ADC
4
4
8
latches
amp
8
1 dummy column
odd
4-bit
ADC
De0-3
Do0-3
4
chip
temperature
sensor
Sensor
Each pixel is a sensor in itself. The sensor detects a temperature differential between
the beginning of acquisition and the reading of information: this is the integration time.
The integration time begins with a reset of the pixel to a predefined initial state. Note that
the integration time reset has nothing to do with the reset of the digital section.
Then, at a rate depending on the sensitivity of the pyroelectric layer, on the temperature
variation between the reset and the end of the integration time, and on the duration of
the integration time, electrical charges are generated at the pixel level.
11
1962C–01/02
Analog-to-Digital
Converter/
Reconstructing an 8-bit
Fingerprint Image
An Analog-to-Digital Converter (ADC) is used to convert the analog signal coming from
the pixel into digital data that can be used by a processor.
Start Sequence
A reset is not necessary between each frame acquisition!
As the data rate for parallel port and USB is in the range of 1 MB per second and at least
a rate of 500 frames per second is needed to reconstruct the image with a fair sweeping
speed for the finger, two 4-bit ADCs have been used to output 2 pixels at a time on 1
byte.
Start sequence must consist of:
1. Set the RST pin to high
2. Set the RST pin to low
3. Send 4 clock pulses (due to pipe-line)
4. Send clock pulses to skip the first frame
Note that the first frame never contains relevant information because the integration
time is not correct.
Figure 8. Start Sequence
4+1124 clock pulses to skip the first frame
Reset RST
Clock PCLK
1
Reading the Frames
2
3
4
1
1124
1
A frame consists of 280 true columns + 1 dummy column of 8 pixels. As two pixels are
output at a time, a system must send 281x4 = 1124 clock pulses to read one frame.
Reset must be low when reading the frames.
Read One Byte/Output
Enable
Clock is taken into account on the falling edge and data are output on the rising edge.
For each clock pulse, after the start sequence, a new byte is output on the Do0-3, De03 pins. This byte contains 2 pixels: 4-bit on Do0-3 (odd pixels), 4-bit on De0-3 (even
pixels).
To output the data, the output enable (OE) pin must be low. When OE is high, the Do03 and De0-3 pins are in high impedance state. This enables an easy connection to a
microprocessor bus without additional circuitry-it will enable data output by using a chip
select signal. Note that the FCD4B14 is always sending data: there is no data exchange
to perform using read/write mode.
Power Supply Noise
IMPORTANT: When a falling edge is applied on OE (i.e when the Output Enable
becomes active), then some current is drained from the power supply to drive the 8 outputs, producing some noise. It is important to avoid such noise just after the falling edge
of the clock PCLK, when the pixels information is evaluated: the timing diagram figure 5
and time TNOOE defines the interval time where the power supply must be as quiet as
possible.
Video Output
An analog signal is also available on pins AVE and AVO. Note that video output is available one clock pulse before the corresponding digital output (one clock pipe-line delay
for the analog to digital conversion).
12
FCD4B14
1962C–01/02
FCD4B14
Pixel Order
After a reset, pixel number one is located on the upper left corner, looking at the chip
with bond pads to the right. For each column of 8 pixels, pixels 1-3-5-7 are output on
odd data Do0-3 pins, pixels 2-4-6-8 are output on even data De0-3 pins. Most significant
bit is bit #3, least significant is bit #0.
Figure 9. Pixel Order
Pixel #2233 (280,1)
Pixel #1 (1,1)
B ond pads
Pixel #8 (1,8)
Synchronization: The
Dummy Column
Pixel #2240 (280,8)
A dummy column has been added to the sensor to act as a specific pattern to detect the
first pixel. So, 280 true columns + 1 dummy column are read for each frame.
The 4 bytes of the dummy column contain a fixed pattern on the two first bytes, and temperature information on the last two bytes.
Dummy Byte
Odd
Even
Dummy Byte 1 DB1:
111X
0000
Dummy Byte 2 DB2:
111X
0000
Dummy Byte 3 DB3:
rrrr
nnnn
Dummy Byte 4 DB4:
tttt
pppp
Note:
x represents 0 or 1
The sequence 111X0000 111X0000 appears on every frame (exactly every 1124 clock
pulses), so it is an easy pattern to recognize for synchronization purposes.
13
1962C–01/02
Thermometer
The dummy bytes DB3 and DB4 contains some internal and temperature information.
The even nibble nnnn in DB3 can be used to measure an increase (or decrease) of the
chip temperature, using the difference between two measures of the same physical
device. The following table gives values in Kelvin.
nnnn
Decimal
nnnn
Binary
15
1111
11.2
14
1110
8.4
13
1101
7
12
1100
5.6
11
1011
4.2
10
1010
2.8
9
1001
1.4
8
1000
0
7
0111
-1.4
6
0110
-2.8
5
0101
-4.2
4
0100
-5.6
3
0011
-7
2
0010
-8.4
1
0001
-11.2
0
0000
< -16.8
Temperature differential with code 8 in
Kelvin
For code 0 and 15, the absolute value is a minimum (saturation).
When the image contrast becomes low because of a low temperature difference
between the finger and the sensor, it is recommended to use the temperature stabilization circuitry to increase the temperature of two codes (i.e. from 8 to 10), to get at least
an increase >1.4 Kelvin of the sensor. This enables to recover enough contrast to get a
proper fingeprint for recognition purpose.
14
FCD4B14
1962C–01/02
FCD4B14
Integration Time and
Clock Jitter
The FCD4B14 is not very sensitive to clock jitter (clock variation). The most important
requirement is a regular integration time that ensures the frame reading rate is also as
regular as possible, in order to get consistent fingerprint slices.
If the integration time is not regular, contrast will vary from one frame to another.
Note that it is possible to introduce some waiting time between each set of 1124 clock
pulses, but the overall time of one frame read must be regular. This waiting time is generally the time needed by the processor to perform some calculation over the frame (to
detect the finger, for instance).
Figure 10. Read One Frame
Reset RST is low
1
Column 1
2
3
Column 2
4
5
Column 280
6
1119
Dummy Column 281
1120
1121
1122
1123
1124
7&8
DB1
DB2
DB3
DB4
Clock PCLK
Pixels 1 & 2
3&4
5&6
7&8
1&2
3&4
Figure 11. Regular Integration Time
REGULAR INTEGRATION TIME
Frame n
Frame n+1
Frame n+2
Frame n+3
Clock PCLK
1124 pulses
1124 pulses
1124 pulses
1124 pulses
15
1962C–01/02
Power Management
Nap Mode
Several strategies are possible to reduce power consumption when not in use.
The simplest and most efficient is to cut the power supply, using external means.
A nap mode is also implemented in the FCD4B14. To activate this nap mode, user must:
1. Set the reset RST pin to high. Doing this, all analog sections of the device are
internally powered down.
2. Set the clock PCLK pin to high (or low), thus stopping the entire digital section.
3. Set the TPE pin to low or disconnect TPP to stop the temperature stabilization
feature.
4. Set Output Enable OE pin to high, so that output are forced in HiZ.
Figure 12. Nap Mode
Nap mode
Reset RST
Nap
Clock PCLK
In Nap Mode, all internal transistors are in shut mode. Only leakage current is drained in
power supply, generally less than the tested value.
Static Current
Consumption
When the clock is stopped (set to 1) and the reset is low (set to 0), the analog sections
of the device drain some current and the digital section does not consume current if the
outputs are connected to a standard CMOS input (= no current is drained in the I/O). In
this case the typical current value is 5 mA. This current does not depend on the voltage
(i.e. it is almost the same from 3V to 5.5V).
Dynamic Current
Consumption
When the clock is running, the digital sections are consuming current, and particularly
the outputs if they are heavily loaded. In any case, it should be less than the testing
machine (120 pF load on each I/O), 50 pF maximum is recommended.
Connected to a USB interface chip (see application note 26 related to the FCDEMO4
kit) at 5V, and running at about 1 MHz, the FCD4B14 consumes less than 7 mA on VCC
pin.
Temperature
Stabilization Power
Consumption (TPP pin)
When the TPE pin is set to 1, current is drained via the TPP pin. The current is limited by
the internal equivalent resistance given in table 4 and a possible external resistor.
Most of the time, TPE is set to 0 and no current is drained in TPP. When the image contrast becomes low because of a low temperature differential (less than one Kelvin), then
it is recommended to set TPE to 1 during a short time so that the dissipated power in the
chip elevates the temperature, enabling to recover contrast. The necessary time to
increase the chip temperature of one Kelvin depends on the dissipated power, the thermal capacity of the silicon sensor and the thermal resistance between the sensor and
the surroundings.
As a rule of thumb, dissipating 300 mW in the chip elevates the temperature of 1 Kelvin
in one second. With the 30 Ω typical value, 300 mW is 3V applied on TPP.
16
FCD4B14
1962C–01/02
FCD4B14
Packaging:
Mechanical Data
Figure 13. COB: Top View (all dimensions in mm)
0.2 A
+0.07
17.51
-0.01 at 0.4 height from B ref.
0.89 ± 0.3
5.45 ± 0.30
14
2.32 ± 0.5
0.35
5.90 max 2.95 ± 0.50
9.45 ± 0.5*
+ 0.07
1.66
- 0.01 at 0.4 height from B ref.
A
0.83 ± 0.50
0.2 min
5.20 max
26.6 ± 0.25*
*: including burrs
Dam and Fill
B
1.5 max
0.790
max
0.2 max
Figure 14. COB: Bottom View (all dimensions in mm)
1± 0.075
0.5 ± 0.075
1.15 ± 0.15
2.15 ± 0.15
3.5 ± 0.075
1.5 ± 0.075
1 ± 0.15
6.30 ± 0.1
+0.08
(x3)
R0.75
-0.12
2 ± 0.075
2 ± 0.15
0.75
+0.33
-0.25
23.85 ± 0.1
1.5
+0.15
(x3)
-0.23
17
1962C–01/02
1.1 ± 0.1
0.25 max
Figure 15. DIL Package (all dimensions in mm)
0.08
60°
4.75 ± 0.1
0.81 ± 0.05
0.46 ± 0.05
2.54 ± 0.13
0.75 max
18
25.4 ± 0.25
0.08
(0.90)
(0.20)
NO.1
7.87 ± 0.25
9.36 ± 0.15 6.34 ± 0.15
0.1 min
NO.20
NO.11
7.5 ± 0.25
(2.45)
(7.62)
6.5 max
3.15 ± 0.32
0.25 ± 0.05
22.86 ± 0.13
NO.10
5.4 max
FCD4B14
1962C–01/02
FCD4B14
Ordering Information
Package Device
FC
D4B14
C
C
—
Atmel prefix
FingerChip family
Quality level
— : s tandard
Device type
Temperature range
Com: 0° to +70°C
Package
C: DIP Ceramic 20 pins
CB: Chip On Board (COB)
19
1962C–01/02
Atmel Headquarters
Atmel Operations
Corporate Headquarters
Memory
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 487-2600
Atmel Corporate
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 436-4270
FAX 1(408) 436-4314
Europe
Atmel SarL
Route des Arsenaux 41
Casa Postale 80
CH-1705 Fribourg
Switzerland
TEL (41) 26-426-5555
FAX (41) 26-426-5500
Microcontrollers
Atmel Corporate
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 436-4270
FAX 1(408) 436-4314
Atmel Nantes
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
TEL (33) 2-40-18-18-18
FAX (33) 2-40-18-19-60
Asia
Atmel Asia, Ltd.
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimhatsui
East Kowloon
Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
ASIC/ASSP/Smart Cards
Japan
Atmel Japan K.K.
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Atmel Rousset
Zone Industrielle
13106 Rousset Cedex, France
TEL (33) 4-42-53-60-00
FAX (33) 4-42-53-60-01
RF/Automotive
Atmel Heilbronn
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
TEL (49) 71-31-67-0
FAX (49) 71-31-67-2340
Atmel Colorado Springs
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
FAX 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Atmel Grenoble
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
TEL (33) 4-76-58-30-00
FAX (33) 4-76-58-34-80
Atmel Colorado Springs
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
FAX 1(719) 540-1759
Atmel Smart Card ICs
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
TEL (44) 1355-803-000
FAX (44) 1355-242-743
e-mail
[email protected]
Web Site
http://www.atmel.com
© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
ATMEL ® is the registered trademarks of Atmel.
Other terms and product names may be the trademarks of others.
1962C–01/02/xM