PHK12NQ03LT N-channel TrenchMOS™ logic level FET Rev. 02 — 02 March 2004 M3D315 Product data 1. Product profile 1.1 Description N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS™ technology. 1.2 Features ■ Low on-state resistance ■ Fast switching. 1.3 Applications ■ DC-to-DC converters ■ Portable equipment applications. 1.4 Quick reference data ■ VDS ≤ 30 V ■ Ptot ≤ 2.5 W ■ ID ≤ 11.8 A ■ RDSon ≤ 14 mΩ 2. Pinning information Table 1: Pinning - SOT96-1 (SO8), simplified outline and symbol Pin Description 1,2,3 source (s) 4 gate (g) 5,6,7,8 drain (d) Simplified outline 8 Symbol d 5 g 1 Top view 4 MBB076 s MBK187 SOT96-1 (SO8) 3. Ordering information Table 2: Ordering information Type number PHK12NQ03LT Package Name Description Version SO8 Plastic small outline package; 8 leads SOT96 PHK12NQ03LT Philips Semiconductors N-channel TrenchMOS™ logic level FET 4. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit 25 °C ≤ Tj ≤ 150 °C - 30 V - ±20 V VDS drain-source voltage (DC) VGS gate-source voltage ID drain current Tamb = 25 °C; pulsed; tp ≤ 10 s; Figure 2 and 3 - 11.8 A IDM peak drain current Tamb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 - 35.3 A Ptot total power dissipation Tamb = 25 °C; pulsed; tp ≤ 10 s; Figure 1 - 2.5 W Tstg storage temperature −55 +150 °C Tj junction temperature −55 +150 °C Tamb = 25 °C; pulsed; tp ≤ 10 s - 11.8 A unclamped inductive load; ID = 7.7 A; tp = 2.35 ms; VDD ≤ 30 V; VGS = 10 V; starting Tj = 25 °C - 440 mJ Source-drain diode IS source (diode forward) current Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12955 Product data Rev. 02 — 02 March 2004 2 of 12 PHK12NQ03LT Philips Semiconductors N-channel TrenchMOS™ logic level FET 03aa11 120 03aa19 120 Ider (%) Pder (%) 80 80 40 40 0 0 0 50 100 150 200 Tamb (°C) 0 50 100 150 200 Tamb (°C) VGS ≥ 5 V P tot P der = ----------------------- × 100% P ° ID I der = ------------------- × 100% I ° tot ( 25 C ) D ( 25 C ) Fig 1. Normalized total power dissipation as a function of ambient temperature. Fig 2. Normalized continuous drain current as a function of ambient temperature. 003aaa160 102 ID (A) tp = 10 µ s Limit RDSon = VDS / ID 100 µ s 10 1 ms 1 10 ms DC 1s 10-1 10-2 10-1 10 s 1 10 VDS (V) 102 Tamb = 25 °C; IDM is single pulse Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12955 Product data Rev. 02 — 02 March 2004 3 of 12 PHK12NQ03LT Philips Semiconductors N-channel TrenchMOS™ logic level FET 5. Thermal characteristics Table 4: Thermal characteristics Symbol Parameter thermal resistance from junction to ambient Rth(j-a) Conditions Min Typ Max Unit mounted on a printed-circuit board; minimum footprint; tp ≤ 10 s; Figure 4 - - 50 K/W 5.1 Transient thermal impedance 003aaa161 102 Zth(j-amb) δ = 0.5 (K/W) 0.2 10 0.1 0.05 0.02 1 single pulse 10-1 10-4 10-3 10-2 10-1 1 10 tp (s) 102 Fig 4. Transient thermal impedance from junction to ambient as a function of pulse duration. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12955 Product data Rev. 02 — 02 March 2004 4 of 12 PHK12NQ03LT Philips Semiconductors N-channel TrenchMOS™ logic level FET 6. Characteristics Table 5: Characteristics Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit ID = 250 µA; VGS = 0 V 30 - - V 1 - 2 V Tj = 25 °C - - 1 µA Tj = 100 °C - - 5 µA Static characteristics V(BR)DSS drain-source breakdown voltage VGS(th) gate-source threshold voltage ID = 250 µA; VDS = VGS; Tj = 25 °C; Figure 9 IDSS drain-source leakage current VDS = 24 V; VGS = 0 V IGSS gate-source leakage current VGS = ±20 V; VDS = 0 V - 100 nA RDSon drain-source on-state resistance VGS = 4.5 V; ID = 10 A; Figure 8 - 11 14 mΩ VGS = 10 V; ID = 12 A; Figure 8 - 8.9 10.5 mΩ Dynamic characteristics gfs forward transconductance VDS = 15 V; ID = 10 A; - 34 - S Qg(tot) total gate charge ID = 15 A; VDD = 16 V; VGS = 5 V; Figure 13 - 17.6 - nC Qgs gate-source charge - 4 - nC Qgd gate-drain (Miller) charge - 4.4 - nC Ciss input capacitance - 1335 - pF Coss output capacitance - 391 - pF Crss reverse transfer capacitance - 190 - pF td(on) turn-on delay time - 10.6 - ns tr rise time - 11.7 - ns td(off) turn-off delay time - 37 - ns tf fall time - 19 - ns VGS = 0 V; VDS = 16 V; f = 1 MHz; Figure 11 VDD = 16 V; RD = 10 Ω; VGS = 10 V Source-drain (reverse) diode VSD source-drain (diode forward) voltage IS = 1 A; VGS = 0 V; Figure 12 trr reverse recovery time IS = 2.3 A; dIS/dt = −100 A/µs; VGS = 0 V 0.7 1.0 V 70 - ns © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12955 Product data - Rev. 02 — 02 March 2004 5 of 12 PHK12NQ03LT Philips Semiconductors N-channel TrenchMOS™ logic level FET 003aaa162 16 5V 003aaa163 20 4V ID (A) VDS > ID x RDSon ID (A) 12 15 2.8 V 10 8 2.5 V 4 5 Tj = 25 °C 150 °C VGS = 2.2 V 0 0 0 0.2 0.4 0.6 0 0.8 1 VDS (V) Tj = 25 °C 2 3 VGS (V) 4 Tj = 25 °C and 150 °C; VDS > ID × RDSon Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values. 003aaa164 03aa27 2 0.1 2.8 V VGS = 2.5 V RDSon 1 a (Ω) 0.08 1.5 0.06 1 0.04 0.5 4V 0.02 5V 0 0 0 4 8 12 ID (A) 16 Tj = 25 °C -60 60 120 Tj (°C) 180 R DSon a = ----------------------------R DSon ( 25°C ) Fig 7. Drain-source on-state resistance as a function of drain current; typical values. Fig 8. Normalized drain source on-state resistance factor as a function of junction temperature. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12955 Product data 0 Rev. 02 — 02 March 2004 6 of 12 PHK12NQ03LT Philips Semiconductors N-channel TrenchMOS™ logic level FET 03aa33 2.5 VGS(th) max ID (A) 10-2 typ 10-3 (V) 2 1.5 03ai52 10-1 min min 1 10-5 0 10-6 0 max 10-4 0.5 -60 typ 60 120 Tj (°C) 180 ID = 250 µA; VDS = VGS 0 1 2 3 VGS (V) Tj = 25 °C; VDS = 5 V Fig 9. Gate-source threshold voltage as a function of junction temperature. 003aaa165 104 Fig 10. Sub-threshold drain current as a function of gate-source voltage. 003aaa166 20 VGS = 0 V IS (A) C (pF) 15 Ciss 103 10 Coss 5 150 °C Tj = 25 °C Crss 102 10-1 0 1 10 VDS (V) 102 0.4 0.8 VSD (V) 1 Tj = 25 °C and 150 °C; VGS = 0 V VGS = 0 V; f = 1 MHz Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values. Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12955 Product data 0.6 Rev. 02 — 02 March 2004 7 of 12 PHK12NQ03LT Philips Semiconductors N-channel TrenchMOS™ logic level FET 003aaa167 10 VGS (V) 8 6 4 2 0 0 10 20 30 40 QG (nC) ID = 15 A; VDD = 16 V Fig 13. Gate-source voltage as a function of gate charge; typical values. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12955 Product data Rev. 02 — 02 March 2004 8 of 12 PHK12NQ03LT Philips Semiconductors N-channel TrenchMOS™ logic level FET 7. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 inches 0.010 0.057 0.069 0.004 0.049 0.05 0.244 0.039 0.028 0.041 0.228 0.016 0.024 0.01 0.01 0.028 0.004 0.012 θ o 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 14. SOT96-1 (SO8). © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12955 Product data Rev. 02 — 02 March 2004 9 of 12 PHK12NQ03LT Philips Semiconductors N-channel TrenchMOS™ logic level FET 8. Revision history Table 6: Revision history Rev Date 02 20040302 CPCN Description - Product data (9397 750 12955) Modifications • • • • • • • • 01 20020322 - Data sheet updated to latest presentation standards. Section 1.4 “Quick reference data” correction to ID value. Section 4 “Limiting values” ID, IDM, Ptot and IS conditions and values corrected. Section 4 “Limiting values” Figure 1, 2 and 3 corrected. Section 4 “Limiting values” EDS(AL)S added. Section 5 “Thermal characteristics” typ and max values corrected. Section 5 “Thermal characteristics” Figure 4 corrected. Section 6 “Characteristics” Figure 13 corrected. Product data (9397 750 09405) © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12955 Product data Rev. 02 — 02 March 2004 10 of 12 PHK12NQ03LT Philips Semiconductors N-channel TrenchMOS™ logic level FET 9. Data sheet status Level Data sheet status[1] Product status[2][3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 10. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 12. Trademarks TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V. 11. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: [email protected]. Product data Fax: +31 40 27 24825 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12955 Rev. 02 — 02 March 2004 11 of 12 Philips Semiconductors PHK12NQ03LT N-channel TrenchMOS™ logic level FET Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 5.1 6 7 8 9 10 11 12 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Transient thermal impedance . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 © Koninklijke Philips Electronics N.V. 2004. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 02 March 2004 Document order number: 9397 750 12955