MAXIM MAX100

19-0282; Rev 0; 7/94
IT
K
ATION
EVALU
BLE
AVAILA
250Msps, 8-Bit ADC with Track/Hold
____________________________Features
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
250Msps Conversion Rate
6.8 Effective Bits at 125MHz
Less than ±1/2LSB INL
50Ω Differential or Single-Ended Inputs
±270mV Input Signal Range
Reference Sense Inputs
Ratiometric Reference Inputs
Configurable Dual-Output Data Paths
Latched, ECL-Compatible Outputs
Low Error Rate, Less than 10-15 Metastable States
Selectable On-Chip 8:16 Demultiplexer
84-Pin Ceramic Flat Pack
________________________Applications
High-Speed Digital Instrumentation
High-Speed Signal Processing
Medical Systems
Radar/Sonar
High-Energy Physics
Communications
______________Ordering Information
PART
TEMP. RANGE
MAX100CFR* 0°C to +70°C
PIN-PACKAGE
84 Ceramic Flat Pack (with heatsink)
*Contact factory for 84-Pin Ceramic Flat Pack without heatsink.
_________________________________________________________Functional Diagram
VART VARTS
VACT VACTS
VARBS VARB
8
AIN+
AIN-
8
FLASH CONVERTER
TRACK/
HOLD
8
CLK
MODE
CONTROL
CLK
MOD
DIV
A=B
L
A
T
C
H
E
S
B
U
F
F
E
R
L
A
T
C
H
E
S
AData
(A0–A7)
DCLK
DCLK
BData
(B0–B7)
________________________________________________________________ Maxim Integrated Products
Call toll free 1-800-998-8800 for free literature.
1
MAX100
_______________General Description
The MAX100 ECL-compatible, 250Msps, 8-bit analog-todigital converter (ADC) allows accurate digitizing of analog signals from DC to 125MHz (Nyquist frequency).
Designed with Maxim’s proprietary advanced bipolar
processes, the MAX100 contains a high-performance
track/hold (T/H) amplifier and a quantizer in a single
ceramic strip-line package.
The innovative design of the internal T/H assures an
exceptionally wide input bandwidth of 1.2GHz and aperture delay uncertainty of less than 2ps, resulting in a high
6.8 effective bits performance. Special comparator output
design and decoding circuitry reduce out-of-sequence
code errors. The probability of erroneous codes occurring
due to metastable states is reduced to less than 1 error
per 1015 clock cycles. Unlike other ADCs, which can
have errors that result in false full-scale or zero-scale outputs, the MAX100 keeps the magnitude to less than 1LSB.
The analog input is designed for either differential or singleended use with a ±270mV range. Sense pins for the reference input allow full-scale calibration of the input range or
facilitate ratiometric use. Midpoint tap for the reference
string is available for applications that need to modify the
output coding for a user-defined bilinear response. Use of
separate high-current and low-current ground pins provides better noise immunity and highest device accuracy.
Dual output data paths provide several data output modes
for easy interfacing. These modes can be configured as
either one or two identical latched ECL outputs. An 8:16
demultiplexer mode that reduces the output data rates to
one-half the clock rate is also available.
For applications that require faster data rates, refer to
Maxim’s MAX101, which allows conversion rates up to
500Msps.
MAX100
250Msps, 8-Bit ADC with Track/Hold
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltages
VCC .............................................................................0V to +7V
VEE ...............................................................................-7V to 0V
VCC - VEE............................................................................+12V
Analog Input Voltage .............................................................±2V
Digital Input Voltage .................................................-2.3V to +0V
Reference Voltage (VART) .....................................-0.3V to +1.5V
Reference Voltage (VARB).....................................-1.5V to +0.3V
Data Output Current ..........................................................-33mA
DCLK Output Current ........................................................-43mA
Operating Temperature Range...............................0°C to +70°C
Operating Junction Temperature (Note 2)............0°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+250°C
Note 1: The digital control inputs are diode protected; however, permanent damage may occur on unconnected units under highenergy electrostatic fields. Keep unused units in conductive foam or shunt the terminals together. Discharge the conductive foam to the destination socket before insertion.
Note 2: Typical thermal resistance, junction-to-case RθJC = 5°C/W and thermal resistance, junction to ambient (MAX100CA) RθJA =
12°C/W, providing 200 lineal ft/min airflow with heatsink. See Package Information.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VEE = -5.2V, VCC = +5V, RL = 50Ω to -2V, VART = 1.02V, VARB = -1.02V, TMIN to TMAX = 0°C to +70°C, TA = +25°C, unless
otherwise noted.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY
Resolution
8
Integral Nonlinearity (Note 4)
INL
AData, BData
Differential Nonlinearity
DNL
AData, BData,
no missing codes
TA = +25°C
TA = TMIN to TMAX
TA = +25°C
TA = TMIN to TMAX
fCLK = 250MHz,
VIN = 95% full scale
(Note 5)
fAIN = 10MHz
fAIN = 50MHz
fAIN = 125MHz
Bits
±0.5
±0.6
±0.75
±0.85
LSB
LSB
DYNAMIC SPECIFICATIONS
Effective Bits
Signal-to-Noise Ratio
Maximum Conversion Rate
Analog Input Bandwidth
Aperture Width
Aperture Jitter
ANALOG INPUT
ENOB
SNR
fCLK
BW3dB
tAW
tAJ
Input Voltage Range
VIN
Input Offset Voltage
Least-Significant-Bit Size
Input Resistance
VIO
LSB
RI
Input Resistance
Temperature Coefficient
2
7.4
7.1
fAIN = 50MHz, fCLK = 250MHz, VIN = 95%
full scale (Note 6)
(Note 7)
Full scale
Zero scale
AIN+, AIN-, TA = TMIN to TMAX
TA = TMIN to TMAX
AIN+ and AIN- with respect to GND
44.5
dB
1.2
270
2
Msps
GHz
ps
ps
250
Figure 5
Figure 5
AIN+ to AIN-, Table 2,
TA = TMIN to TMAX
Bits
6.8
230
-305
-17
1.8
49
315
-215
+32
2.5
51
0.008
_______________________________________________________________________________________
mV
mV
mV
Ω
Ω/°C
250Msps, 8-Bit ADC with Track/Hold
(VEE = -5.2V, VCC = +5V, RL = 50Ω to -2V, VART = 1.02V, VARB = -1.02V, TMIN to TMAX = 0°C to +70°C, TA = +25°C, unless
otherwise noted.) (Note 3)
PARAMETER
REFERENCE INPUT
Reference String Resistance
SYMBOL
RREF
CONDITIONS
VART to VARB
MIN
TYP
116
Reference String Resistance
Temperature Coefficient
MAX
UNITS
175
Ω
Ω/°C
0.02
LOGIC INPUTS
Digital Input Low Voltage
(Note 8)
VIL
DIV, MOD, A=B, CLK, CLK,
TA = TMIN to TMAX
Digital Input High Voltage
(Note 8)
VIH
DIV, MOD, A=B, CLK, CLK,
TA = TMIN to TMAX
Digital Input Low Current
IIL
Digital Input High Current
IIH
-1.5
-1.07
V
V
DIV, MOD, A=B = -1.8V, TA = TMIN to TMAX
-5
20
CLK, CLK, VIL = -1.8V (no termination),
TA = TMIN to TMAX
0
80
DIV, MOD, A=B = -0.8V, TA = TMIN to TMAX
-5
20
CLK, CLK, VIH = -0.8V (no termination),
TA = TMIN to TMAX
0
80
µA
µA
LOGIC OUTPUTS (Note 9)
Digital Output Low Voltage
VOL
AData, BData,
DCLK, DCLK
TA = +25°C
-1.95
-1.60
TA = TMIN to TMAX
-1.95
-1.50
Digital Output High Voltage
VOH
AData, BData,
DCLK, DCLK
TA = +25°C
-1.02
-0.70
TA = TMIN to TMAX
-1.10
-0.70
Positive Supply Current
ICC
VCC = 5.0V
Negative Supply Current
IEE
VEE = -5.2V
V
V
POWER REQUIREMENTS
Common-Mode Rejection Ratio
Power-Supply Rejection Ratio
CMRR
PSRR
VINCM = ±0.5V
TA = TMIN to TMAX
TA = +25°C
464
TA = TMIN to TMAX
670
710
TA = +25°C
-750
TA = TMIN to TMAX
-780
TA = TMIN to TMAX
35
VCC(nom) = ±0.25V
40
VEE(nom) = ±0.25V
40
-560
mA
mA
dB
dB
_______________________________________________________________________________________
3
MAX100
ELECTRICAL CHARACTERISTICS (continued)
TIMING CHARACTERISTICS
(VEE = -5.2V, VCC = +5V, RL = 50Ω to -2V, VART = 1.02V, VARB = -1.02V, TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
Clock Pulse Width Low
Clock Pulse Width High
tPWL
tPWH
CLK to DCLK
Propagation Delay
tPD1
DCLK to A/BData
Propagation Delay
tPD2
Rise Time
tR
Fall Time
tF
Pipeline Delay
(Latency)
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
tNPD
CONDITIONS
MIN
CLK, CLK, Figures 1 and 2
CLK, CLK, Figures 1 and 2
DIV = 0, Figure 1
DIV = 1, Figure 2
DIV = 0, Figure 1
DIV = 1, Figure 2
DCLK
20% to 80%
DATA
DCLK
20% to 80%
DATA
1.9
1.9
0.8
1.9
0.5
-1.4
TYP
MAX
UNITS
5.0
ns
ns
See Figures 3 and 4
and Table 1 (delay
depends on output
mode)
Divide-by-1 mode
7 1/2
7 1/2
Divide-by- AData
2 mode
BData
7 1/2
8 1/2
7 1/2
8 1/2
2.4
5.7
2.2
-0.1
500
700
600
550
ns
ns
ps
ps
Clock
Cycles
All devices are 100% production tested at +25°C and are guaranteed by design for TA = TMIN to TMAX as specified.
Deviation from best-fit straight line. See Integral Nonlinearity section.
See the Signal-to-Noise Ratio and Effective Bits section in the Definitions of Specifications.
SNR calculated from effective bits performance using the following equation: SNR (dB) = 1.76 + (6.02) (effective bits).
Clock pulse width minimum requirements tPWL and tPWH must be observed to achieve stated performance.
Functionality guaranteed for -1.07 ≤ VIH ≤ -0.7 and -2.0 ≤ VIL ≤ -1.5.
Outputs terminated through 50Ω to -2.0V.
__________________________________________Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
0.75
0.75
0.50
0.50
0.25
0.25
DNL (LSBs)
INL (LSBs)
MAX100
250Msps, 8-Bit ADC with Track/Hold
0
-0.25
-0.25
-0.50
-0.50
-0.75
-0.75
0
64
128
OUTPUT CODE
4
0
192
256
0
64
128
192
OUTPUT CODE
_______________________________________________________________________________________
256
250Msps, 8-Bit ADC with Track/Hold
FFT PLOT (fAIN = 10.4462MHz)
FFT PLOT (fAIN = 120.4462MHz)
-20
-30
SIGNAL AMPLITUDE (dB)
SIGNAL AMPLITUDE (dB)
0
-10
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125
12.5
fCLK = 250MHz, fAIN = 120.4462MHz
SER = -42.3dB, NOISE FLOOR = -65.4dB
62.5
EFFECTIVE BITS
vs. CLOCK FREQUENCY
7
MAX100-11
8
MAX100-10
8
7
6
6
EFFECTIVE BITS
5
4
3
2
4
3
2
fCLK = 250MHz,
VIN = 95% FS
1
5
fAIN = 10.4MHz,
VIN = 95% FS
1
0
0
0
50
100
200
150
250
300
0
50
100
150
200
250 300
fAIN (MHz)
fCLK (MHz)
EFFECTIVE BITS
vs. ANALOG INPUT FREQUENCY
EFFECTIVE BITS
vs. ANALOG INPUT FREQUENCY
8
MAX100-12
8
7
MAX100-13
EFFECTIVE BITS
50
fCLK = 250MHz, fAIN = 10.4462MHz
SER = -45.87dB, NOISE FLOOR = -68.5dB
EFFECTIVE BITS
vs. ANALOG INPUT FREQUENCY
7
6
6
EFFECTIVE BITS
EFFECTIVE BITS
37.5
25
FREQUENCY (MHz)
FREQUENCY (MHz)
5
4
3
2
4
3
2
TCASE = +80°C,
fCLK = 250MHz,
VIN = 95% FS
1
5
TCASE = -15°C,
fCLK = 250MHz
VIN = 95% FS
1
0
0
0
50
100
150
fAIN (MHz)
200
250
0
50
100
150
200
250
fAIN (MHz)
_______________________________________________________________________________________
5
MAX100
____________________________Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX100
250Msps, 8-Bit ADC with Track/Hold
____________________________Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
DIGITAL CLOCK
(POSITIVE EDGE)
CLOCK RELATIONSHIP
(DIVIDE-BY-1 MODE)
A
DCLK
100mV/div
B
A = CLK, 200mV/div
B = DCLK, 200mV/div
TIMEBASE = 1ns/div,
fCLK = 250MHz
CLOCK/DATA
(DIVIDE-BY-1 MODE)
TIMEBASE = 1ns/div, tr = 580ps
DATA OUTPUT
(NEGATIVE EDGE)
A
AData
OUTPUT
B
100mV/div
C
A = CLK, 500mV/div
B = DCLK, 500mV/div
C = AData, 500mV/div
TIMEBASE = 2ns/div,
fCLK = 250MHz
CLOCK/DATA
(DIVIDE-BY-2 MODE)
TIMEBASE = 1ns/div, tf = 596ps
CLOCK/DATA DETAIL
(DIVIDE-BY-5 MODE)
A
A
B
B
C
A = CLK, 500mV/div
B = DCLK, 500mV/div
C = AData, 500mV/div
6
TIMEBASE = 2ns/div,
fCLK = 250MHz
A = DCLK, 200mV/div
B = AData, 200mV/div
TIMEBASE = 5ns/div,
fCLK = 250MHz
_______________________________________________________________________________________
250Msps, 8-Bit ADC with Track/Hold
PIN
NAME
1
PAD
Internal connection, leave open.
FUNCTION
2, 62
CLK
3, 61
CLK
Complementary Differential Clock Inputs. Can be driven from standard 10K ECL with the following
considerations: Internally, pins 2 & 62 and 3 & 61 are the ends of a 50Ω transmission line. Either end
can be driven, with the other end terminated with 50Ω to -2V. See Typical Operating Circuit.
4, 7, 15, 49,
57, 60, 64,
67, 70, 71,
74, 77, 78,
79, 82, 84
GND
Power-Supply Ground. Connect GND and DGND pins (Note 10).
5, 6, 9, 10,
31, 33, 35,
48, 58, 59,
63, 81, 83
N.C.
No Connect—there is no internal connection to these pins.
8, 21, 43, 56
VCC
Positive power supply, +5V ±5% nominal
11
DIV
Divide Enable Input. DIV and MOD select the output modes. See Table 1.
12
MOD
Modulus. MOD and DIV select the output modes. See Table 1.
13
DCLK
14
DCLK
Complementary Differential Clock Outputs. Used to synchronize following circuitry: AData and BData
outputs are valid tPD2 after the rising edge of DCLK. See Figures 1–4.
16
A=B
17, 20, 23,
26, 36, 39,
42, 45
Sets AData equal to BData when asserted (A=B = 1). See Table 1.
A7–A0
19, 22, 25,
28, 38, 41,
44, 47
B7–B0
18, 24, 27,
30, 34, 37,
40, 46
DGND
29
SUB
Circuit Substrate Contact. This pin must be connected to VEE.
32, 69, 80
VEE
Negative Power Supply, -5.2V ±5% nominal
50
VART
Positive Reference Voltage Input (Note 11)
51
VARTS
Positive Reference Voltage Sense (Note 11)
AData and BData Outputs. A0 and B0 are the LSBs, and A7 and B7 are the MSBs. AData and BData
outputs conform to standard 10K ECL logic swings and drive 50Ω transmission lines. Terminate with
50Ω to -2V. See Figures 1–4.
Power-Supply Ground. Connect all ground (GND, DGND) pins together, as described in Note 10.
_______________________________________________________________________________________
7
MAX100
______________________________________________________________Pin Description
MAX100
250Msps, 8-Bit ADC with Track/Hold
_________________________________________________Pin Description (continued)
PIN
NAME
52
VACTS
Reference Bias Resistor Center-Tap Sense (Note 12)
53
VACT
Reference Bias Resistor Center Tap (Note 12)
54
VARBS
Negative Reference Voltage Sense (Note 11)
55
VARB
Negative Reference Voltage Input (Note 11)
65
TP3
Internal node. Do not connect.
66
TP2
Internal node. Do not connect.
Internal connection. This pin must be connected to GND.
68
TP1
72, 73
AIN+
75, 76
AIN-
Note 10:
Note 11:
Note 12:
FUNCTION
Analog Inputs, internally terminated with 50Ω to ground. Full-scale linear input range is approximately
±270mV. Drive AIN+ and AIN- differentially for best high-frequency performance.
Use a multilayer board with a separate layer dedicated to ground. Connect GND and DGND in separate areas in the
ground plane (separated by at least 1/4 inch) and at only one location on the board (see Typical Operating Circuit).
Reference bias supply. Use a separate high-quality supply for these pins. Carefully bypassing these pins to achieve
noise-free operation of the reference supplies contributes directly to high ADC accuracy.
The center-tap connection of the MAX100 is normally left open. It can be driven with a bias voltage, but should be
bypassed carefully (refer to Note 11).
CLK
CLK
DCLK
DCLK
AData
BData
tpd1
tpwl
tpd2
tpwh
Figure 1. Output Timing: Divide-by-1 Mode (DIV = 0)
8
_______________________________________________________________________________________
250Msps, 8-Bit ADC with Track/Hold
MAX100
CLK
CLK
DCLK
DCLK
AData
BData
tpd1
tpd2
tpwl
tpwh
Figure 2. Output Timing: Divide-by-2 or Divide-by-5 Mode (DIV = 1)
N-1
CLK
N
N+1
1
DCLK
2
3
4
5
6
7
AData
BData
8
N-1
N
N+1
N-1
N
N+1
tpd2
tpd1
tNPD
Figure 3. Output Timing: Clock to Data, Divide-by-1 Mode (fast mode, DIV = 0)
N-2
N-1
N
N+1
N+2
CLK
1
2
3
4
5
DCLK
AData
BData
N-1
N+1
N+3
N-2
N
N+2
tpd2
tNPD
Figure 4. Output Timing: Divide-by-2 Mode (DIV = 1)
_______________________________________________________________________________________
9
MAX100
250Msps, 8-Bit ADC with Track/Hold
______Definitions of Specifications
Signal-to-Noise Ratio and Effective Bits
Signal-to-noise ratio (SNR) is the ratio between the RMS
amplitude of the fundamental input frequency and the
RMS amplitude of all other analog-to-digital (A/D) output
signals. The theoretical minimum A/D noise is caused by
quantization error and is a direct result of the ADC’s resolution: SNR = (6.02N + 1.76)dB, where N is the number
of effective bits of resolution. Therefore, a perfect 8-bit
ADC can do no better than 50dB. The FFT plots in the
Typical Operating Characteristics show the output level in
various spectral bands.
Effective bits is calculated from a digital record taken from
the ADC under test. The quantization error of the ideal
converter equals the total error of the device. In addition
to ideal quantization error, other sources of error include
all DC and AC nonlinearities, clock and aperture jitter,
missing output codes, and noise. Noise on references
and supplies also degrades effective bits performance.
The ADC’s input is a sine wave filtered with an anti-aliasing filter to remove any harmonic content. The digital
record taken from this signal is compared against a
mathematically generated sine wave. DC offsets, phase,
and amplitudes of the mathematical model are adjusted
until a best-fit sine wave is found. After subtracting this
sine wave from the digital record, the residual error
remains. The rms value of the error is applied in the following equation to yield the ADC’s effective bits.
Effective bits = N - log2
(
measured rms error
—————————
ideal rms error
)
where N is the resolution of the converter. In this case,
N = 8.
The worst-case error for any device will be at the converter’s maximum clock rate with the analog input near
the Nyquist rate (1/2 the input clock rate).
Aperture Width and Jitter
Aperture width is the time the T/H circuit takes to disconnect the hold capacitor from the input circuit (i.e., to
turn off the sampling bridge and put the T/H in hold
mode). Aperture jitter is the sample-to-sample variation
in aperture delay (Figure 5).
Error Rates
Errors resulting from metastable states may occur when
the analog input voltage, at the time the sample is
taken, falls close to the decision point for any one of the
input comparators. The resulting output code for many
10
CLK
CLK
tAW
ANALOG
INPUT
tAD
tAJ
SAMPLED
DATA (T/H)
TRACK
HOLD
TRACK
T/H
APERTURE DELAY (tAD)
APERTURE WIDTH (tAW)
APERTURE JITTER (tAJ)
Figure 5. T/H Aperture Timing
typical converters can be incorrect, including false fullor zero-scale output. The MAX100’s unique design
reduces the magnitude of this type of error to 1LSB,
and reduces the probability of the error occurring to
less than one in every 10 15 clock cycles. If the
MAX100 were operated at 250MHz, 24 hours a day,
this would translate to less than one metastable-state
error every 46 days.
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the transfer
function from a reference line measured in fractions of
1LSB using a “best straight line” determined by a least
square curve fit.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
the measured LSB step and an ideal LSB step size
between adjacent code transitions. DNL is expressed
in LSBs and is calculated using the following equation:
[VMEAS - (VMEAS-1)] - LSB
DNL(LSB) = —————————————
LSB
where VMEAS-1 is the measured value of the previous
code.
A DNL specification of less than 1LSB guarantees no
missing codes and a monotonic transfer function.
______________________________________________________________________________________
250Msps, 8-Bit ADC with Track/Hold
Converter Operation
The parallel or “flash” architecture used by the MAX100
provides the fastest multibit conversion of all common
integrated ADC designs. The basic element of a flash
(as with all other ADC architectures) is the comparator,
which has a positive input, a negative input, and an
output. If the voltage at the positive input is higher than
the negative input (connected to a reference), the output will be high. If the positive input voltage is lower
than the reference, the output will be low. A typical nbit flash consists of 2n-1 comparators with negative
inputs evenly spaced at 1LSB increments from the bottom to the top of the reference ladder. For n = 8, there
will be 255 comparators.
For any input voltage, all the comparators with negative
inputs connected to the reference ladder below the
input voltage will have outputs of 1, and all comparators with negative inputs above the input voltage will
have outputs of 0. Decode logic is provided to convert
this information into a parallel n-bit digital word (the output) corresponding to the number of LSBs (minus 1)
that the input voltage is above the level set at the bottom of the ladder.
Finally, the comparators contain latch circuitry and are
clocked. This allows the comparators to function as
described above when, for example, clock is low.
When clock goes high (samples) the comparator will
latch and hold its state until the clock goes low again.
Track/Hold
As with all ADCs, if the input waveform is changing
rapidly during the conversion the effective bits and
SNR will decrease. The MAX100 has an internal
track/hold (T/H) that increases attainable effective-bits
performance and allows more accurate capture of analog data at high conversion rates.
The internal T/H circuit provides two important circuit
functions for the MAX100:
1) Its nominal voltage gain of 4 reduces the input driving signal to ±270mV differential (assuming a
±1.02V reference).
2) It provides a differential 50Ω input that allows easy
interface to the MAX100.
Data Flow
The MAX100 contains an internal T/H amplifier that
stores the analog input voltage for the ADC to convert.
The differential inputs AIN+ and AIN- are tracked continuously between data samples. When a negative CLK
edge is applied, the T/H enters hold mode (Figure 5).
When CLK goes low, the most recent sample is presented to the ADC’s input comparators. Internal processing of the sampled data is delayed for several
clock cycles before it is available at outputs AData or
BData. All output data is timed with respect to DCLK
and DCLK (Figures 1–4).
__________Applications Information
Analog Input Ranges
Although the normal operating range is ±270mV, the
MAX100 can be operated with up to ±500mV on each
input with respect to ground. This extended input level
includes the analog signal and any DC common-mode
voltage.
To obtain a full-scale digital output with differential input
drive, a nominal +270mV must be applied between
AIN+ and AIN-. That is, AIN+ = +135mV and AIN- =
-135mV (with no DC offset). Mid-scale digital output
code occurs when there is no voltage difference across
the analog inputs. Zero-scale digital output code, with
differential -270mV drive, occurs when AIN+ = -135mV
and AIN- = +135mV. Table 2 shows how the output of
the converter stays at all ones (full scale) when over
ranged or all zeros (zero scale) when under ranged.
For single-ended operation:
1) Apply a DC offset to one of the analog inputs, or
leave one input open. (Both AIN+ and AIN- are terminated internally with 50Ω to analog ground.)
2) Drive the other input with a ±270mV + offset to
obtain either full- or zero-scale digital output. If a DC
common-mode offset is used, the total voltage swing
allowed is ±500mV (analog signal plus offset with
respect to ground).
Table 1. Input Voltage Range
INPUT
Differential
Single
Ended
AIN+**
(mV)
AIN-**
(mV)
+135
0
-135
+270
0
-270
-135
0
+135
0
0
0
OUTPUT
CODE
11111111
10000000
00000000
11111111
10000000
00000000
MSB to LSB
full scale
mid scale
zero scale
full scale
mid scale
zero scale
**An offset VIO, as specified in the DC electrical parameters, may
be present at the input. Compensate for this offset by either
adjusting the reference voltage (VART or VARB), or introducing an
offset voltage in one of the input terminals AIN + or AIN-.
______________________________________________________________________________________
11
MAX100
_______________Detailed Description
MAX100
250Msps, 8-Bit ADC with Track/Hold
Table 2. Output Mode Control
DIV
0
0
1
MOD
X
X
0
A=B
0
1
0
DCLK*
(MHz)
MODE
250
Divide
by 1
Data appears on
AData only, BData
port inactive
(Figure 3).
Divide
by 1
AData identical to
BData (Figure 3).
Divide
by 2
8:16 demultiplexer
mode. AData
and BData ports
are active. BData
carries older
sample and
AData carries
most recent sample (Figure 4).
Divide
by 2
AData and BData
ports are active,
both carry identical sampled data.
Alternate samples
are taken but discarded.
250
125
POSITIVE
REFERENCE
DESCRIPTION
VART
PARASITIC
RESISTANCE
VARTS
R
R
TO
COMPARATORS
R/2
1
1
1
0
1
1
1
0
1
125
50
50
Divide
by 5
AData port
updates data on
5th input CLK.
BData port inactive. Other 4 sampled data points
are discarded.
Divide
by 5
AData and BData
ports are both
active with identical data. Data is
updated on output ports every
5th input clock
(CLK). The other
4 samples are
discarded.
VACT
VACTS
CENTER TAP
R/2
R
R
VARBS
PARASITIC
RESISTANCE
VARB
–——–
*Input clocks (CLK, CLK) = 250MHz for all above combinations.
In divide-by-2 or divide-by-5 mode the output clock DCLK will
always be a 50% duty-cycle signal. In divide-by-1 mode DCLK
will have the same duty cycle as CLK.
NEGATIVE
REFERENCE
Figure 6. Reference Ladder String
12
______________________________________________________________________________________
250Msps, 8-Bit ADC with Track/Hold
CLK and DCLK
All input and output clock signals are differential. The
input clocks, CLK and CLK, are the primary timing signals for the MAX100. CLK and CLK are fed to the internal circuitry from pins 2 & 3 or pins 62 & 61 through an
internal 50Ω transmission line. One pair of CLK/CLK
inputs should be driven and the other pair terminated
by 50Ω to -2V. Either pair can be used as the driven
inputs (input lines are balanced) for easy circuit connection. A minimum pulse width (tPWL) is required for
CLK and CLK (Figures 1–4).
For best performance and consistent results, use a low
phase-jitter clock source for CLK and CLK. Phase jitter
larger than 2ps from the input clock source reduces the
converter’s effective-bits performance and causes
inconsistent results.
DCLK and DCLK are output clock signals derived from
the input clocks and are used for external timing of the
AData and BData outputs. The MAX100 is characterized to work with maximum input clock frequencies of
250MHz (Table 1). See Typical Operating Circuit.
Output Mode Control
DIV, MOD, and A=B are input pins that determine the
operating mode of the two output data paths. Six
options are available (Table 1). A typical operating configuration (8:16 demultiplexer mode) is set by 1 on DIV,
0 on MOD, and 0 on A=B. This will give the most
recent sample at AData with the older data on BData.
Both outputs are synchronous and are at half the input
clock rate. To terminate the control inputs, use a resistor to -2V or the equivalent circuit resistor combination
from DGND to -5.2V up to 1kΩ. When using a diode
pull-up to tie an input high, bias the diode “on” with a
pull-down resistor to avoid input voltage excursions
close to ground. The control inputs are compatible with
standard ECL 10K logic levels over temperature.
Layout, Grounding, and Power Supplies
The MAX100 is designed with separate analog and digital ground connections to isolate high-current digital
noise spikes. The high-current digital ground, DGND,
is connected to the collectors of the output emitter follower transistors. The low-current ground connection is
GND, which is a combination of the analog ground and
the ground of the low-current digital decode section.
The DGND and GND connections should be at the
same DC level, and should be connected at only one
location on the board. This will provide better noise
immunity and highest device accuracy. A ground
plane is recommended.
A +5V ±5% supply as well as a -5.2V ±5% supply is
needed for proper operation. Bypass the VEE and
VCC supply pins to GND with high-quality 0.1µF and
0.001µF ceramic capacitors located as close to the
package as possible. An evaluation kit with a suggested layout is available.
______________________________________________________________________________________
13
MAX100
Reference
The ADC’s reference resistor is a Kelvin-sensed, centertapped resistor string that sets the ADC’s LSB size and
dynamic operating range. Normally, the top and bottom of
this string are driven with an op amp, and the center tap is
left open. However, driving the center tap is an effective
way to modify the output coding to provide a user-defined
bilinear response. The buffer amplifier used to drive the
top and bottom inputs will need to supply approximately
18mA due to the resistor string impedance of 116Ω minimum. A reference voltage of ±1.02V is normally applied to
inputs VART and VARB. This reference voltage can be
adjusted up to ±1.4V to accommodate extended input
requirements (accuracy specifications are guaranteed with
±1.02V references). The reference input VARTS, VARBS,
and VACTS allow Kelvin sensing of the applied voltages
to increase precision.
An RC network at the ADC’s reference terminals is
needed for best performance. This network consists of
a 33Ω resistor connected in series with the op amp output that drives the reference. A 0.47µF capacitor must
be connected near the resistor at the op amp’s output
(see Typical Operating Circuit ). This resistor and
capacitor combination should be located within 0.5
inches of the MAX100 package. Any noise on these
pins will directly affect the code uncertainty and
degrade the ADC’s effective-bits performance.
MAX100
250Msps, 8-Bit ADC with Track/Hold
___________________________________________________Typical Operating Circuit
0.01µF
1
+VS
VOUT
GND
3
MX580LH
+5V
2.5V
2
0.1µF
0.01µF
0.001µF
150Ω
50Ω
8, 21, 43, 56
1/2 MAX412
1.02V
50Ω
20Ω
0.22µF
120Ω
50
MC100E151
VCC
VART
CMPSH-3
51Ω
51
D
Q
>
Q
D
Q
>
Q
8
AData
VARTS
VACT
VACTS
20k
20k
51Ω
54
MC100E151
VARBS
1/2 MAX412
20Ω
50k
33Ω
55
D
Q
>
Q
D
Q
>
Q
VARB
8
70k
BData
CMPSH-3
0.22µF
10k
MAX100
WATKINS-JOHNSON
SMRA 89-1
0.47µF
72. 73
AIN+
DCLK
DCLK
50Ω
14
-2V
CLOCK
13
75, 76
AIN-
A=B
1k
16
-2V
1k
2
50Ω
-2V
62
-2V
CLK
DIV
11
3
50Ω
MC100E116
-2V
CLK
MOD
61
DGND
GND
*
*PINS 68, 4, 7, 15, 49, 57, 60, 64
67, 70, 71, 74, 77, 78, 79,
82, 84, 18, 24, 27, 30, 34,
37, 40, 46
14
1k
12
-2V
SUB VEE
29
32, 69, 80
0.1µF
0.001µF
-5.2V
______________________________________________________________________________________
10µF
250Msps, 8-Bit ADC with Track/Hold
TP3
GND
TP2
64
GND
66
65
TP1
67
VEE
GND
GND
AIN+
AIN+
68
69
70
71
72
73
AIN-
AIN-
GND
GND
GND
VEE
N.C.
GND
N.C.
GND
74
75
76
77
78
79
80
81
82
83
84
GND
TOP VIEW
PAD
1
63 N.C.
CLK
2
62 CLK
CLK
3
61 CLK
GND
4
60 GND
N.C.
5
59
N.C.
N.C.
6
58
N.C.
GND
7
57
GND
VCC
8
56
VCC
N.C.
9
55
VARB
N.C.
10
54
VARBS
DIV
11
53 VA
CT
MOD
12
52 VA
CTS
DCLK
13
51 VARTS
DCLK
14
50 VART
GND
15
49
GND
A=B
16
48
N.C.
A7
17
47
B0
DGND
18
46
DGND
B7
19
45
A0
A6
20
44
B1
VCC
21
43
VCC
38
39
40
41
42
B3
A2
DGND
B2
A1
36
A3
37
35
N.C.
DGND
34
VEE
DGND
32
N.C.
33
31
N.C.
30
DGND
29
SUB
28
B4
26
A4
DGND
25
B5
27
24
DGND
22
23
B6
A5
MAX100
Ceramic Flat Pack
______________________________________________________________________________________
15
MAX100
____________________________________________________________Pin Configuration
________________________________________________________Package Information
PIN FIN HEATSINK
FORCED CONVECTION PARAMETERS
MAX100-insertB
23
21
19
θJA (°C/W)
MAX100
250Msps, 8-Bit ADC with Track/Hold
17
15
0 Degrees*
13
11
45 Degrees*
12
7
0
100
200
300
400
500
VELOCITY (ft /min)
*DIRECTION OF AIRFLOW ACROSS HEATSINK
E1
E
E2
e
S
0.060±.005(7x)
D1
D
D2
PIN #1
c
MILLIMETERS
MIN
MAX
A
17.272 18.288
A1 1.041 1.270
A2 3.048 3.302
b
0.406 0.508
C
0.228 0.279
D
29.184 29.794
D1 44.196 44.704
D2 25.298 25.502
D3 28.448 28.829
1.270 BSC
e
E
29.184 29.794
E1 44.196 44.704
E2 25.298 25.502
E3 28.194 28.702
S
1.930 2.184
DIM
b
A2 A1
A
5–6°
D3
0.075±.020(6x)
EQUAL SPACES
INCHES
MIN MAX
0.680 0.720
0.041 0.050
0.120 0.130
0.016 0.020
0.009 0.011
1.149 1.173
1.740 1.760
0.996 1.004
1.120 1.135
0.050 BSC
1.149 1.173
1.740 1.760
0.996 1.004
1.110 1.130
0.076 0.086
84 LEAD CERAMIC FLAT
PACK WITH HEAT SINK
0.060±.005
E3
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1994 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.