CYPRESS High-Density FIFO P R O D U C T O V E RV I E W HIGH - DENSITY FIFOS WITH PROGRA MM ABLE FEATURES K E Y S P E C I F I C AT I O N S The Cypress programmable first in first out (FIFO) family offers the industry’s highest density DENSITY: 18 Mb, 36 Mb, 72 Mb, 144 Mb programmable FIFO memory device. In addition to densities up to 144 Mb, it has best-in- SPEED: 133 MHz class speed of 133 MHz in addition to segment-specific, value-added features such as THROUGHPUT: UP TO 4.8 Gbps multiqueueing and selectable memory organizations. All of this helps customers design faster and more efficiently making it ideal for a wide range of applications. Based on BUS WIDTH: USER SELECTABLE x 9, x 12, x 16, x 18, x 20, x 24, x 32, x 36 SRAM technology, high-density (HD) FIFO offers high data reliability and low latency. The CORE VOLTAGE: 1.5 V, 1.8 V easy-to-use bus interface reduces implementation and debugging efforts. It is an off-theshelf solution that accelerates time-to-market and reduces associated engineering efforts. The device also offers width expansion options. It suits the video broadcasting, military, medical imaging, and basestation (networking) PACKAGE: 209-BALL BGA (14 mm X 22 mm) INDUSTRIAL TEMPERATURE RANGE: -40 °C to +85 °C segments and caters to a host of applications such as: • Frame buffers for common HD formats (720p, 1080i, 1080p): stores up to four frames of 1080p resolution • HDTV/SDTV frame synchronization • Switcher or format converter box • High-end digital video camera • High-density buffering in military radars • Medical imaging • Basestations - 3G, 4G, and networking www.cypress.com/go/HDFIFO K E Y F E AT U R E S DIFFERENT DEVICES OFFERED FOR MULTI-QUEUEING • Single queue (up to 133 MHz) • Two queues (up to 100 MHz) • Eight queues (up to 100 MHz) I/O VOLTAGE OPTIONS • Supports 1.8 V and 3.3 V • Available in LVCMOS KEY FEATURES • Multi-queue feature: Divide the FIFO into queues and switch randomly between queues. Useful for picture in picture and interlacing/ de-interlacing • Unidirectional operation with independent read/write ports - supports simultaneous read/write operations • Input and output enable control for write mask and read skip operations • Mark and retransmit feature resets read pointer to user marked position • A mail box register to send data from input to output port bypassing the FIFO sequence • Separate SCLK input for serial programming of the configuration register • Empty, full, half-full, and programmable almost-empty and almost-full status flags • Programmable flags can be programmed either through serial or parallel means • A partial reset to clear data but retain programmable settings • JTAG port for boundary scan function D0 to D35 IE WEN 3 SEN SCLK WCLK Input Register WQSEL (2:0) LD SI Configuration Registers/ Mail Box MB Write Control Logic FF PAF EF Write Pointer Flag Logic PRS MRS Reset Logic TCK TRST TMS TDO JTAG Control Memory Array 18 Mbit 36 Mbit 72 Mbit 144 Mbit PAE DVal HF Read Pointer TDI RT MARK Read Control Logic 3 Output Register RQSEL (2:0) RCLK REN OE Q0 to Q35 Memory Organization 3 PORTSZ (2:0) HD FIFO Functional Block Diagram www.cypress.com/go/HDFIFO P R O D U C T O V E RV I E W KEY ADVANTAGES Simplified System Architecture - HD FIFO versus Other Discrete FIFOs Discrete FIFOs in today’s market are constrained by the densities they offer and high costs per megabit. The multi-queueing feature in Cypress’s HD FIFO provides a much-needed tool that simplifies the system architecture of high performance imaging, video processing, and networking systems. This allows customers to design solutions quickly and more cost effectively than other discrete solutions. FPGA/DSP Integrated Memory - HD FIFO and FPGA versus SDRAM and FPGA Solution Image processing systems require very high amounts of data buffering that is handled by an FPGA. To achieve this high-density memory buffering, FPGAs are often coupled with an external SDRAM. By implementing FIFO controller logic inside the FPGA, the external SDRAM functions like a FIFO. To compensate for the latency of the external DRAM, a small memory buffer is created inside the FPGA. However, this has some drawbacks, which force customers to use higher-range FPGAs: • Valuable logic resources in the FPGA used, making the design complicated and reducing efficiency • Valuable FPGA I/Os used as the controller implemented in the FPGA needs to send address signals to the external SDRAM memory • FPGA’s internal memory space required (scratch pad memory), eliminating availability for other purposes • Increased system complexity reduces performance With Cypress’s programmable HD FIFO, customers can choose to use a lower density FPGA resulting in reduced system costs. The diagram below shows the comparison between two such systems. HD FIFO also enables various combinations of part offerings to meet customer requirements and feature priorities. WITHOUT HD FIFO FPGA Control Control Write Buffers Parallel Port Interface Data SDRAM Controller Read Buffers Address SDRAM Data Other Subsystems Registers Clock WITH HD FIFO Data FPGA HD FIFO Data Other Subsystems Clock Block Diagram Comparing Systems with and without HD FIFO P R O D U C T O V E RV I E W ORDERING INFORM ATION Density (Mb) Organization V DD (V) Temperature (°C) Frequency (MHz) I/O Voltage Standards (V) Queues Package 18 Production parts available - order now! 36 72 User selectable x9, x12, x16, x18, x20, x24, x32, x36 144 Availability 1.5, 1.8 -40 to +85 133 Single, double, 8 1.8, 3.3 209-ball BGA Engineering samples available in Q3 2012. Production in Q1 2013. HD FIFO IN AN IM AGING SYSTEM - AN EX A MPLE The diagram below illustrates the working of an imaging system with HD FIFO. A typical imaging system comprises two sets of cards: Data Acquisition and Consolidation Cards - Data acquisition cards filter incoming data. A diagnostic imaging system may comprise multiple data acquisition cards. Data consolidation cards buffer and align the acquired data. For CT and PET scanners, detectors rotate around the body and the data is serialized and sent across a slip ring electromechanical subassembly. Image/Data Processing Cards - These cards perform heavy duty filtering and the most algorithm-intensive image reconstruction. A/D and Filtering Incoming Data A/D and Filtering DSP DSP Data Alignment HDHD FIFO FIFO Video Display Image Processing A/D and Filtering HD FIFO Data Acquisition and Consolidation Card Data Processing Card Example Application Bock Diagram with the Cards GET STARTED NOW For more information on HD FIFOs, visit www.cypress.com/go/HDFIFO or contact [email protected]. Cypress Semiconductor Corporation 198 Champion Court, San Jose CA 95134 phone +1 408.943.2600 toll free +1 800.858.1810 (U.S. only) © 2012 Cypress Semiconductor Corporation. All rights reserved. All other trademarks are the property of their respective owners. Doc# 001-65453 Rev*C 0312/MBAT/NITA Audio Output