AN98508 Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide.pdf

AN98508
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Author: Umesh Painaik
Associated Part Families: S25FL, S70FL, S25FS, S70FS
AN98508 outlines PCB layout recommendations for Cypress SPI flash devices, including S25FL-P, S70FL-P, S25FL-S,
S70FL-S, S25FS-S, and S70FS-S flash families.
Contents
1
2
3
4
5
1
Introduction ............................................................... 1
Basic SPI Flash Connectivity .................................... 1
SPI Flash Packaging................................................. 4
3.1 SPI Flash Package Connection Diagrams ....... 5
3.2 SPI Flash Package Drawings ......................... 10
Land Patterns Recommendations........................... 22
4.1 BGA Land Pad Recommendations ................ 26
Printed Circuit Board Design Recommendations.... 27
5.1 Power Supply Decoupling ...............................27
5.2 Clock Signal Routing .......................................27
5.3 Data Signal Routing ........................................28
5.4 Via Routing .....................................................29
5.5 Escape Path Routing ......................................29
6
Summary ................................................................. 29
Document History Page ...................................................30
Worldwide Sales and Design Support ..............................31
Introduction
The Cypress serial peripheral interface (SPI) flash devices are high speed synchronous access non-volatile
memory devices. Standard high speed layout practices should be followed when performing printed circuit board
(PCB) design with SPI flash. This application note outlines PCB layout recommendations for Cypress SPI flash
devices, including S25FL-P, S70FL-P, S25FL-S, S70FL-S, S25FS-S and S70FS-S flash families.
2
Basic SPI Flash Connectivity
All S25FL/S25FS devices feature one flash die per package and are enabled via a single chip select control input.
All S70FL/S70FS devices feature two identical die per package which are individually enabled via two chip select
control inputs and all other control inputs and I/O are shared between die. Figure 1 and Figure 2 illustrate basic
Host to SPI Flash configuration options for S25FL flash and S70FL flash, respectively.
www.cypress.com
Document No. 001-98508 Rev. *B
1
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Figure 1. Simplified Connection Diagrams for S25FL Single and Multi I/O Configurations
Standard Single I/O Configuration
Host
SCK
SCK
SO
SI
SI
SO
W#
W#
HOLD#
S25FL
SPI Flash
HOLD#
CS#
CS#
Multi I/O Configuration
Host
SCK
SCK
S25FL
SPI Flash
SI/IO0
SO/IO0
SI/IO1
SO/IO1
W#/ACC/IO2
W#/ACC/IO2
HOLD#/IO3
HOLD#/IO3
CS#
CS#
Figure 2. Simplified Connection Diagrams for S70FL Single and Multi I/O Configurations
Standard Single I/O Configuration
Host
SCK
SCK
SO
SI
SI
SO
W#
W#
HOLD#
S70FL
SPI Flash
HOLD#
CS1#
CS1#
CS2#
CS2#
Multi I/O Configuration
Host
SCK
SO/IO0
SI/IO1
W#/ACC/IO2
HOLD#/IO3
www.cypress.com
SCK
S70FL
SPI Flash
SI/IO0
SO/IO1
W#/ACC/IO2
HOLD#/IO3
CS1#
CS1#
CS2#
CS2#
Document No. 001-98508 Rev. *B
2
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Often multiple SPI devices are connected to a single host. Figure 3 illustrates such a configuration. Use of a dual
die S70FL device can be viewed as use of Device 1 and Device 2 in Figure 3.
Figure 3. Simplified Multi- SPI Device Connection Diagram
SO
SI
SCK
SPI
Bus
Master
SCK
CS#
SO
Device 1
S1
W#
HOLD#
SCK
SO
S1
SCK
SO
Device 3
S1
HOLD#
CS#
W#
HOLD#
Device 2
CS#
W#
CS1#
CS2#
CS3#
Many SPI flash applications do not utilize the ACC, WP# or HOLD# functions. In those applications where an input
is not utilized, the unused I/O should be pulled up to VCC, or VIO if present, via a suitable resistor, e.g., 4.7 kto
10 k.
www.cypress.com
Document No. 001-98508 Rev. *B
3
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
3
SPI Flash Packaging
The FL-P and FL-S SPI Flash families provide a user configurable high speed single, dual or quad channel
interface to the host controller. Cypress SPI flash are available in a variety of packages, including SOIC-8 and
SOIC-16 leaded packages, USON-8 and WSON-8 leadless packages and FAB024 and FAC024 ball grid array
(BGA) packages. Table 1 provides a matrix of package options for all FL-P and FL-S devices.
Table 1. Device Availability Matrix
Package \ Density
< 16Mbit
32 Mbit
64 Mbit
128 Mbit
256-1024 Mbit
SOIC 8L
Narrow Body
Pkg Code: SOA008
S25FL204K
S25FL208K
S25FL216K
S25FL116K
S25FL132K
–
–
–
SOIC 8L
Wide Body
Pkg Code: SOC008
S25FL204K
S25FL208K
S25FL216K
S25FL116K
S25FL032P
S25FL132K
S25FL164K
S25FL127S
S25FS128S
S25FL256S
S25FL512S
S25FS256S
S25FS512S
SO3 016
–
S25FL032P
S25FL064P
S25FL164K
S25FL128P
S25FL129P
S25FL128S
S25FL127S
S25FL128K
SL3 016
–
–
–
–
S70FL256P
S70FL01GS
S70FS01GS
USON 8L
–
S25FL032P
–
–
–
WSON 8L
Pkg Code: WND008
S25FL116K
S25FL132K
S25FL164k
S25FL127S
S25FS128S
–
WSON 8L
Pkg Code: WNF008
–
S25FL032P
S25FL064P
S25FL128P
S25FL129P
–
WSON 8L
Pkg Code: WNG008
–
–
–
S25FL128S
S25FL256S
WSON 8L
Pkg Code: WNH008
–
–
–
–
S25FS256S
S25FS512S
S25FL256L
FAB024
S25FL116K
S25FL032P
S25FL132K
S25FL064P
S25FL164k
S25FL129P
S25FL128S
S25FL127S
S25FL256S
S25FL512S
FAC024
S25FL116K
S25FL032P
S25FL132K
S25FL064P
S25FL164K
S25FL129P
S25FL128S
S25FL127S
S25FL256S
S25FL512S
ZSA024
–
–
–
–
S70FL256P
other BGA (planned)
–
–
–
–
S25FL512S
S70FL512S
S70FL01GS
www.cypress.com
Document No. 001-98508 Rev. *B
4
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
3.1
SPI Flash Package Connection Diagrams
Applicable package connection diagrams are provided in each SPI Flash data sheet. These diagrams are
included here in Figure 4 through Figure 17 for reference.
Note: The packaging information is provided as typical examples and the reader should reference the most recent
revision of the subject flash datasheet for latest packaging information and signal assignments.
Figure 4. SOIC 8L Narrow Body - S25FL204K/208K/216K/116K/132K
CS#
1
8
VCC
SO / IO1
2
7
HOLD# / IO3
W#/ACC/IO2
3
6
SCK
4
5
SI/IO0
GND
GND
Figure 5. SOIC 8L Wide Body - S25FL204K/208K/216K/116K/032P/132K/164K/127S, S25FS128S
CS#
1
8
VCC
SO / IO1
2
7
HOLD# / IO3
W#/ACC/IO2
3
6
SCK
4
5
GND
GND
SI/IO0
Figure 6. SO3 016 – S25FL128P
www.cypress.com
HOLD#
1
16
SCK
VCC
2
15
SI
NC
3
14
PO6
PO2
4
13
PO5
PO1
5
12
PO4
PO0
6
11
PO3
CS#
7
10
GND
SO/PO7
8
9
WP#/ACC
Document No. 001-98508 Rev. *B
5
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Figure 7. SO3 016 – S25FL032P/064P/164K/127S/129P
HOLD#/IO3
1
16
SCK
VCC
2
15
SI/IO0
DNC
3
14
DNC
DNC
4
13
DNC
DNC
5
12
DNC
DNC
6
11
DNC
CS#
7
10
GND
SO/IO1
8
9
W#/ACC/IO2
Figure 8. SO3 016 – S29FL128S/256S/512S
www.cypress.com
HOLD#/IO3
1
16
SCK
VCC
2
15
SI/IO0
RESET#/RFU
3
14
VIO/RFU
RFU
4
13
DNC
RFU
5
12
DNC
RFU
6
11
DNC
CS#
7
10
GND
SO/IO1
8
9
W#/ACC/IO2
Document No. 001-98508 Rev. *B
6
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Figure 9. SO3 016 - S25FS256S/512S
IO3/RESET#
1
16
SCK
VDD
2
15
SI/IO0
RFU
3
14
RFU
NC
4
13
DNU
NC
5
12
DNU
RFU
6
11
DNU
CS#
7
10
VSS
SO/IO1
8
9
WP#/IO2
Figure 10. SL3 016 – S70FL256P/01GS
www.cypress.com
HOLD#/IO3
1
16
SCK
VCC
2
15
SI/IO0
DNU
3
14
DNU
DNU
4
13
DNC
DNU
5
12
DNC
CS2#
6
11
DNC
CS1#
7
10
GND
SO/IO1
8
9
W#/ACC/IO2
Document No. 001-98508 Rev. *B
7
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Figure 11. SL3 016 - S70FS01GS
1
16
SCK
VDD
2
15
SI / IO0
RFU
3
14
RFU
NC
4
13
DNU
NC
5
12
DNU
RFU
6
11
DNU
CS#
7
10
VSS
SO / IO1
8
9
IO3/RESET#
WP# / IO2
Figure 12. USON 8L – S25FL032P
CS#
1
8
VCC
SO/IO1
2
7
HOLD#/IO3
W#/ACC/IO2
3
6
SCK
GND
4
5
SI/IO0
Figure 13. WSON 8L – S25FL128P
CS#
1
8
VCC
SO
2
7
HOLD#
WP#/ACC
3
6
SCK
4
5
SI
GND
Figure 14. WSON 8L – S25FL032/064/129P, S25FL116K, S25FL128/256S
CS#
1
8
VCC
SO/IO1
2
7
HOLD#/IO3
W#/ACC/IO2
3
6
SCK
4
5
SI/IO0
GND
www.cypress.com
Document No. 001-98508 Rev. *B
8
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Figure 15. FAB024 – S25FL032/064/129P, S25FL116K, S25FL128/256S
1
2
3
4
5
A
NC
NC RESET#/RFU NC
B
NC
SCK
GND
NC
CS#
NC
SO/IO1
NC
NC
VCC
NC
C
NC W#/ACC/IO2 NC
D
SI/IO1 HOLD#/IO3
NC
E
NC
VIO/RFU
NC
Note:
RESET# and VIO inputs apply to S25FL-S models only.
Figure 16. FAC024 – S25FL032/064/129P, S25FL116K, S25FL128/256S
1
2
3
NC
NC
NC
SCK
NC
CS#
NC
SO/IO1
NC
NC
NC
NC
NC
NC
4
A
NC RESET#/RFU
B
GND
VCC
C
NC W#/ACC/IO2
D
SI/IO0 HOLD#/IO3
E
F
VIO/RFU
Note:
RESET# and VIO inputs apply to S25FL-S models only.
Figure 17. ZSA024 – S70FL256P
1
2
3
4
5
NC
NC
NC
NC
NC
SCK
GND
VCC
NC
NC
CS#1
CS#2 W#/ACC/IO2 NC
NC
SO/IO1
NC
NC
A
B
C
D
SI/IO1 HOLD#/IO3
NC
E
www.cypress.com
NC
NC
NC
Document No. 001-98508 Rev. *B
9
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
3.2
SPI Flash Package Drawings
Applicable package drawings are provided in each SPI Flash data sheet. These drawings are included here in
Figure 18 through Figure 29 for reference.
Figure 18. SOIC 8L – Narrow 8-Pin Plastic Small Outline 150-mils Body Width Package (SOA008)
NOTES:
PACKAGE
JEDEC
SYMBOL
SOA 008 (mm)
SOA 008 (inches)
MS-012(F)AA
MS-012(F)AA
ALL DIMENSIONS ARE IN MILLIMETERS (INCHES ARE FOR
REFERENCE ONLY).
2.
DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
3.
DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm
PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1
DIMENSIONS ARE DETERMINED AT DATUM H.
4.
THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE
BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE
OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF
MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
MIN
MAX
MIN
A
---
1.75
---
0.069
A1
0.10
0.25
0.004
0.010
A2
1.32
---
0.052
---
b
0.31
0.51
0.012
0.020
b1
0.28
0.48
0.011
0.019
c
0.17
0.25
0.007
0.010
c1
0.17
0.23
0.007
0.009
D
4.90 BSC
E
6.00 BSC
0.236 BSC
5.
DATUMS A AND B TO BE DETERMINED AT DATUM H.
E1
3.90 BSC
0.153 BSC
6.
e
1.27 BSC
0.050 BSC
"N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR
THE SPECIFIED PACKAGE LENGTH.
7.
THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.
8.
DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL
IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL
CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
9.
THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,
THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX
AREA INDICATED.
10.
LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED
FROM THE SEATING PLANE.
L
0.40
0.89
MAX
1.
0.193 BSC
0.016
0.035
L1
1.04 REF
0.041 REF
L2
0.25 BSC
0.010 BSC
N
8
8
h
0.25
0.50
0.10
0.196
Θ
0°
8°
0°
8°
Ĭ
ƒ
ƒ
ƒ
ƒ
Ĭ
ƒ5()
ƒ5()
g5060 \ 16-038.3 \ 12.4.15
www.cypress.com
Document No. 001-98508 Rev. *B
10
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Figure 19. SOIC 8L – Wide 8-Pin Plastic Small Outline 208 mils Body Width Package (SOC008)
NOTES:
PACKAGE
SOC 008 (mm)
JEDEC
SYMBOL
N/A
MAX
MIN
MAX
A
1.75
2.16
0.069
0.085
A1
0.05
0.25
0.002
0.010
A2
1.70
1.90
0.067
0.075
b
0.36
0.48
0.014
0.019
b1
0.33
0.46
0.013
0.018
c
0.18
0.25
0.007
0.010
c1
0.15
0.20
0.006
0.008
D
5.28 BSC
0.208 BSC
E
8.00 BSC
0.315 BSC
E1
e
L
5.28 BSC
0.208 BSC
1.27 BSC
0.51
0.76
0.050 BSC
0.020
2.
DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
3.
DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm
PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1
DIMENSIONS ARE DETERMINED AT DATUM H.
4.
THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE
BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE
OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF
MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
5.
DATUMS A AND B TO BE DETERMINED AT DATUM H.
6.
"N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR
THE SPECIFIED PACKAGE LENGTH.
7.
THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.
8.
DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL
IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL
CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
9.
THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,
THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX
AREA INDICATED.
10.
LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED
FROM THE SEATING PLANE.
0.030
L1
1.36 REF
0.054 REF
L2
0.25 BSC
0.010 BSC
N
ALL DIMENSIONS ARE IN MILLIMETERS (INCHES ARE FOR
REFERENCE ONLY).
SOC 008 (inches)
N/A
MIN
1.
8
8
Θ
0°
8°
0°
8°
Ĭ
ƒ
ƒ
ƒ
ƒ
Ĭ
ƒ5()
ƒ5()
g5059 \ 16-038.3 \ 12.4.15
www.cypress.com
Document No. 001-98508 Rev. *B
11
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Figure 20. SO3 016 – 16-Pin Wide Plastic Small Outline Package (300 mil Body Width)
NOTES:
1.
PACKAGE
JEDEC
SO3 016 (mm)
SO3 016 (inches)
MS-013(E)AA
MS-013(E)AA
SYMBOL
MIN
MAX
MIN
A
2.35
2.65
0.093
0.104
A1
0.10
0.30
0.004
0.012
A2
2.05
2.55
0.081
0.104
b
0.31
0.51
0.012
0.020
b1
0.27
0.48
0.011
0.019
c
0.20
0.33
0.008
0.013
c1
0.20
0.30
0.008
0.012
D
10.30 BSC
0.406 BSC
E
10.30 BSC
0.406 BSC
E1
e
L
7.50 BSC
0.295 BSC
1.27 BSC
0.40
1.27
MAX
0.050 BSC
0.016
2.
DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
3.
DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm
PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1
DIMENSIONS ARE DETERMINED AT DATUM H.
4.
THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE
BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE
OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF
MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
5.
DATUMS A AND B TO BE DETERMINED AT DATUM H.
6.
"N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR
THE SPECIFIED PACKAGE LENGTH.
7.
THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.
8.
DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL
IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL
CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
9.
THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,
THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX
AREA INDICATED.
10.
LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED
FROM THE SEATING PLANE.
0.050
L1
1.40 REF
0.055 REF
L2
0.25 BSC
0.010 BSC
N
16
16
h
0.25
0.75
0.10
0.30
Θ
0°
8°
0°
8°
Ĭ
ƒ
ƒ
ƒ
ƒ
Ĭ
ƒ
ƒ
ALL DIMENSIONS ARE IN MILLIMETERS (INCHES ARE FOR
REFERENCE ONLY).
g5058 \ 16-038.3 \ 12.4.15
www.cypress.com
Document No. 001-98508 Rev. *B
12
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Figure 21. SL3 016 – 16-Pin Wide Plastic Small Outline Package (300 mil Body Width)
NOTES:
PACKAGE
JEDEC
SYMBOL
SL3 016 (mm)
MAX
MS-013(E)AA
MIN
MAX
A
2.35
2.65
0.093
0.104
A1
0.10
0.30
0.004
0.012
A2
2.05
2.55
0.081
0.104
b
0.31
0.51
0.012
0.020
b1
0.27
0.48
0.011
0.019
c
0.20
0.33
0.008
0.013
c1
0.20
0.30
0.008
0.012
D
10.30 BSC
0.406 BSC
E
10.30 BSC
0.406 BSC
E1
e
L
7.50 BSC
0.295 BSC
1.27 BSC
0.40
1.27
ALL DIMENSIONS ARE IN MILLIMETERS (INCHES ARE FOR
REFERENCE ONLY).
2.
DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
3.
DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm
PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1
DIMENSIONS ARE DETERMINED AT DATUM H.
4.
THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE
BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE
OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF
MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
5.
DATUMS A AND B TO BE DETERMINED AT DATUM H.
6.
"N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR
THE SPECIFIED PACKAGE LENGTH.
7.
THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.
8.
DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL
IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL
CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
9.
THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,
THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX
AREA INDICATED.
10.
LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED
FROM THE SEATING PLANE.
SL3 016 (inches)
MS-013(E)AA
MIN
1.
0.050 BSC
0.016
0.050
L1
1.40 REF
0.055 REF
L2
0.25 BSC
0.010 BSC
N
16
16
h
0.25
0.75
0.10
0.30
Θ
0°
8°
0°
8°
Ĭ
ƒ
ƒ
ƒ
ƒ
Ĭ
ƒ
ƒ
g5057 \ 16-038.3 \ 12.4.15
www.cypress.com
Document No. 001-98508 Rev. *B
13
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Figure 22. USON 8L - 8-contact (5 x 6 mm) No-Lead Package (UNE008)
NOTES:
PACKAGE
SYMBOL
UNE008
MIN
NOM
MAX
NOTE
e
1.27 BSC.
N
8
3
ND
4
5
1.
DIMENSIONING AND TOLERANCING CONFORMS TO
ASME Y14.5M - 1994.
2.
ALL DIMENSIONS ARE IN MILLMETERS.
3.
N IS THE TOTAL NUMBER OF TERMINALS.
4
DIMENSION “b” APPLIES TO METALLIZED TERMINAL AND IS
MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL
TIP. IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE
OTHER END OF THE TERMINAL, THE DIMENSION “b”
SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
L
0.55
0.60
b
0.35
0.40
0.65
0.45
D2
3.90
4.00
4.10
5
ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE.
E2
3.30
3.40
3.50
6.
MAX. PACKAGE WARPAGE IS 0.05mm.
4
D
5.00 BSC
7.
MAXIMUM ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS.
E
6.00 BSC
8
PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.
9
BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED
HEAT SINK SLUG AS WELL AS THE TERMINALS.
A
0.45
0.50
0.55
A1
0.00
0.02
0.05
A3
0.20 REF
K
0.20 MIN.
g5033 \ 16-038.30 \ 03.25.14
www.cypress.com
Document No. 001-98508 Rev. *B
14
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Figure 23. WSON 8L - 8-Contact (5 x 6 mm) No-Lead Package (WND008)
NOTES:
PACKAGE
SYMBOL
WND008
MIN
NOM
MAX
NOTES
e
1.27 BSC.
N
8
3
ND
4
5
L
0.55
0.60
b
0.35
0.40
0.45
D2
3.90
4.00
4.10
E2
3.30
3.40
3.50
D
5.00 BSC
E
6.00 BSC
A
0.70
0.75
0.80
0.00
0.02
0.05
0.20 REF
K
0.20 MIN.
DIMENSIONING AND TOLERANCING CONFORMS TO
ASME Y14.5M-1994.
2.
ALL DIMENSIONS ARE IN MILLMETERS.
3.
N IS THE TOTAL NUMBER OF TERMINALS.
4
DIMENSION “b” APPLIES TO METALLIZED TERMINAL AND IS
MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL
TIP. IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE
OTHER END OF THE TERMINAL, THE DIMENSION “b”
SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
0.65
A1
A3
1.
4
5
ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE.
6.
MAX. PACKAGE WARPAGE IS 0.05mm.
7.
MAXIMUM ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS.
8
PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED
ZONE.
9
BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED
HEAT SINK SLUG AS WELL AS THE TERMINALS.
g5026 \ 16-038.30 \ 03.20.14
www.cypress.com
Document No. 001-98508 Rev. *B
15
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Figure 24. WSON 8L - 8-Contact (6 x 8 mm) No-Lead Package (WNF008)
NOTES:
PACKAGE
SYMBOL
WNF008
MIN
NOM
MAX
NOTE
e
1.27 BSC.
N
8
3
ND
4
5
1.
DIMENSIONING AND TOLERANCING CONFORMS TO
ASME Y14.5M - 1994.
2.
ALL DIMENSIONS ARE IN MILLMETERS.
3.
N IS THE TOTAL NUMBER OF TERMINALS.
4
DIMENSION “b” APPLIES TO METALLIZED TERMINAL AND IS
MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL
TIP. IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE
OTHER END OF THE TERMINAL, THE DIMENSION “b”
SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
L
0.45
0.50
b
0.35
0.40
0.55
0.45
D2
4.70
4.80
4.90
5
ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE.
E2
5.70
5.80
5.90
6.
MAX. PACKAGE WARPAGE IS 0.05mm.
4
D
6.00 BSC
7.
MAXIMUM ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS.
E
8.00 BSC
8
PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.
9
BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED
HEAT SINK SLUG AS WELL AS THE TERMINALS.
10
A MAXIMUM 0.15mm PULL BACK (L1) MAY BE PRESENT.
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
K
L1
0.20 MIN.
0.00
---
0.15
10
g5030 \ 16-038.30 \ 03.25.14
www.cypress.com
Document No. 001-98508 Rev. *B
16
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Figure 25. WSON 8L - 8-Contact (6 x 8 mm) No-Lead Package (WNG008)
NOTES:
PACKAGE
SYMBOL
WNG008
MIN
NOM
MAX
NOTE
e
1.27 BSC.
N
8
3
ND
4
5
1.
DIMENSIONING AND TOLERANCING CONFORMS TO
ASME Y14.5M - 1994.
2.
ALL DIMENSIONS ARE IN MILLMETERS.
3.
N IS THE TOTAL NUMBER OF TERMINALS.
4
DIMENSION “b” APPLIES TO METALLIZED TERMINAL AND IS
MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL
TIP. IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE
OTHER END OF THE TERMINAL, THE DIMENSION “b”
SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
L
0.45
0.50
b
0.35
0.40
0.55
0.45
D2
4.70
4.80
4.90
5
ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE.
E2
4.55
4.65
4.75
6.
MAX. PACKAGE WARPAGE IS 0.05mm.
4
D
6.00 BSC
7.
MAXIMUM ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS.
E
8.00 BSC
8
PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.
9
BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED
HEAT SINK SLUG AS WELL AS THE TERMINALS.
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
A3
0.20 REF
K
0.20 MIN
g5031 \ 16-038.30 \ 03.25.14
www.cypress.com
Document No. 001-98508 Rev. *B
17
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Figure 26. WSON 8L - 8-Contact (6 x 8 mm) No-Lead Package (WNH008)
NOTES:
PACKAGE
SYMBOL
WNH008
MIN
NOM
MAX
NOTE
e
1.27 BSC.
N
8
3
ND
4
5
1.
DIMENSIONING AND TOLERANCING CONFORMS TO
ASME Y14.5M - 1994.
2.
ALL DIMENSIONS ARE IN MILLMETERS.
3.
N IS THE TOTAL NUMBER OF TERMINALS.
4
DIMENSION “b” APPLIES TO METALLIZED TERMINAL AND IS
MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL
TIP. IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE
OTHER END OF THE TERMINAL, THE DIMENSION “b”
SHOULD NOT BE MEASURED IN THAT RADIUS AREA.
L
0.45
0.50
b
0.35
0.40
0.55
0.45
D2
3.90
4.00
4.10
5
ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE.
E2
3.30
3.40
3.50
6.
MAX. PACKAGE WARPAGE IS 0.05mm.
4
D
6.00 BSC
7.
MAXIMUM ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS.
E
8.00 BSC
8
PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.
9
BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED
HEAT SINK SLUG AS WELL AS THE TERMINALS.
A
0.70
0.75
0.80
A1
0.00
---
0.05
A3
0.20 REF
K
0.20 MIN.
g5032 \ 16-038.30 \ 03.25.14
www.cypress.com
Document No. 001-98508 Rev. *B
18
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Figure 27. FAB024 24-ball Ball Grid Array (6 x 8 mm) Package
NOTES:
PACKAGE
FAB 024
JEDEC
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
8.00 mm x 6.00 mm
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.20
A1
0.20
---
---
NOTE
PROFILE
4.
BALL HEIGHT
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE
"D" DIRECTION.
D
8.00 BSC.
BODY SIZE
E
6.00 BSC.
BODY SIZE
D1
4.00 BSC.
MATRIX FOOTPRINT
E1
4.00 BSC.
MATRIX FOOTPRINT
MD
5
MATRIX SIZE D DIRECTION
ME
5
MATRIX SIZE E DIRECTION
N
24
BALL COUNT
b
0.35
0.40
0.45
e REPRESENTS THE SOLDER BALL GRID PITCH.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
N IS THE TOTAL NUMBER OF POPULATED SOLDER
BALL POSITIONS FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
“SD” AND “SE” ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
BALL DIAMETER
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW “SD” OR “SE” = 0.
eE
1.00 BSC.
BALL PITCH
eD
1.00 BSC.
BALL PITCH
SD
0.00 BSC.
SOLDER BALL PLACEMENT
SE
0.00 BSC.
SOLDER BALL PLACEMENT
A1
3. BALL POSITION DESIGNATION PER JEP95, SECTION
3, SPP-020.
DEPOPULATED SOLDER BALLS
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, “SD” = eD/2 AND “SE” = eE/2.
8. "+" INDICATES THE THEORETICAL CENTER OF
DEPOPULATED BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
g5049 16-038.9 \ 6.26.15
www.cypress.com
Document No. 001-98508 Rev. *B
19
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Figure 28. FAC024 24-ball Ball Grid Array (6 x 8 mm) Package
NOTES:
PACKAGE
FAC 024
JEDEC
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
8.00 mm x 6.00 mm
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.20
A1
0.25
---
---
NOTE
PROFILE
4.
BALL HEIGHT
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE
"D" DIRECTION.
D
8.00 BSC.
BODY SIZE
E
6.00 BSC.
BODY SIZE
D1
5.00 BSC.
MATRIX FOOTPRINT
E1
3.00 BSC.
MATRIX FOOTPRINT
MD
6
MATRIX SIZE D DIRECTION
ME
4
MATRIX SIZE E DIRECTION
N
b
24
0.35
0.40
N IS THE TOTAL NUMBER OF POPULATED SOLDER
BALL POSITIONS FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
“SD” AND “SE” ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
BALL DIAMETER
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW “SD” OR “SE” = 0.
eE
1.00 BSC.
BALL PITCH
eD
1.00 BSC.
BALL PITCH
SD
0.50 BSC.
SOLDER BALL PLACEMENT
SE
0.50 BSC.
SOLDER BALL PLACEMENT
---
e REPRESENTS THE SOLDER BALL GRID PITCH.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
BALL COUNT
0.45
3. BALL POSITION DESIGNATION PER JEP95, SECTION
3, SPP-020.
DEPOPULATED SOLDER BALLS
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, “SD” = eD/2 AND “SE” = eE/2.
8. "+" INDICATES THE THEORETICAL CENTER OF
DEPOPULATED BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
g5051 16-038.9 \ 6.26.15
www.cypress.com
Document No. 001-98508 Rev. *B
20
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Figure 29. ZSA024 24-ball Ball Grid Array (6 x 8 mm) Packages
NOTES:
PACKAGE
ZSA 024
JEDEC
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
8.00 mm x 6.00 mm
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.20
A1
0.20
---
---
NOTE
PROFILE
4.
BALL HEIGHT
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE
"D" DIRECTION.
D
8.00 BSC.
BODY SIZE
E
6.00 BSC.
BODY SIZE
D1
4.00 BSC.
MATRIX FOOTPRINT
E1
4.00 BSC.
MATRIX FOOTPRINT
MD
5
MATRIX SIZE D DIRECTION
ME
5
MATRIX SIZE E DIRECTION
n
24
BALL COUNT
0.35
b
SD
0.40
0.45
n IS THE TOTAL NUMBER OF POPULATED SOLDER
BALL POSITIONS FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
“SD” AND “SE” ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
BALL DIAMETER
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW “SD” OR “SE” = 0.
1.00 BSC.
BALL PITCH
eD
1.00 BSC.
BALL PITCH
0.00 BSC.
SOLDER BALL PLACEMENT
A1
e REPRESENTS THE SOLDER BALL GRID PITCH.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
eE
SE
3. BALL POSITION DESIGNATION PER JEP95, SECTION
3, SPP-020.
DEPOPULATED SOLDER BALLS
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, “SD” = eD/2 AND “SE” = eE/2.
8. "+" INDICATES THE THEORETICAL CENTER OF
DEPOPULATED BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
g5062 16-038.86 \ 12.4.15
www.cypress.com
Document No. 001-98508 Rev. *B
21
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
4
Land Patterns Recommendations
Applicable PCB land pattern recommendations for SOC 008, SO3 016, SL3 016, USON, WSON, FAB024,
FAC024, and ZSA024 packages are provided here in Figure 31 through Figure 35.
Note: All dimensions are in mm.
Figure 30. SOA008 Proposed Land Pattern
Figure 31. SOC008 Proposed Land Pattern
www.cypress.com
Document No. 001-98508 Rev. *B
22
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Figure 32. SO3 016 and SL3 016 Proposed Land Pattern
www.cypress.com
Document No. 001-98508 Rev. *B
23
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Figure 33. USON 8L and WSON 8L Proposed Land Pattern
Packag e
USO N 8L
Pac kag e Le ad Pitch
Code
e
UN E00 8
W N D0 08
W NF 008
WS ON 8L
W N G0 08
W N H0 08
1 .27
1 .27
1 .27
1 .27
1 .27
LE ( m in)
4.6 5
4.6 5
6.7 5
6.8 5
6.8 5
PCB Land Pa tte rn Re com m e ndation
ZE D2 t E 2t Y1
( m ax)
(m a x)
(m a x)
6 .75
6 .75
8 .05
8 .75
8 .75
4.1 0
4.1 0
4.9 0
4.9 0
4.1 0
3.5 0
3.5 0
5.9 0
4.7 5
3.5 0
1.05
1.05
0.65
0.95
0.95
X1
0.45
0.45
0.5
0.45
0.45
The USON 8L and WSON 8L land patterns are shown above. It is recommended that the center slug should be
solder mask define (SMD) to avoid bridging. The mask opening should be 0.05 – 0.1 mm smaller than the center
pad on all four sides. At the pin, it should be NSMD with the mask opening 3 mil larger than the copper pad on all
sides. At center slug, the stencil should also has small multiple openings with solder paste coverage about 40 –
70% of the exposed pad area to prevent bridging between the center slug and pins.
www.cypress.com
Document No. 001-98508 Rev. *B
24
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Figure 34. FAB024 and ZSA024 Proposed Land Pattern
Figure 35. FAC024 Proposed Land Pattern
www.cypress.com
Document No. 001-98508 Rev. *B
25
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
4.1
BGA Land Pad Recommendations
PCB solder-ball land pads can be either non-solder-mask defined (NSMD) or solder-mask-defined (SMD). For
NSMD configurations, there is a small gap between the solder pad and the solder mask. Solder will flow into the
gap between the pad and the solder mask (reference Figure 36). For SMD configurations, the solder mask covers
the outer edge of the solder pad. Solder is prevented from flowing over the edges of the pad by the solder mask.
Figure 36. SMD vs. NSMD Landing Pad Definition
Solder
Pad
Solder
Pad
Mask
Mask
Pad
Mask Opening
Mask
Opening
Pad
Board Material
Board material
NSMD
SMD
NSMD is generally the recommended land pad configuration because it enables a stronger bond between the
solder pad and the solder ball with less stress concentration.
For SMD configurations, it is good practice to make the solder mask opening the same size as the diameter of the
solder ball. On NSMD configurations, the solder pad should be between 80% and 100% of the solder ball
diameter and the solder mask opening should be 0.15 mm larger than the solder pad to provide ample space for
excess solder. Table 2 provides dimensional recommendations for SMD and NSMD configurations suitable for
use with the FAB024, FAC024 and ZSC024 packages.
Table 2. NSMD and SMD Dimensional Recommendations for BGA Packages
Configuration
SMD
NSMD
www.cypress.com
Opening
Recommended Dimension
Solder Pad
0.55 mm
Solder Mask
0.45 mm
Solder Pad
0.45 mm
Solder Mask
0.60 mm
Document No. 001-98508 Rev. *B
26
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
5
Printed Circuit Board Design Recommendations
This section contains general layout recommendations.
5.1
Power Supply Decoupling
All S25FL and S70FL SPI Flash have one power supply input pin (VCC) and one ground pin (GND). Additionally,
certain models support a separate I/O supply input pin (VIO) for applications that require I/O levels to be less than
VCC. Use of one 0.1 µF ceramic capacitor, normally in a 0603 or 0402 package, is recommended for decoupling
each power supply input pin. A decoupling capacitor should be placed as close as possible to the VCC supply
input pin, as well as the VIO supply input pin if present.
The routing of the decoupling capacitor should be optimized to achieve low inductance. Power supply trace
lengths from the package pads to the vias should be as short as possible with a trace width of approximately 0.6
mm. It is recommended to avoid sharing the same via with 2 or more decoupling capacitors. Figure 37 shows
examples of routing the decoupling capacitor.
Figure 37. Routing with Decoupling Capacitor
T oo lo ng trac e
`
`
`
`
G oo d e xam ple s
S hared via
`
`
`
`
(ii)
(i)
5.2
`
`
Clock Signal Routing
For reliable high speed synchronous data transfers, it is essential for the clock signal to have very good signal
integrity. The following recommendations should be taken into consideration when routing the clock signal.

Run the clock signal at least 3x of the trace width away from all other signal traces. This will help keep clock
signal clean from noise, reference Figure 38.

Use as few vias as possible for the entire path of the clock signal. Each via will create impedance changes
and signal reflections.

Run the clock trace as straight as possible and avoid using serpentine routing, reference Figure 39.

Keep a continuous ground in the next layer as a reference plane.

Route the clock trace with controlled impedance, typically a 50 ohm trace impedance with ± 5% tolerance.
Figure 38. Separate Clock from other Traces
X
3X
3X
S ig n a l trace s
C lo ck trace
www.cypress.com
Document No. 001-98508 Rev. *B
27
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Figure 39. Straight Trace Runs for Clock
A void serpen tin e for clock
R un straight trace for clock
5.3
Data Signal Routing
The FL Flash support 1, 2 and 4-bit data bus configurations. In 2 and 4-bit multiple I/O configurations, it is
important that the I/O traces are routed such that they have identical lengths, within ~ 3 mm, to assure equivalent
propagation delays. To assure reliable data transfers for all configurations it is important that the propagation
delays for the clock trace and all data traces are identical.
The data signals should be routed with traces of controlled impedance to reduce signal reflection. Data traces
should have no 90° angle corners. The preferred method for implementing a 90° angle change is to cut the corner
to smooth the trace, reference Figure 40. To maximize signal integrity, avoid using multiple signal layers for data
signal routing and ensure all signal traces have a continuous reference plane.
Figure 40. Signal Routing at the Corner
S h a rp co rn e r cau ses
m o re re flectio n
www.cypress.com
Document No. 001-98508 Rev. *B
S m o o th co rn e r re d uce s
re flection
28
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
5.4
Via Routing
Vias should not be placed within a land pad as this can cause solder wicking inside the via hole, resulting in
misshapen solder joints and electrical opens. Vias should be placed a minimum of 0.3 mm away from the solder
pad as shown in Figure 41.
Figure 41. Recommended via Placement
30
0.
m
m
5.5
Escape Path Routing
Maintaining good signal integrity must be a top priority when considering BGA escape path routing. Only one
signal trace should be routed between any two adjacent land pads, reference Figure 42.
Figure 42. Escape Path Routing (example: FAB024)
6
Summary
The Cypress S25FL/S25FS serial peripheral flash devices utilize industry standard packages. PCB layout for
Cypress SPI flash requires use of standard high speed board layout principals.
www.cypress.com
Document No. 001-98508 Rev. *B
29
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Document History Page
Document Title: AN98508 - Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Document Number: 001-98508
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
–
–
07/02/2010
Initial version
*A
–
–
04/08/2011
SPI Flash Package Drawings: Updated figure: SO3 016 – 16-Pin Wide Plastic Small
Outline Package (300 mil Body Width)
Land Patterns Recommendations: Updated E2 dimension for WSON-8 package
*B
5050808
MSWI
12/1152015
Updated in Cypress template
www.cypress.com
Document No. 001-98508 Rev. *B
30
Cypress Serial Peripheral Interface (SPI) FL Flash Layout Guide
Worldwide Sales and Design Support
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives, and distributors. To find the
office closest to you, visit us at Cypress Locations.
#
999
Products
PSoC® Solutions
Automotive..................................cypress.com/go/automotive
psoc.cypress.com/solutions
Clocks & Buffers ................................ cypress.com/go/clocks
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Interface......................................... cypress.com/go/interface
Cypress Developer Community
Lighting & Power Control ............cypress.com/go/powerpsoc
Memory........................................... cypress.com/go/memory
PSoC ....................................................cypress.com/go/psoc
Touch Sensing .................................... cypress.com/go/touch
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
USB Controllers ....................................cypress.com/go/USB
Wireless/RF .................................... cypress.com/go/wireless
MirrorBit®, MirrorBit® Eclipse™, ORNAND™, EcoRAM™ and combinations thereof, are trademarks and registered trademarks of Cypress Semiconductor Corp. All
other trademarks or registered trademarks referenced herein are the property of their respective owners.
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone:
Fax:
Website:
408-943-2600
408-943-4730
www.cypress.com
© Cypress Semiconductor Corporation, 2010-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation
assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or
other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant
to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a
malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application
implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive,
non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating
custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without
further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein.
Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in
significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in
doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
www.cypress.com
Document No. 001-98508 Rev. *B
31