S71WS-P
1.8 Volt-only Flash with CellularRAM
Features
Power supply voltage of 1.7 to 1.95V
pSRAM burst frequency: 104 MHz
Flash access time: 80 ns, 20 ns
Package:
– 8.0 × 11.6 mm MCP
Flash burst frequencies: 80 MHz, 104 MHz
Operating Temperature
– –25 °C to +85 °C (wireless)
pSRAM Access time: 70 ns, 20 ns
The S71WS series is a product line of stacked packages and consists of:
One S29WS256P NOR flash memory die
CellularRAM die
The products covered by this document are listed in the table below.
CellularRAM Density (Mb)
Device
64 Mb
S29WS256P
S71WS256PC0
Note:
For a full list of OPNs, please contact the local sales representative or refer to the Ordering Information valid combinations tables.
For detailed specifications, please refer to the individual data sheets.
Document
Cypress Document Number
S29WS512/256/128P datasheet
002-01747
64M CellularRAM PN: SWM064D133S1R
SWM064D133S1R
Cypress Semiconductor Corporation
Document Number: 001-98532 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 04, 2016
S71WS-P
1.
Product Selector Guide
Model
Number
Device
S71WS256PC0HH3
YL
S71WS256PC0HH3
YR
Flash Density
(Mb)
CellularRAM
Density (Mb)
256
64
Flash Speed
(MHz)
CellularRAM
Speed (MHz)
CellularRAM Supplier
Package
104
SWM064D133S1R
84 ball MCP
8x11.6x1.2 mm
104
80
2. MCP Block Diagram
A0-Amax
A0-Amax
AFlash
AFlash
RDY
RDY
CLK
AVD#
F-CE#
OE#
F-RST#
F-ACC
F-WP#
F-WE#
CLK
AVD#
CE#
OE#
RESET#
ACC
WP#
WE#
WS-P
Flash
Memory
DQ0-DQ15
DQ0-DQ15
VSS
VSS
VCC
VCCQ
F-VCC
F-VCCQ
A0-Amax
DQ0-DQ15
WAIT
R-CE#
R-LB#
R-UB#
R-CRE
CLK
AVD#
CE#
OE#
LB#
UB#
WE#
CRE
pSRAM
Memory
VSS
VCC
VCCQ
Document Number: 001-98532 Rev. *B
R-VCC
Page 2 of 10
S71WS-P
3. Connection Diagrams
1
2
3
4
5
6
7
8
9
10
A
DNU
DNU
B
AVD#
VSS
CLK
RFU
F-VCC
RFU
RFU
RFU
Legend
C
F-WP#
A7
R-LB#
F-ACC
WE#
A8
A11
RFU
Reserved f
Future Us
D
A3
A6
R-UB# F-RST#
RFU
A19
A12
A15
NOR Flash O
E
A2
A5
A18
RDY
A20
A9
A13
A21
A1
A4
A17
RFU
A23
A10
A14
A22
A0
VSS
DQ1
RFU
RFU
DQ6
A24
A16
F-CE#
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
R-CRE
R-CE#
DQ0
DQ10
F-VCC
R-VCC
DQ12
DQ7
VSS
RFU
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU
RFU
RFU
VSS
F-VCC
RFU
RFU
F-VCCQ
DNU
F
pSRAM Only
G
Flash & pS
Shared On
H
Do Not Us
J
K
L
M
DNU
DNU
Note:
1. VCC pins must ramp simultaneously.
3.1
MCP
Flash-only Addresses
Shared Addresses
S71WS256PC0
A23–A22
A21–A0
Special Handling Instructions For FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data
integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.
3.2
Look-ahead Ballout for Future Designs
Please refer to the Design-in Scalable Wireless Solutions with Cypress Products application note (publication number:
Design_Scalable_Wireless). Contact your local Cypress sales representative for more details.
Document Number: 001-98532 Rev. *B
Page 3 of 10
S71WS-P
3.3
NOR Flash and pSRAM Input/Output Descriptions
Signal
Amax-A0
DQ15-DQ0
F-CE#
Description
Flash
pSRAM
NOR Flash Address inputs
X
X
Flash Data input/output
X
X
NOR Flash Chip-enable input #1. Asynchronous relative to CLK for Burst Mode.
X
OE#
Output Enable input. Asynchronous relative to CLK for Burst mode.
X
X
WE#
Write Enable input.
X
X
F-VCC
NOR Flash device power supply (1.7 V - 1.95 V).
X
Input/Output Buffer power supply.
X
VSS
Ground
X
X
RFU
Reserved for Future Use. No device internal signal is currently connected to the package
connector but there is potential future use for the connector for a signal. It is recommended
to not use RFU connectors for PCB routing channels so that the PCB may take advantage
of future enhanced features in compatible footprint devices.
RDY
Flash ready output. Indicates the status of the Burst read. VOL = data valid. The Flash RDY
pin is shared with the WAIT pin of the pSRAM.
X
X
CLK
NOR Flash Clock, shared with CLK of burst-mode pSRAM.. The first rising edge of CLK in
conjunction with AVD# low latches the address input and activates burst mode operation.
After the initial word is output, subsequent rising edges of CLK increment the internal
address counter. CLK should remain low during asynchronous access.
X
X
NOR Flash Address Valid input. Shared with AVD# of burst-mode pSRAM. Indicates to
device that the valid address is present on the address inputs.
VIL = for asynchronous mode, indicates valid address; for burst mode, causes starting
address to be latched on rising edge of CLK.
VIH= device ignores address inputs
X
X
F-RST#
NOR Flash hardware reset input. VIL= device resets and returns to reading array data
X
F-WP#
NOR Flash hardware write protect input. VIL = disables program and erase functions in the
four outermost sectors.
X
F-ACC
NOR Flash accelerated input. At VHH, accelerates programming; automatically places
device in unlock bypass mode. At VIL, disables all program and erase functions. Should be
at VIH for all other conditions.
X
F-VCCQ
AVD#
R-CE#
Chip-enable input for pSRAM
X
R-CRE
Control Register Enable (pSRAM). For CellularRAM only.
X
R-VCC
pSRAM Power Supply
X
R-UB#
Upper Byte Control (pSRAM)
X
R-LB#
Lower Byte Control (pSRAM)
X
DNU
Do Not Use. A device internal signal may be connected to the package connector. The
connection may be used by Cypress for test or other purposes and is not intended for
connection to any host system signal. Any DNU signal related function will be inactive
when the signal is at VIL. The signal has an internal pull-down resistor and may be left
unconnected in the host system or may be tied to VSS. Do not use these connections for
PCB signal routing channels. Do not connect any host system signal to these connections.
Note: Some customers prefer being able to tie DNU signals to VSS on the PCB.
Document Number: 001-98532 Rev. *B
Page 4 of 10
S71WS-P
4.
Ordering Information
The order number is formed by a valid combinations of the following:
S71WS
256
P
C0
H
H
3
YL
0
PACKING TYPE
0 = Tray
2 = 7” Tape and Reel
3 = 13” Tape and Reel
MODEL NUMBER
Refer to Product Selector Guide on page 2
PACKAGE DESCRIPTOR
3 = 84-ball Fine-pitch BGA, 11.6 mm x 8 mm
MATERIAL SET
H = Low-Halogen, Pb-free
PACKAGE TYPE
H = 1.2 mm MCP FBGA
CellularRAM DENSITY
C0 = 64 Mb
PROCESS TECHNOLOGY
P = 90 nm, MirrorBit® Technology
CODE FLASH DENSITY
256 = 256 Mb
PRODUCT FAMILY
S71WS Stacked Products (MCP)
1.8 V NOR Flash with pSRAM
4.1
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
Valid Combination
Product Family
Code Flash
Denisty (Mb)
Process
Technology
CellularRAM
Density
Package
Type /
Material
Model Number Combo
Packing Type
S71WS
256
P
C0
HH3
YL, YR
0, 2, 3 (Note 1)
Notes:
1. Packing Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading S and packing type designator from ordering part number.
Document Number: 001-98532 Rev. *B
Page 5 of 10
S71WS-P
5.
5.1
Physical Dimensions
TLA084— 84-ball Fine Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package
D1
A
D
eD
0.15 C
(2X)
10
9
SE 7
8
7
6
E
E1
5
4
eE
3
2
1
M L K J
INDEX MARK
PIN A1
CORNER
B
10
TOP VIEW
H G F
E D C
B A
7
SD
0.15 C
PIN A1
CORNER
(2X)
BOTTOM VIEW
0.20 C
A A2
A1
C
0.08 C
SIDE VIEW
6
b
84X
0.15
0.08
M C A B
M C
NOTES:
PACKAGE
TLA 084
JEDEC
N/A
DxE
11.60 mm x 8.00 mm
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.20
A1
0.17
---
---
A2
0.81
---
0.97
NOTE
PROFILE
BODY SIZE
E
8.00 BSC.
BODY SIZE
D1
8.80 BSC.
MATRIX FOOTPRINT
E1
7.20 BSC.
MATRIX FOOTPRINT
MD
12
MATRIX SIZE D DIRECTION
ME
10
MATRIX SIZE E DIRECTION
84
0.35
0.40
2.
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
BALL HEIGHT
11.60 BSC.
n
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
BODY THICKNESS
D
Øb
1.
n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
BALL COUNT
0.45
eE
0.80 BSC.
BALL PITCH
eD
0.80 BSC
BALL PITCH
SD / SE
0.40 BSC.
SOLDER BALL PLACEMENT
A2,A3,A4,A5,A6,A7,A8,A9
DEPOPULATED SOLDER BALLS
B1,B10,C1,C10,D1,D10,
E1,E10,F1,F10,G1,G10,
H1,H10,J1,J10,K1,K10,L1,L10,
M2,M3,M4,M5,M6,M7,M8,M9
Document Number: 001-98532 Rev. *B
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
BALL DIAMETER
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9.
N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3372-2 \ 16-038.22a
Page 6 of 10
S71WS-P
6. Revision History
Spansion Publication Number: S71WS-P_00
Section
Description
Revision 01 (February 21, 2006 to August 17 2012)
Initial Release
Added the S71WS512PC0
Added the S71WS512PD0 108MHz OPN
Added the S71WS256PD0 MCP
Added the S71WS256PC0 MCP
Added new CellularRAM Type 3
Revised Valid Combination table
Revised Product Selector Guide
Added S71WS128PC0 MCP offering
Added the S71WS512PD0JF4 OPN
Added the S71WS512PD0HF3SR OPN
Added 80 MHz S71WS128PC0 to Valid Combinations
Added 54 MHz and Asynchronous S71WS512PC0 MCP
Revised Valid Combinations
Add 104 MHz, 80 Mhz and 66 MHz S71WS256PC, S71WS256PD and S71WS128PC MCP products
Removed the S71WS512PD0JF MCP
Added package TSB084
Added OPNs S71WS128PB0HF3SR/SV
Added low-Halogen options for S71WS128PB0, S71WS128PC0, S71WS256PC0, S71WS256PD0, and
S71WS512PD0
Added 64M CellularRAM Type 2
Updated 128M CellularRAM Type 2 PID
Removed 128M/64M CellularRAM Type 3 OPNs and PIDs
Added CellularRAM Type 3 and associated OPNs
Added CellularRAM PN: SWM128D104R1R and associated OPNs
Changed Flash Page Access time to 20 ns
In Features, changed max Flash burst frequency from 108 MHz to 104 MHz
Removed OPNs S71WS512PD0HH3HL, S71WS256PD0HH3HL, S71WS256PD0HH3HR
Added MCP OPNs S71WS256PC0HH3YR0/L0 and CellularRAM OPN SWM064D133S1R
Added MCP OPNs S71WS128PB0HH3RL0/RR0/RV0 for new 32 Mb CellularRAM OPN SWM032D133S1R
Removed all OPNs except S71WS512PD0HH3YL/YR/YV, S71WS256PC0HH3YR/YL and
S71WS128PB0HH3RL/RR/RV
Removed TSB084 drawing
Removed all OPNs and corresponding references, except S71WS256PC0HH3YR/YL
Document Number: 001-98532 Rev. *B
Page 7 of 10
S71WS-P
Document History Page
Document Title: S71WS-P 1.8 Volt-only Flash with CellularRAM
Document Number: 001-98532
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
–
WIOB
Initial Release
Added the S71WS512PC0
Added the S71WS512PD0 108MHz OPN
Added the S71WS256PD0 MCP
Added the S71WS256PC0 MCP
Added new CellularRAM Type 3
Revised Valid Combination table
Revised Product Selector Guide
Added S71WS128PC0 MCP offering
Added the S71WS512PD0JF4 OPN
Added the S71WS512PD0HF3SR OPN
Added 80 MHz S71WS128PC0 to Valid Combinations
Added 54 MHz and Asynchronous S71WS512PC0 MCP
Revised Valid Combinations
Add 104 MHz, 80 Mhz and 66 MHz S71WS256PC, S71WS256PD and
S71WS128PC MCP products
Removed the S71WS512PD0JF MCP
Added package TSB084
02/21/2006 Added OPNs S71WS128PB0HF3SR/SV
to 08/17/12 Added low-Halogen options for S71WS128PB0, S71WS128PC0,
S71WS256PC0, S71WS256PD0, and S71WS512PD0
Added 64M CellularRAM Type 2
Updated 128M CellularRAM Type 2 PID
Removed 128M/64M CellularRAM Type 3 OPNs and PIDs
Added CellularRAM Type 3 and associated OPNs
Added CellularRAM PN: SWM128D104R1R and associated OPNs
Changed Flash Page Access time to 20 ns
In Features, changed max Flash burst frequency from 108 MHz to 104 MHz
Removed OPNs S71WS512PD0HH3HL, S71WS256PD0HH3HL,
S71WS256PD0HH3HR
Added MCP OPNs S71WS256PC0HH3YR0/L0 and CellularRAM OPN
SWM064D133S1R
Added MCP OPNs S71WS128PB0HH3RL0/RR0/RV0 for new 32 Mb
CellularRAM OPN SWM032D133S1R
Removed all OPNs except S71WS512PD0HH3YL/YR/YV,
S71WS256PC0HH3YR/YL and S71WS128PB0HH3RL/RR/RV
Removed TSB084 drawing
Removed all OPNs and corresponding references, except
S71WS256PC0HH3YR/YL
*A
4965208
WIOB
10/15/2015 Updated to Cypress template.
Document Number: 001-98532 Rev. *B
Page 8 of 10
S71WS-P
Document History Page (Continued)
Document Title: S71WS-P 1.8 Volt-only Flash with CellularRAM
Document Number: 001-98532
Rev.
*B
ECN No.
5162276
Orig. of
Change
PSR
Submission
Date
Description of Change
Updated Features on page 1:
Replaced “S29WS-P” with “S29WS256P”.
Updated table for detailed specifications:
Replaced “S29WS-P” with “S29WS512/256/128P datasheet” in “Document”
03/04/2016 column.
Replaced “Publication Identification Number (PID)” with “Cypress Document
Number” in column heading and replaced “S29WS-P_00” with “002-01747” in
the same column.
Updated to new template.
Document Number: 001-98532 Rev. *B
Page 9 of 10
S71WS-P
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
cypress.com/clocks
Interface
cypress.com/interface
Lighting & Power Control
cypress.com/psoc
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
cypress.com/powerpsoc
Memory
cypress.com/memory
PSoC
cypress.com/psoc
Touch Sensing
Technical Support
cypress.com/support
cypress.com/touch
USB Controllers
cypress.com/usb
Wireless/RF
cypress.com/wireless
© Cypress Semiconductor Corporation 2006-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify
and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license (without the right
to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum
extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or compilation of the Software
is prohibited.
CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of
weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or
hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any
component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole
or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify
and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress
products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-98532 Rev. *B
®
®
®
®
Revised March 04, 2016
Page 10 of 10
Cypress , Spansion , MirrorBit , MirrorBit Eclipse™, ORNAND™, HyperBus™, HyperFlash™, and combinations thereof, are trademarks and registered trademarks of Cypress Semiconductor
Corporation.