ETC CD4541BNSR

[ /Title
(CD45
41B)
/Subject
(CMO
S Programmable
Timer
High
Voltage
Types
(20V
Rating))
/Autho
r ()
/Keywords
(Harris
Semiconductor,
CD400
0,
metal
gate,
CMOS
, pdip,
cerdip,
mil,
military,
mil
CD4541B
CMOS Programmable Timer
High Voltage Types (20V Rating)
Data sheet acquired from Harris Semiconductor
SCHS085A – Revised March 2002
Features
Description
• Low Symmetrical Output Resistance, Typically 100Ω
at VDD = 15V
CD4541B programmable timer consists of a 16-stage binary
counter, an oscillator that is controlled by external R-C components (2 resistors and a capacitor), an automatic power-on
reset circuit, and output control logic. The counter increments
on positive-edge clock transitions and can also be reset via the
MASTER RESET input.
• Built-In Low-Power RC Oscillator
• Oscillator Frequency Range . . . . . . . . . . DC to 100kHz
• External Clock (Applied to Pin 3) can be Used Instead
of Oscillator
The output from this timer is the Q or Q output from the 8th,
10th, 13th, or 16th counter stage. The desired stage is chosen
using time-select inputs A and B (see Frequency Select Table).
The output is available in either of two modes selectable via the
MODE input, pin 10 (see Truth Table). When this MODE input is
a logic “1”, the output will be a continuous square wave having
a frequency equal to the oscillator frequency divided by 2N.
With the MODE input set to logic “0” and after a MASTER
RESET is initiated, the output (assuming Q output has been
selected) changes from a low to a high state after 2N-1 counts
and remains in that state until another MASTER RESET pulse
is applied or the MODE input is set to a logic “1”.
• Operates as 2N Frequency Divider or as a SingleTransition Timer
• Q/Q Select Provides Output Logic Level Flexibility
• AUTO or MASTER RESET Disables Oscillator During
Reset to Reduce Power Dissipation
• Operates With Very Slow Clock Rise and Fall Times
• Capable of Driving Six Low Power TTL Loads, Three
Low-Power Schottky Loads, or Six HTL Loads Over
the Rated Temperature Range
• Symmetrical Output Characteristics
Timing is initialized by setting the AUTO RESET input (pin 5) to
logic “0” and turning power on. If pin 5 is set to logic “1”, the
AUTO RESET circuit is disabled and counting will not start until
after a positive MASTER RESET pulse is applied and returns
to a low level. The AUTO RESET consumes an appreciable
amount of power and should not be used if low-power operation
is desired. For reliable automatic power-on reset, VDD should
be greater than 5V.
• 100% Tested for Quiescent Current at 20V
• 5V, 10V, and 15V Parametric Ratings
• Meets All Requirements of JEDEC Standard No. 13B,
“Standard Specifications for Description of ‘B’ Series
CMOS Devices”
Ordering Information
PART NUMBER
TEMP.
RANGE (oC)
PACKAGE
PKG.
NO.
CD4541BF
-55 to 125
14 Ld CERDIP
F14.3
CD4541BE
-55 to 125
14 Ld PDIP
E14.3
CD4541BH
-55 to 125
Chip
CD4541BM
-55 to 125
14 Ld SOIC
M14.15
CD4541BNSR
-55 to 125
14 Ld SOP
-
The RC oscillator, shown in Figure 2, oscillates with a
frequency determined by the RC network and is calculated
using:
1
f = ----------------------------------2.3 R TC C TC
-
Where f is between 1kHz
and 100kHz
and R S ≥ 10k Ω and ≈ 2R TC
Pinout
CD4541B (CERDIP, PDIP, SOIC, SOP)
TOP VIEW
RTC 1
14 VDD
CTC 2
13 B
RS 3
12 A
NC 4
11 NC
AUTO RESET 5
10 MODE
MASTER RESET 6
9 Q/Q SELECT
8 OUTPUT
VSS 7
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2002, Texas Instruments Incorporated
1
File Number
CD4541B
Functional Diagram
12
A
13
B
1
RTC
2
CTC
3
RS
5
AR
6
MR
10
MODE
9
Q/Q
SELECT
8
Q
VDD = PIN 14
VSS = PIN 7
Functional Block Diagram
12
13
†A †B
R
N
8
P
Q
1 OF 3
MUX
N
P
3
210 213
†RS
2
†CTC
†RTC
8-STAGE
COUNTER
OSC
†Q/Q SELECT
VDD
8-STAGE
COUNTER
1
R
R
10
†MODE
AUTO
RESET†
R
5
9
216
OR
28
PWR ON
RESET
VSS
VDD = 14
VSS = 7
6
MANUAL RESET†
† All inputs are protected by CMOS Protection Network.
NC = 4, 11
FIGURE 1.
FREQUENCY SELECTION TABLE
A
B
NO. OF
STAGES N
COUNT 2N
0
0
13
8192
0
1
10
1024
1
0
8
256
1
1
16
65536
3
TO CLOCK
CKT
RS
INTERNAL
RESET
CTC
2
TRUTH TABLE
1
STATE
PIN
0
RTC
1
5
Auto Reset On
Auto Reset Disable
6
Master Reset Off
Master Reset On
9
Output Initially Low After
Reset (Q)
Output Initially High After
Reset (Q)
10
Single Transition Mode
Recycle Mode
FIGURE 2. RC OSCILLATOR CIRCUIT
2
CD4541B
Absolute Maximum Ratings
Thermal Information
DC Supply - Voltage Range, VDD
Voltages Referenced to VSS Terminal . . . . . . . . . . -0.5V to +20V
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . ±10mA
Device Dissipation Per Output Transistor
For TA = Full Package Temperature Range
(All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW
Package Thermal Impedance, θJA (see Note 1)
PDIP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80oC/W
SOIC package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86oC/W
SOP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76oC/W
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range (TSTG) . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s)
At Distance 1/16in ± 1/32in (1.59mm ±0.79mm)
from case for 10s Maximum . . . . . . . . . . . . . . . . . . . . . . . . 265oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range TA . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range
For TA = Full Package Temperature Range . . . . . 3V (Min), 18V (Typ)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
Electrical Specifications
LIMITS AT INDICATED TEMPERATURES (oC)
CONDITIONS
25
PARAMETER
Quiescent Device
Current,
(Note 2) IDD (Max)
Output Low (Sink)
Current lOL (Min)
Output High (Source)
Current, IOH (Min)
Output Voltage:
Low-Level, VOL (Max)
Output Voltage:
High-Level, VOH (Min)
Input Low Voltage,
VIL (Max)
VO
(V)
VIN
(V)
VDD
(V)
-55
-40
85
125
MIN
TYP
MAX
UNITS
-
0, 5
5
5
5
150
150
-
0.04
5
µA
-
0, 10
10
10
10
300
300
-
0.04
10
µA
-
0, 15
15
20
20
600
600
-
0.04
20
µA
-
0, 20
20
100
100
3000
3000
-
0.08
100
µA
0.4
0, 5
5
1.9
1.85
1.26
1.08
1.55
3.1
-
µA
0.5
0, 10
10
5
4.8
3.3
2.8
4
8
-
µA
1.5
0, 15
15
12.6
12
8.4
7.2
10
20
-
µA
4.6
0, 5
5
-1.9
-1.85
-1.26
-1.08
-1.55
-3.1
-
mA
2.5
0, 5
5
-6.2
-6
-4.1
-3
-5
-10
-
mA
9.5
0, 10
10
-5
-4.8
-3.3
-2.8
-4
-8
-
mA
13.5
0, 15
15
-12.6
-12
-8.4
-7.2
-10
-20
-
mA
-
0, 5
5
-
0.05
-
0
0.05
mA
-
0, 10
10
-
0.05
-
0
0.05
mA
-
0, 15
15
-
0.05
-
0
0.05
mA
-
0, 5
5
-
4.95
4.95
5
-
mA
-
0, 10
10
-
9.95
9.95
10
-
mA
-
0, 15
15
-
14.95
14.95
15
-
mA
0.5, 4.5
-
5
-
1.5
-
-
1.5
V
1, 9
-
10
-
3
-
-
3
V
1.5, 13.5
-
15
-
4
-
-
4
V
3
CD4541B
Electrical Specifications
(Continued)
LIMITS AT INDICATED TEMPERATURES (oC)
CONDITIONS
25
VO
(V)
VIN
(V)
VDD
(V)
-55
0.5, 4.5
-
5
-
1, 9
-
10
1.5, 13.5
-
-
0, 18
PARAMETER
Input High Voltage,
VIH (Min)
Input Current, lIN (Max)
-40
85
MIN
TYP
MAX
UNITS
3.5
3.5
-
-
V
-
7
7
-
-
V
15
-
11
11
-
-
V
18
±0.1
-
±10-5
±0.1
µA
±0.1
±1
125
±1
NOTE:
2. With AUTO RESET enabled, additional current drain at 25oC is:
7µA (Typ), 200µA (Max) at 5V;
30µA (Typ), 350µA (Max) at 10V;
80µA (Typ), 500µA (Max) at 15V
Dynamic Electrical Specifications
PARAMETER
Propagation Delay Times
Clock to Q
TA = 25oC, Input tr , tf = 20ns, CL = 50pF, RL = 200kΩ
SYMBOL
VDD (V)
MIN
TYP
MAX
UNITS
(28) tPHL , tPLH
5
-
3.5
10.5
µs
10
-
1.25
3.8
µs
15
-
0.9
2.9
µs
5
-
6.0
18
µs
10
-
3.5
10
µs
15
-
2.5
7.5
µs
5
-
100
200
ns
10
-
50
100
ns
15
-
40
80
ns
5
-
180
360
ns
10
-
90
180
ns
15
-
65
130
ns
5
900
300
-
ns
10
300
100
-
ns
15
225
85
-
ns
5
-
1.5
-
MHz
10
-
4
-
MHz
15
-
6
-
MHz
(216) tPHL , tPLH
Transition Time
tTHL
tTHL
MASTER RESET, CLOCK
Pulse Width
Maximum Clock Pulse Input
Frequency
Maximum Clock Pulse Input
Rise or Fall time
fCL
tr , tf
5, 10, 15
Unlimited
4
µs
CD4541B
Digital Timer Application
0
10
20
30
40
50
60
70
80 88
82
80
A positive pulse on MASTER RESET resets the counters
and latch. The output goes high and remains high until the
number of pulses, selected by A and B, are counted. This
circuit is retriggerable and is as accurate as the input frequency. If additional accuracy is desired, an external clock
can be used on pin 3. A setup time equal to the width of the
one-shot output is required immediately following initial
power up, during which time the output will be high.
70
60
50
79 - 87
(2.007 - 2.210)
40
30
VDD
RTC
CTC
RS
AR
MR
INPUT
1
14
2
3
4
5
6
13
12
11
10
9
7
8
20
10
B
A
0
4 - 10
(0.102 - 0.254)
85 - 93
(2.159 - 2.362)
OUTPUT
t
NOTE: Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations
are in mils (10-3 inch).
FIGURE 3. DIGITAL TIMER APPLICATION CIRCUIT
FIGURE 4. DIMENSIONS AND PAD LAYOUT FOR CD4541B
5
CD4541B
Dual-In-Line Plastic Packages (PDIP)
N
E14.3 (JEDEC MS-001-AA ISSUE D)
E1
INDEX
AREA
1 2 3
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE
N/2
INCHES
-B-
SYMBOL
-AE
D
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
e
B1
D1
B
0.010 (0.25) M
C
L
eA
A1
eC
C A B S
C
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm).
6
MILLIMETERS
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
B1
0.045
0.070
1.15
1.77
8
C
0.008
0.014
0.204
0.355
-
D
0.735
0.775
18.66
D1
0.005
-
0.13
19.68
-
5
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
6
eB
-
0.430
-
10.92
7
L
0.115
0.150
2.93
3.81
4
N
14
14
9
Rev. 0 12/93
CD4541B
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)
LEAD FINISH
c1
14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
-A-
BASE
METAL
INCHES
(c)
SYMBOL
E
M
-Bbbb S
C A-B S
-C-
S1
-
0.200
-
5.08
-
0.014
0.026
0.36
0.66
2
b1
0.014
0.023
0.36
0.58
3
b2
0.045
0.065
1.14
1.65
-
α
eA
A A
b2
b
ccc M C A - B S
e
D S
eA/2
NOTES
b
A
L
MAX
A
Q
SEATING
PLANE
MIN
M
(b)
D
BASE
PLANE
MILLIMETERS
MAX
b1
SECTION A-A
D S
MIN
c
b3
0.023
0.045
0.58
1.14
4
c
0.008
0.018
0.20
0.46
2
c1
0.008
0.015
0.20
0.38
3
D
-
0.785
-
19.94
5
E
0.220
0.310
5.59
7.87
5
e
aaa M C A - B S D S
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
-
eA/2
0.150 BSC
3.81 BSC
-
L
0.125
0.200
3.18
5.08
-
Q
0.015
0.060
0.38
1.52
6
S1
0.005
-
0.13
-
7
α
90o
105o
90o
105o
-
aaa
-
0.015
-
0.38
-
bbb
-
0.030
-
0.76
-
ccc
-
0.010
-
0.25
-
M
-
0.0015
-
0.038
2, 3
N
14
14
8
Rev. 0 4/94
7
CD4541B
Small Outline Plastic Packages (SOIC)
M14.15 (JEDEC MS-012-AB ISSUE C)
N
INDEX
AREA
H
0.25(0.010) M
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
B M
E
INCHES
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
0.25(0.010) M
α
C A M
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.3367
0.3444
8.55
8.75
3
E
0.1497
0.1574
3.80
4.00
4
e
C
0.10(0.004)
B S
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
8
MILLIMETERS
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
N
α
14
0o
1.27
14
8o
0o
6
7
8o
Rev. 0 12/93
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