AN1057 TAXI™ to Cypress CY7C9689A Hotlink® Transceiver Conversion Series: 1. System Parallel Interface Associated Project: No Associated Part Family: CY7C9689A Software Version: NA Related Application Notes: None To get the latest version of this application note, or the associated project file, please visit http://www.cypress.com/go/AN1057. AN1057 discusses about the system parallel interface built with the CY7C9689A that are directly compatible with the legacy systems made using AMD TAXI™. Introduction The Cypress CY7C9689A TAXI-compatible HOTLink® Transceiver facilitates point-to-point data communication over high-speed serial links. Systems built with the CY7C9689A are directly compatible with legacy systems made using AMD TAXI chip devices. The CY7C9689A HOTLink Transceiver is functionally equivalent to an AMD AM7968 TAXI transmitter and AM7969 receiver pair, with numerous technology enhancements and extensions. Time has moved on, and the AMD TAXI chipset has been left behind. The TAXI chipset is a full bipolar design and consumes approximately 3 W of power. The CY7C9689A is designed on 0.35-mm CMOS technology and consumes only 30% of the power of the AMD chipset. The CY7C9689A contains both transmit and receive functions, and integrates separate transmit and receive FIFOs in the same device. The CY7C9689A is available in a 100-pin TQFP package, offering significant board real estate savings. It operates from 50 MBd to 200 MBd, while the TAXI chipset has a maximum serial signaling rate of 175 MBd. In addition, the AMD TAXI chipset has been discontinued, leaving numerous designs and products in jeopardy. www.cypress.com Fortunately, the CY7C9689A is a simple replacement for the TAXI chipset that requires little change in surrounding system logic. The CY7C9689A allows the continued use and manufacturing of these legacy systems with minimal impact to the equipment, and enables new designs with up-to-date technology. By replacing the TAXIchip devices with the CY7C9689A, it is possible to maintain compatibility with those systems deployed in the field, while increasing integration, lowering power requirements, and improving reliability. Although the CY7C9689A is not pin-for-pin compatible with the TAXI device, the CY7C9689A parallel interface and serial interface can be mapped onto the TAXI functional pins with minimal external logic. Since the CY7C9689A was designed with modern systems in mind, it has many enhanced functions that the TAXI lacks. The objective of this document is to show the basic configuration of the CY7C9689A for replacing the TAXI chipset in the most general applications. Document No. 001-34342 Rev. *C 1 ® TAXI™ to Cypress CY7C9689A HOTLink Transceiver Conversion Series: 1. System Parallel Interface Figure 1. TAXI vs. CY7C9689A System Parallel Interface M-bit N-bit CY7C9689A HOT Link TX DATA AM7968 TAXI TX DATA SEROUT COMMAND COMMAND OUT STRB ACK M-bit N-bit TXEN REFCLK TX External Logic TXFULL TXSC/D STRB ACK Note: M+N=12 AM7969 TAXI RX M-bit RX DATA M-bit DATA N-bit N-bit SERIN IN COMMAND VLTN DSTRB RXSC/D CSTRB Overview The TAXI chipset, when operating in 8- or 10-bit mode, uses 4B/5B or 5B/6B encoding and decoding respectively. The encoded data is further enhanced for serial transmission by NRZI coding. The CY7C9689A Transceiver uses the same 4B/5B, 5B/6B, and NRZI encoding and decoding. This allows direct communication between the CY7C9689A and TAXI devices at the serial interface. Figure 1 shows how a CY7C9689A transceiver would be connected in a serial link with the TAXI chipset. While both the serial and parallel interfaces of the CY7C9689A are compatible with the corresponding interface of the AMD TAXI devices, the devices are not identical. This application note discusses the replacement of TAXI chipset with the CY7C9689A in existing system interfaces. www.cypress.com COMMAND VLTN RXEN RXCLK RX External Logic DSTRB CSTRB Converting TAXI to CY7C9689A Parallel Interface The parallel interface of the TAXI transmitter and receiver is based on a strobe/acknowledge interface that is seldom used in present-day designs. The transmit and receive parallel-data interface on the CY7C9689A makes use of a much more predictable and easier to control clocked (synchronous) interface. Although this clocked interface is different from that of the original TAXI, it can generally be interfaced with existing system logic with minimal changes. Transmitter System Interface Bus Mapping The AM7968 TAXI transmitter parallel interface consists of an N-bit data bus, an M-bit command bus (N = 8, 9, or 10, where N+M=12), a write strobe, and an acknowledge signal. For example, when configured for 8-bit data, the TAXI data bus is eight bits wide and the command bus is four bits wide. Document No. 001-34342 Rev. *C 2 ® TAXI™ to Cypress CY7C9689A HOTLink Transceiver Conversion Series: 1. System Parallel Interface The CY7C9689A data and command buses are organized in exactly the same fashion. Unlike the TAXI devices (which support 8, 9, or 10-bit data paths), the CY7C9689A only supports 8- and 10-bit modes. Within the CY7C9689A, the data path bus-width is controlled by the BYTE8/10 ¯¯ signal. When configured to transport 8-bit data (BYTE8/10 ¯¯ = HIGH), the CY7C9689A data bus is eight bits wide and its command bus is four bits wide. When configured to transport 10-bit data (BYTE8/10 ¯¯ = LOW), the CY7C9689A data bus is ten bits wide and its command bus is two bits wide. With the TAXI transmitter and receiver, the data bus width is configured using the DMS signal. Figure 2 shows the setting of the DMS and BYTE8/10 ¯¯ signals to configure both the TAXI and CY7C9689A for 8-bit data and 4-bit command bus-widths. Transmitter Interface Control Signaling T AX I T r a n s m i t t e r S T R B a n d AC K Data is latched into the TAXI transmitter using a strobe pulse called STRB. The STRB input on the TAXI transmitter can often be treated as an asynchronous signal with respect to the reference clock input and the CLK output. The TAXI transmitter latches information present on the data and command buses on the rising edge of the STRB input. When this captured information is transferred out of the TAXI-transmitter input register, it provides an acknowledge pulse (ACK) back to the system to confirm reception of the data or command information, and to indicate that the input register is ready to accept new data/command information. This asynchronous STRB/ACK interface was appropriate at the time when the TAXI chipset was introduced into the market. Figure 2. 8-bit Data Bus Configuration AM7968 TAXI TX 8-bit VDD DATA COMMAND 4-bit 9 bit DMS 10 bit 8 bit GND 8-bit COMMAND 10 bit When the FIFOs in the CY7C9689A are bypassed (FIFOBYP ¯¯¯¯¯¯¯¯ = LOW) and the REFCLK input is configured to operate at twice the character rate, the ¯¯¯¯¯¯¯ TXFULL flag becomes a character-rate clock output. ¯¯¯¯¯¯¯ TXFULL also indicates which REFCLK cycle the transmitter is ready to accept data. The transmitter captures data on each rising edge of REFCLK when both ¯¯¯¯¯¯¯ TXFULL and ¯¯¯¯¯ TXEN are LOW (see Figure 4). When the system STRB output is synchronous to the system CLK (i.e., ¯¯¯¯¯¯¯ TXFULL ), then the system STRB signal can be connected to the ¯¯¯¯¯ TXEN input of the CY7C9689A through an inverter. Figure 3. TX External Logic CY7C9689A FIFOBYP GND TXEN STRB CLK 2X char rate TXFULL REFCLK ACK COMMAND VD D AM7969 TAXI RX GND 4-bit 9 bit The parallel interface of the CY7C9689A no longer makes use of a strobe to capture data. It follows the more modern construct of a synchronous interface. However, using a small amount of external logic, it is possible to emulate the strobe-based interface of a TAXI transmitter on the CY7C9689A. This external transmit logic is shown in Figure 3, and requires that the CY7C9689A be configured for use with a 2x reference clock (REFCLK) input. D Q 8 bit DATA VDD TX 8-bit 4-bit C o n ve r t i n g S T R B t o ¯T¯X¯E¯N¯ System CY7C9689A DATA Although this strobed interface is (by definition) asynchronous, most applications implement STRB synchronous to the character-clock output (CLK) of the TAXI transmitter. This is necessary (when the TAXI transmitter is loaded at or near the character-clock rate) to avoid the “Strobe Stayout Area” or “t6 window” located around the falling edge of CLK. To ensure that STRB assertion remains outside of the stayout area, most systems generate STRB synchronous to CLK. 10 bit BYTE8/10* Optional RX M-bit 8-bit DATA Command TXSC/D 4-bit COMMAND DMS 8 bit GND www.cypress.com Document No. 001-34342 Rev. *C 3 ® TAXI™ to Cypress CY7C9689A HOTLink Transceiver Conversion Series: 1. System Parallel Interface With the circuit in Figure 3, the STRB signal can pulse once per character as it does in a normal TAXI system. It may also remain HIGH when characters to be sent are present on the command/data bus. To prevent duplicate or invalid characters from being sent, STRB must be deasserted after the last valid character is captured. If STRB stays asserted after acknowledgement, anything on the data/command bus will be latched on the subsequent REFCLK cycle when ¯¯¯¯¯¯¯ TXFULL is LOW. This information must also remain valid until the hold time (from the rising edge of REFCLK) is satisfied. Figure 4. TX External Logic Timing Figure 5. Alternative TX External Logic Timing R EF C LK T XF U LL S T RB T X EN D AT A/ C OMM AN D T XSC / D R EF C LK VA LID T XF U LL Figure 6. Asynchronous TX External Logic S T RB CY7C9689A System VDD T X EN FIFOBYP TXEN A CK D ATA / C OM M AN D Optional GND STRB VAL ID Optional T X SC /D When ¯¯¯¯¯ TXEN is asserted (and ¯¯¯¯¯¯¯ TXFULL is LOW), latching of the information on the data/command bus is guaranteed at the correct REFCLK cycle. Therefore, the ACK handshake signal is optional and can be omitted (if not required by the system). C o n ve r t i n g S T R B t o ¯T¯X¯E¯N¯ ( s y n c h r o n o u s t o C L K / ¯T¯X¯F¯U¯L¯L¯ ) With a slight change to the circuit in Figure 3, it is possible to alter the method of enabling write operations to the CY7C9689A transmit interface (see Figure 5). Here the CY7C9689A does not directly use the STRB signal. Instead, it captures the information on the data/command bus on the rising edge of REFCLK when both ¯¯¯¯¯¯¯ TXFULL and ¯¯¯¯¯ TXEN are LOW. This allows STRB and ¯¯¯¯¯ TXEN to be generated relative to the rising edge of ¯¯¯¯¯¯¯ TXFULL /CLK. This eliminates the need for designing external logic at a 2X character rate. (REFCLK must still operate at twice the character rate.) www.cypress.com ACK 1X, 2X, or 4X char rate Command TXCLK Delay Element REFCLK M-bit TXSC/D When STRB/TXEN ¯¯¯¯¯ is generated relative to ¯¯¯¯¯¯¯ TXFULL , latching of the information on the data/command bus is guaranteed to occur within the correct REFCLK cycle. Again, the ACK handshake signal can be omitted. I n t e r f a c i n g As y n c h r o n o u s S T R B a n d AC K t o CY7C9689A In spite of the TAXI transmitter’s “Strobe Stayout Area” requirement, some legacy systems with low data-rate requirements still use asynchronous STRB/ACK handshaking. Document No. 001-34342 Rev. *C 4 ® TAXI™ to Cypress CY7C9689A HOTLink Transceiver Conversion Series: 1. System Parallel Interface To interface the CY7C9689A to these asynchronous system interfaces, the internal FIFO must be enabled (TXEN ¯¯¯¯¯ = HIGH). Figure 6 shows the circuit connections between the asynchronous system interface and the CY7C9689A. The delay element used for ACK generation must be such that the FIFO cannot be loaded faster than the characters are read from the FIFO and transmitted. This allows the system to be built without monitoring the ¯¯¯¯¯¯¯ TXFULL FIFO status flag. If the generation of STRB pulses is self-limiting (due to the speed at which characters are made available by the system), the generation of ACK may be as simple as a direct connection between STRB and ACK. The operation of this asynchronous interface is similar to the TAXI transmitter input latch. The system STRB is connected directly to the TX FIFO write clock (TXCLK). This latches data or commands into the FIFO input register at the rising edge of the TXCLK. ACK is generated directly by STRB (or a time delayed form of STRB) as shown in Figure 7. Upon the falling edge of STRB/TXCLK, the data in the input register is transferred into the FIFO. Upon the next rising edge of STRB/TXCLK (which writes the next data/command character into the input register), the internal FIFO pointers are updated, and the internal transmit state machine reads this character from the TX FIFO for serial transmission. Because the TX FIFO requires a following rising edge on TXCLK to update the internal FIFO pointers, it may be necessary to write a dummy SYNC character to the command bus after the last data/command character to allow that character to be transmitted. This extra write operation ensures that the last data/command character of a burst or packet is transmitted before the first character of the next burst. Receiver System Interface Bus Mapping Just like the Transmit Data and Command Bus, the Receive Data and Command Bus mapping of the CY7C9689A is exactly the same as the TAXI in 8- and 10bit modes. The CY7C9689A also has a Violation (VLTN) output to indicate when characters are received that do not match any valid data or command character. Figure 7. Asynchronous TX External Logic Timing ST R B/T XC L K T X EN A CK D AT A/ C OM MA ND T XSC / D VALI D Figure 8. RXSC/¯¯ D to DSTRB and CSTRB Translation CY7C9689A System RXSC/D Data and Command Transmission DSTRB RXCLK The TAXI transmitter switches between Data and Command transmission by examining the Command bus inputs. An all zero pattern on the Command bus (when a character is captured) causes Data to be sent. Any nonzero pattern on the Command bus causes the associated command character to be sent. www.cypress.com The system logic for a TAXI transmit interface normally contains an internal signal which determines when the Command bus needs to be “zeroed” for transmission of data. In the CY7C9689A, the TXSC/¯¯ D input serves this same purpose. It determines whether a Data or Command character is captured on the current write cycle. When TXSC/¯¯ D is sampled LOW, a Data character is captured. If TXSC/¯¯ D is sampled HIGH, a Command character is captured. If a signal is not available to drive TXSC/¯¯ D ,a simple OR gate can be used to combine all the Command signals to drive the TXSC/¯¯ D input (as shown in Figure 3). RXEN CSTRB FIFOBYP Document No. 001-34342 Rev. *C GND 5 ® TAXI™ to Cypress CY7C9689A HOTLink Transceiver Conversion Series: 1. System Parallel Interface Receiver System Interface Control Signaling T AX I r e c e i ve r D S T R B a n d C S T R B Upon reception of valid serial data, the TAXI receiver decodes the incoming data and presents the decoded Data or Command character on the Data/Command bus. It then notifies the system that a Data or Command character is available on the bus by asserting the data strobe (DSTRB) or command strobe (CSTRB) respectively. CY7C9689A Synchronous Parallel Interface Generation of DSTRB and CSTRB When configured as a synchronous interface, the internal receive FIFO of the CY7C9689A is bypassed (FIFOBYP ¯¯¯¯¯¯¯¯ = LOW), and RXCLK becomes the recovered clock output. The data and command buses on the CY7C9689A receive interface are synchronized with the RXCLK output. Unlike REFCLK (which may be configured for 1X or 2X character-rate operation), RXCLK switches only at the recovered character-rate frequency. With the receive FIFO bypassed, the Data/Command bus (with VLTN) is updated at every RXCLK cycle. RXEN ¯¯¯¯¯ must be asserted LOW to enable the Data/Command Bus. The RXSC/¯¯ D output signal indicates whether the information on the Data/Command bus is a data character or a command character. As the transmit parallel interface, it is easy to translate this receive synchronous interface to a strobe based interface. The circuitry shown in Figure 8 translates RXCLK and RXSC/¯¯ D into DSTRB and CSTRB. C Y 7 C 9 6 8 9 A As y n c h r o n o u s P a r a l l e l I n t e r f a c e Generation of DSTRB and CSTRB When the internal FIFOs are enabled to allow asynchronous operation (FIFOBYP ¯¯¯¯¯¯¯¯ = HIGH), RXCLK becomes an input. A free running character-rate clock must be used to drive the RXCLK input. This clock may be completely asynchronous to the internal recovered clock, and is usually operated faster than the received characterrate to prevent the receive FIFO from overflowing (with the resulting loss of data). When the FIFO is empty, the RXEMPTY flag is asserted to indicate that the information on the data/command bus is not valid. Figure 9 shows an implementation of DSTRB and CSTRB with the CY7C9689A internal FIFOs enabled. This circuit assumes the free-running character-rate clock has 40/60 (or better) duty cycle, to ensure that the received data and flag are stable before the falling edge of the clock. www.cypress.com CY7C9689A Static Control Configuration To emulate the TAXI chipset, the CY7C9689A can be configured to its most basic functional form. The configurations of CY7C9689A static inputs for TAXI parallel interface emulation are summarized in Table 1. Table 1. CY7C9689A Static Input Configurations for TAXI Asynchronous Parallel Interface Emulation Static Signals 50–100 MBd 100–200 MBd ¯¯¯¯¯¯¯¯ FIFOBYP High High ENCBYP ¯¯¯¯¯¯¯ High High EXTFIFO Low Low SPDSEL Low High RANGESEL Low High RXMODE[1] Low Low RXMODE[0] Low Low ¯¯¯¯¯¯¯¯¯ TXBISTEN High High RXBISTEN ¯¯¯¯¯¯¯¯¯ High High RFEN High High ¯¯¯ CS Low Low ¯¯¯¯¯¯¯¯ FIFOBYP The TAXI transmitter does not have integrated FIFOs (beyond the two-character FIFO used for synchronizing the internal state machine with the external asynchronous strobe-base interface). Figure 9. RXSC/¯¯ D to DSTRB and CSTRB Translation CY7C9689A System RXSC/D RXCLK RXEMPTY DSTRB FIFOBYP RXEN VD D GND CSTRB Char. rate Clk For synchronous parallel interface implementations, the CY7C9689A internal 256-character FIFOs must be bypassed by asserting ¯¯¯¯¯¯¯¯ FIFOBYP LOW. For asynchronous parallel interface implementation, the internal FIFOs must be enabled by asserting ¯¯¯¯¯¯¯¯ FIFOBYP HIGH. Document No. 001-34342 Rev. *C 6 ® TAXI™ to Cypress CY7C9689A HOTLink Transceiver Conversion Series: 1. System Parallel Interface ENCBYP ¯¯¯¯¯¯¯ ¯¯¯¯¯¯¯¯¯ TXBISTEN and RXBISTEN ¯¯¯¯¯¯¯¯¯ The 4B/5B or 5B/6B encoder and decoder of the CY7C9689A are enabled by asserting ENCBYP ¯¯¯¯¯¯¯ HIGH. When BYTE8/10 ¯¯ is asserted HIGH (8-bit mode), the dual 4B/5B encoders are enabled. When BYTE8/10 ¯¯ is asserted LOW (10-bit mode), the dual 5B/6B encoders are enabled. The CY7C9689A has Built-In-Self-Test (BIST) functions on both the transmitter and receiver. The BIST state machine in the transmitter provides a predictable but pseudo-random sequence that can be matched to an identical state machine in the receiver. This is a powerful feature for serial link testing and debugging. For normal link operation, BIST must be turned off on both the transmitter and receiver by deasserting ¯¯¯¯¯¯¯¯¯ TXBISTEN and RXBISTEN ¯¯¯¯¯¯¯¯¯ to HIGH. Because this BIST capability is not present in the TAXI devices, it can only be used for link validation with other CY7C9689A devices. EXTFIFO The external FIFO enable input (EXTFIFO) changes the parallel interface timing of the CY7C9689A for direct connect to an external synchronous FIFO like the Cypress CY7C42XX 18-bit FIFO. Most existing TAXI systems interface to system logic devices (e.g., an ASIC, FPGA, or CPLD) and do not directly interface to FIFOs. For the implementations discussed in this document, we assume that the CY7C9689A does not connect to an external synchronous FIFO, therefore EXTFIFO must be LOW. RFEN Reframe enable (RFEN) input controls the internal character framer of the CY7C9689A. This input must be HIGH for the framer to adjust the internal character boundaries upon reception of SYNC characters. To emulate the TAXI receiver, the RFEN input must be HIGH. SPDSEL and RANGESEL For emulating the TAXI parallel interface using the external logic discussed in this application note, it is recommended that REFCLK operate at twice the character rate. For serial links operating between 50–100 MBd, RANGESEL and SPDSEL must be LOW. The REFCLK frequency should range from 10 MHz to 20 MHz in 8-bit mode, and from 8.33 MHz to 16.67 MHz in 10-bit mode. For 100–200 MBd operation, RANGESEL and SPDSEL must be HIGH. The REFCLK frequency should range from 20 MHz to 40 MHz in 8-bit mode, and 16.67 MHz to 33.33 MHz in 10-bit mode. ¯¯¯ CE The Chip Enable (¯¯¯ CE ) input must be LOW to enable the transmit and receive parallel interfaces. This enables the FIFO status indicator/flags at all times. Without ¯¯¯ CE asserted, the ¯¯¯¯¯ TXEN and RXEN ¯¯¯¯¯ interface enables are not recognized. Summary This concludes how to convert TAXI to CY7C9689A parallel interface with Transmitter/Receiver Bus Mapping along with static input configuration. RXMODE[1:0] The CY7C9689A has built-in SYNC-character filtering for received data. Filtering modes are controlled by the RXMODE[1:0] inputs. These character filters can be used to remove SYNC characters in a controlled fashion. Since the TAXI receiver does not have a character filter, and all received SYNC characters are output with a CSTRB pulse, both RXMODE inputs should be configured LOW to emulate the normal operation of the TAXI receiver. This causes all received characters and commands (including all SYNC characters) to be written to the output register for synchronous operation or into the receive FIFO for asynchronous operation. www.cypress.com Document No. 001-34342 Rev. *C 7 ® TAXI™ to Cypress CY7C9689A HOTLink Transceiver Conversion Series: 1. System Parallel Interface Document History Document Title: TAXI™ to Cypress CY7C9689A HOTLink® Transceiver Conversion Series: 1. System Parallel Interface AN1057 Document Number: 001-34342 Revision ECN Orig. of Change Submission Date Description of Change ** 1505083 YIS 04/09/2000 New application note. *A 3059376 SAAC 10/14/2010 No technical updates. *B 3416014 SAAC 10/20/2011 Added Abstract. Changed part number from CY7C9689 to CY7C9689A throughout the document. Updated CY7C9689A Static Control Configuration: Updated ¯¯¯¯¯¯¯¯¯ TXBISTEN and RXBISTEN ¯¯¯¯¯¯¯¯¯ : Removed the line "For more information, refer the Application Note "HOTLink Built-In-Self-Test". Added Summary. Updated to new template. *C 4572887 YLIU 11/18/2014 Updated to new template. Completing Sunset Review. www.cypress.com Document No. 001-34342 Rev. *C 8 ® TAXI™ to Cypress CY7C9689A HOTLink Transceiver Conversion Series: 1. System Parallel Interface Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. www.cypress.com Document No. 001-34342 Rev. *C 9