TLK1201ARCP, TLK1201AIRCP ETHERNET TRANSCEIVERS www.ti.com • • • • • • • • • • • • • • • No External Filter Capacitors Required Comprehensive Suite of Built-In Testability IEEE 1149.1 JTAG Support 2.5-V Supply Voltage for Lowest Power Operation 3.3-V Tolerant on LVTTL Inputs Hot Plug Protection 64-Pin VQFP With Thermally Enhanced Package (PowerPAD™) CPRI Data Rate Compatible (614 Mbps, 1.22 Gbps) Industrial Temperature Range Supported: –40°C to 85°C GNDPLL VDD TXP TXN VDDA VDDA GNDA VDDA JTRSTN JTMS RXP VDDA RXN GNDA • 0.6-Gbps to 1.3-Gbps Serializer/Deserializer Low Power Consumption <200 mW at 1.25 Gbps LVPECL Compatible Differential I/O on High Speed Interface Single Monolithic PLL Design Support For 10-Bit Interface or Reduced Interface 5-Bit DDR (Double Data Rate) Clocking Receiver Differential Input Thresholds 200 mV Minimum IEEE 802.3 Gigabit Ethernet Compliant ANSI X3.230-1994 (FC-PH) Fibre Channel Compliant Advanced 0.25-µm CMOS Technology 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 JTDI SYNC/PASS GND RD0 RD1 RD2 VDD RD3 RD4 RD5 RD6 VDD RD7 RD8 RD9 GND TESTEN VDDPLL LOOPEN VDD GND REFCLK VDD SYNCEN GND LOS JTDO ENABLE VDD RBC1 RBC0 RBCMODE GND TD0 TD1 TD2 VDD TD3 TD4 TD5 TD6 VDD TD7 TD8 TD9 GND MODESEL PRBSEN VDD TCK • • SLLS580A – FEBRUARY 2004 – REVISED JUNE 2004 DESCRIPTION The TLK1201A/TLK1201AI gigabit ethernet transceiver provides for ultrahigh-speed, full-duplex, point-to-point data transmissions. This device is based on the timing requirements of the 10-bit interface specification by the IEEE 802.3 gigabit ethernet specification and is also compliant with the ANSI X3.230-1994 (FC-PH) fibre channel standard. The device supports data rates from 0.6 Gbps to 1.3 Gbps. The primary application of the transceiver is to provide building blocks for point-to-point baseband data transmission over controlled impedance media of 50 Ω or 75 Ω. The transmission media can be printed-circuit board traces, copper cables, or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated TLK1201ARCP, TLK1201AIRCP ETHERNET TRANSCEIVERS www.ti.com SLLS580A – FEBRUARY 2004 – REVISED JUNE 2004 The transceiver performs the data serialization, deserialization, and clock extraction functions for a physical layer interface device. The transceiver operates at 1.25 Gbps (typical), providing up to 1 Gbps of data bandwidth over a copper or optical media interface. The transceiver supports both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing double data rate (DDR) clocking. In the TBI mode the serializer/deserializer (SERDES) accepts 10-bit wide 8b/10b parallel encoded data bytes. The parallel data bytes are serialized and transmitted differentially at PECL compatible voltage levels. The SERDES extracts clock information from the input serial stream and deserializes the data, outputting a parallel 10-bit data byte. In the DDR mode the parallel interface accepts 5-bit wide 8b/10b encoded data aligned on both the rising and falling edges of the reference clock. The data is clocked most significant bit first (bits 0–4 of the 8b/10b encoded data) on the rising edge of the clock and the least significant bits (bits 5–9 of the 8b/10b encoded data) are clocked on the falling edge of the clock. The transceiver provides a comprehensive series of built-in tests for self-test purposes including loopback and pseudorandom binary sequence (PRBS) generation and verification. An IEEE 1149.1 JTAG port is also supported. The transceiver is housed in a high-performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is recommended that the device PowerPAD be soldered to the thermal land on the board. The transceiver is characterized for operation from 0°C to 70°C (TLK1201A) or –40°C to 85°C (TLK1201AI). The transceiver uses a 2.5-V supply. The I/O section is 3.3-V compatible. With a 2.5-V supply the chipset is very power-efficient, dissipating less than 200 mW typical power when operating at 1.25 Gbps. The transceiver is designed to be hot plug capable. A power-on reset causes RBC0, RBC1, the parallel output signal terminals, TXP, and TXN to be held in a high-impedance state. Differences Between TLK1201A/TLK1201AI and TNETE2201 The TLK1201A/TLK1201AI transceiver is the functional equivalent of the TNETE2201. There are several differences between the devices as noted below. See Figure 12 in the Application Information section for an example of a typical application circuit. • The VCC is 2.5 V for the TLK1201A vs 3.3 V for TNETE2201. • The PLL filter capacitors on terminals 16, 17, 48, and 49 of the TNETE2201 are no longer required. The TLK1201A uses these terminals to provide added test capabilities. The capacitors, if present, do not affect the operation of the device. • No pulldown resistors are required on the TXP/TXN outputs. AVAILABLE OPTIONS TA 2 PACKAGE PLASTIC QUAD FLAT PACK (RCP) 0°C to 70°C TLK1201ARCP –40°C to 85°C TLK1201AIRCP TLK1201ARCP, TLK1201AIRCP ETHERNET TRANSCEIVERS www.ti.com SLLS580A – FEBRUARY 2004 – REVISED JUNE 2004 BLOCK DIAGRAM PRBSEN LOOPEN PRBS Generator TD(0-9) TXP 2:1 MUX Parallel to Serial TXN 10 Bit Registers Clock Phase Generator REFCLK MODESEL ENABLE TESTEN Control Logic PRBS Verification RBC1 RBC0 SYNC/PASS Interpolator and Clock Extraction 2:1 MUX Clock Clock Serial to Parallel and Comma Detect RD(0-9) 2:1 MUX Data RXP RXN SYNCEN LOS RBCMODE JTMS JTAG Control Register JTRSTN JTDI TCK JTDO Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION SIGNAL MODESEL 15 I P/D (1) LOS 26 O RBCMODE 32 I P/D (1) Receive clock mode select. When RBCMODE and MODESEL are low, half-rate clocks are output on RBC0 and RBC1. When MODESEL is low and RBCMODE is high, a full baud-rate clock is output on RBC0 and RBC1 is held low. When MODESEL is high, RBCMODE is ignored and a full baud-rate clock is output on RBC0 and RBC1 is held low. RBC0 RBC1 31 30 O Receive byte clock. RBC0 and RBC1 are recovered clocks used for synchronizing the 10-bit output data on RD0–RD9. The operation of these clocks is dependent upon the receive clock mode selected. In the half-rate mode, the 10-bit output data words are valid on the rising edges of RBC0 and RBC1. These clocks are adjusted to half-word boundaries in conjunction with synchronous detect. The clocks are always expanded during data realignment and never slivered or truncated. RBC0 registers bytes 1 and 3 of received data. RBC1 registers bytes 0 and 2 of received data. In the normal rate mode, only RBC0 is valid and operates at 1/10th the serial data rate. Data is aligned to the rising edge. In the DDR mode, only RBC0 is valid and operates at 1/10th the serial data rate. Data is aligned on both the rising and falling edges. (1) Mode select. This terminal selects between the 10-bit interface and a reduced 5-bit DDR interface. When low, the 10-bit interface (TBI) is selected. When pulled high, the 5-bit DDR mode is selected. The default mode is the TBI. Loss of signal. Indicates a loss of signal on the high-speed differential inputs RXP and RXN. If the magnitude of RXP-RXN > 150 mV, then LOS = 1 which is a valid input signal. If the magnitude of RXP-RXN > 50 mV and < 150 mV, then LOS is undefined. If the magnitude of RXP-RXN < 50 mV, then LOS = 0 which is a loss of signal. P/D = Internal pulldown 3 TLK1201ARCP, TLK1201AIRCP ETHERNET TRANSCEIVERS www.ti.com SLLS580A – FEBRUARY 2004 – REVISED JUNE 2004 Terminal Functions (continued) TERMINAL I/O DESCRIPTION 45, 44, 43, 41, 40, 39, 38, 36, 35, 34 O Receive data. When in TBI mode (MODESEL = low), these outputs carry 10-bit parallel data output from the transceiver to the protocol layer. The data is referenced to terminals RBC0 and RBC1, depending on the receive clock mode selected. RD0 is the first bit received.When in the DDR mode (MODESEL = high), only RD0–RD4 are valid. RD5–RD9 are held low. The 5-bit parallel data is clocked out of the transceiver on the rising edge of RBC0. REFCLK 22 I Reference clock. REFCLK is an external input clock that synchronizes the receiver and transmitter interface (60 MHz to 130 MHz). The transmitter uses this clock to register the input data (TD0–TD9) for serialization.In the TBI mode that data is registered on the rising edge of REFCLK. In the DDR mode, the data is registered on both the rising and falling edges of REFCLK with the most significant bits aligned on the rising edge of REFCLK. RXP RXN 54 52 PECL I Differential input receive. RXP and RXN together are the differential serial input interface from a copper or an optical I/F module. SYNCEN 24 I P/U (2) Synchronous function enable. When SYNCEN is high, the internal synchronization function is activated. When this function is activated, the transceiver detects the K28.5 comma character (0011111 negative beginning disparity) in the serial data stream and realigns data on byte boundaries if required. When SYNCEN is low, serial input data is unframed in RD0–RD9. SYNC/PASS 47 O Synchronous detect. The SYNC output is asserted high upon detection of the comma pattern in the serial data path. SYNC pulses are output only when SYNCEN is activated (asserted high). In PRBS test mode (PRBSEN = high), SYNC/PASS outputs the status of the PRBS test results (high = pass). 2-4, 6-9, 11-13 I Transmit data. When in the TBI mode (MODESEL = low) these inputs carry 10-bit parallel data output from a protocol device to the transceiver for serialization and transmission. This 10-bit parallel data is clocked into the transceiver on the rising edge of REFCLK and transmitted as a serial stream with TD0 sent as the first bit. When in the DDR mode (MODESEL = high) only TD0–TD4 are valid. The 5-bit parallel data is clocked into the transceiver on the rising and falling edge of REFCLK and transmitted as a serial stream with TD0 sent as the first bit. 62 61 PECL O Differential output transmit. TXP and TXN are differential serial outputs that interface to a copper or an optical I/F module. TXP and TXN are put in a high-impedance state when LOOPEN is high and are active when LOOPEN is low. ENABLE 28 I P/U (3) When this terminal is low, the device is disabled for Iddq testing. RD0–RD9, RBCn, TXP, and TXN are high impedance. The pullup and pulldown resistors on any input are disabled. When ENABLE is high, the device operates normally. JTDI 48 I P/U (3) Test data input. IEEE1149.1 (JTAG) JTDO 27 O Test data output. IEEE1149.1 (JTAG) JTMS 55 I P/U (3) Test mode select. IEEE1149.1 (JTAG) JTRSTN 56 I P/U (3) Reset signal. IEEE1149.1 (JTAG) LOOPEN 19 I P/D (4) Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test capability in conjunction with the protocol device. The TXP and TXN outputs are held in a high-impedance state during the loop-back test. LOOPEN is held low during standard operational state with external serial outputs and inputs active. PRBSEN 16 I P/D (4) PRBS enable. When PRBSEN is high, the PRBS generation circuitry is enabled. The PRBS verification circuit in the receive side is also enabled. A PRBS signal can be fed to the receive inputs and checked for errors, that are reported by the SYNC/PASS terminal indicating low. TCK 49 I TESTEN 17 I P/D (4) NAME RD0–RD9 TD0–TD9 TXP TXN NO. TEST (2) (3) (4) 4 P/U = Internal pullup P/U = Internal pullup P/D = Internal pulldown Test clock. IEEE1149.1 (JTAG) Manufacturing test terminal TLK1201ARCP, TLK1201AIRCP ETHERNET TRANSCEIVERS www.ti.com SLLS580A – FEBRUARY 2004 – REVISED JUNE 2004 Terminal Functions (continued) TERMINAL NAME I/O NO. DESCRIPTION POWER VDD 5, 10, 20, 23, 29, 37, 42, 50, 63 Supply Digital logic power. Provides power for all digital circuitry and digital I/O buffers. VDDA 53, 57, 59, 60 Supply Analog power. VDDA provides power for the high-speed analog circuits, receiver, and transmitter 18 Supply PLL power. Provides power for the PLL circuitry. This terminal requires additional filtering. GND 1, 14, 21,25, 33, 46 Ground Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers. GNDA 51, 58 Ground Analog ground. GNDA provides a ground for the high-speed analog circuits RX and TX. 64 Ground PLL ground. Provides a ground for the PLL circuitry. VDDPLL GROUND GNDPLL DETAILED DESCRIPTION Data Transmission This device supports both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing DDR clocking. When MODESEL is low, the TBI mode is selected. When MODESEL is high, the DDR mode is selected. In the TBI mode, the transmitter portion registers incoming 10-bit wide data words (8b/10b encoded data, TD0–TD9) on the rising edge of REFCLK. The REFCLK is also used by the serializer, which multiplies the clock by a factor of 10, providing a signal that is fed to the shift register. The 8b/10b encoded data is transmitted sequentially bits 0 through 9 over the differential high-speed I/O channel. In the DDR mode, the transmitter accepts 5-bit wide 8b/10b encoded data on pins TD0–TD4. In this mode, data is aligned to both the rising and falling edges of REFCLK. The data is then formed into a 10-bit wide word and sent to the serializer. The rising edge REFCLK clocks in bits 0–4, and the falling edge of REFCLK clocks in bits 5–9. Bit 0 is the first bit transmitted. Transmission Latency Data transmission latency is defined as the delay from the initial 10-bit word load to the serial transmission of bit 9. The minimum latency in TBI mode is 19 bit times. The maximum latency in TBI mode is 20 bit times. The minimum latency in DDR mode is 29 bit times, and maximum latency in DDR mode is 30 bit times. Measured 10-Bits TXP, TXN Next 10-Bit Code b7 b8 b9 b0 b1 b2 b3 td(Tx latency) TD(0−9) 10-Bit Code REFCLK Figure 1. Transmitter Latency Full Rate Mode 5 TLK1201ARCP, TLK1201AIRCP ETHERNET TRANSCEIVERS www.ti.com SLLS580A – FEBRUARY 2004 – REVISED JUNE 2004 DETAILED DESCRIPTION (continued) Data Reception The receiver portion deserializes the differential serial data. The serial data is retimed based on an interpolated clock generated from the reference clock. The serial data is then aligned to the 10-bit word boundaries and presented to the protocol controller along with receive byte clocks (RBC0 and RBC1). Receiver Clock Select Mode There are two modes of operation for the parallel bus: 1) the 10-bit (TBI) mode and 2) 5-bit (DDR) mode. When in TBI mode, there are two user-selectable clock modes that are controlled by the RBCMODE terminal: 1) full-rate clock on RBC0 and 2) half-rate clocks on RBC0 and RBC1. When in the DDR mode, only a full-rate clock is available on RBC0; see Table 1. Table 1. Mode Selection RECEIVE BYTE CLOCK MODESEL RBCMODE MODE 0 0 TBI half-rate 30–65 MHz 30–65 MHz 0 1 TBI full-rate 60–130 MHz 60–130 MHz 1 0 DDR 60–130 MHz 60–130 MHz 1 1 DDR 60–130 MHz 60–130 MHz TLK1201A TLK1201AI In the half-rate mode, two receive byte clocks (RBC0 and RBC1) are 180 degrees out of phase and operate at one-half the data rate. The clocks are generated by dividing down the recovered clock. The received data is output with respect to the two receive byte clocks (RBC0 and RBC1) allowing a protocol device to clock the parallel bytes using the RBC0 and RBC1 rising edges. The outputs to the protocol device, byte 0 of the received data is valid on the rising edge of RBC1. See the timing diagram shown in Figure 2. td(S) RBC0 td(S) RBC1 td(H) SYNC td(H) RD(0-9) K28.5 DXX.X DXX.X DXX.X K28.5 DXX.X Figure 2. Synchronous Timing Characteristics Waveforms (TBI Half-Rate Mode) In the normal-rate mode, only RBC0 is used and operates at full data rate (that is, 1.25-Gbps data rate produces a 125-MHz clock). The received data is output with respect to the rising edge of RBC0. RBC1 is low in this mode. See the timing diagram shown in Figure 3. RBC0 td(S) td(H) SYNC RD(0-9) K28.5 DXX.X DXX.X DXX.X K28.5 DXX.X Figure 3. Synchronous Timing Characteristics Waveforms (TBI Full-Rate Mode) 6 TLK1201ARCP, TLK1201AIRCP ETHERNET TRANSCEIVERS www.ti.com SLLS580A – FEBRUARY 2004 – REVISED JUNE 2004 In the double data rate mode, the receiver presents the data on both the rising and falling edges of RBC0. RBC1 is low impedance. The data is clocked bit 0 first, and aligned to the rising edge of RBC0. See the timing diagram shown in Figure 4. td(S) RBC0 td(S) td(H) td(H) SYNC RD(0-4) K28.5 K28.5 DXX.X DXX.X DXX.X DXX.X DXX.X DXX.X K28.5 K28.5 DXX.X Bits 0-4 Bits 5-9 Figure 4. Synchronous Timing Characteristics Waveforms (DDR Mode) The receiver clock interpolator can lock to the incoming data without the need for a lock-to-reference preset. The received serial data rate (RXP and RXN) is at the same baud rate as the transmitted data stream, ±0.02% (200 PPM) for proper operation (see the recommended operating tables). Receiver Word Alignment This device uses the IEEE 802.3 gigabit ethernet defined 10-bit K28.5 character (comma character) word alignment scheme. The following sections explain how this scheme works and how it realigns itself. Comma Character on Expected Boundary This device provides 10-bit K28.5 character recognition and word alignment. The 10-bit word alignment is enabled by forcing the SYNCEN terminal high. This enables the function that examines and compares serial input data to the 7-bit synchronization pattern. The K28.5 character is defined by 8-bit/10-bit coding scheme as a pattern consisting of 0011111010 (a negative number beginning with disparity) with the 7 MSBs (0011111), referred to as the comma character. The K28.5 character was implemented specifically for aligning data words. As long as the K28.5 character falls within the expected 10-bit boundary, the received 10-bit data is properly aligned and data realignment is not required. Figure 2 shows the timing characteristics of RBC0, RBC1, SYNC, and RD0–RD9 while synchronized. (Note: the K28.5 character is valid on the rising edge of RBC1.) Comma Character Not on Expected Boundary If synchronization is enabled and a K28.5 character straddles the expected 10-bit word boundary, then word realignment is necessary. Realignment or shifting the 10-bit word boundary truncates the character following the misaligned K28.5, but the following K28.5 and all subsequent data is aligned properly as shown in Figure 5. The RBC0 and RBC1 pulse widths are stretched or stalled in their current state during realignment. With this design, the maximum stretch that occurs is 20 bit times. This occurs during a worst case scenario when the K28.5 is aligned to the falling edge of RBC1 instead of the rising edge. Figure 5 shows the timing characteristics of the data realignment. 7 TLK1201ARCP, TLK1201AIRCP ETHERNET TRANSCEIVERS www.ti.com SLLS580A – FEBRUARY 2004 – REVISED JUNE 2004 31 Bit Times Max Receive Path Latency INPUT DATA K28.5 DXX.X 30 Bit Times (Max) K28.5 DXX.X DXX.X DXX.X DXX.X K28.5 RBC0 RBC1 Worst Case Misaligned K28.5 RD(0-9) DXX.X DXX.X Corrupt Data K28.5 DXX.X DXX.X Misalignment Corrected K28.5 DXX.X DXX.X DXX.X K28.5 SYNC Figure 5. Word Realignment Timing Characteristics Waveforms Systems that do not require framed data may disable byte alignment by tying SYNCEN low. When a SYNC character is detected, the SYNC signal is brought high and is aligned with the K28.5 character. The duration of the SYNC pulse is equal to the duration of the data when in TBI mode. When in DDR mode the SYNC pulse is present for the entire RBC0 period. Data Reception Latency The serial-to-parallel data latency is the time from when the first bit arrives at the receiver until it is output in the aligned parallel word with RD0 received as first bit. The minimum latency in TBI mode is 21 bit times, and the maximum latency is 31 bit times. The minimum latency in DDR mode is 27 bit times and maximum latency is 34 bit times. 10-Bit Code RXP, RXN b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 td(Rx latency) RD(0−9) 10-Bit Code RBC0 Figure 6. Receiver Latency - TBI Normal Mode Shown Loss of Signal Detection This device has a loss-of-signal (LOS) detection circuit for conditions where the incoming signal no longer has sufficient voltage level to keep the clock recovery circuit in lock. The LOS is intended to be an indication of gross signal error conditions, such as a detached cable or no signal being transmitted, and not an indication of signal coding health. Under a PRBS serial input pattern, LOS is high for signal amplitudes greater than 150 mV. The LOS is low for all amplitudes below 50 mV. Between 50 mV and 150 mV, LOS is undetermined. 8 TLK1201ARCP, TLK1201AIRCP ETHERNET TRANSCEIVERS www.ti.com SLLS580A – FEBRUARY 2004 – REVISED JUNE 2004 Testability The loopback function provides for at-speed testing of the transmit/receive portions of the circuitry. The enable function allows for all circuitry to be disabled so that an Iddq test can be performed. The PRBS function also allows for a BIST (built-in self test). The terminal setting, TESTEN high, enables the test mode. The terminal TESTEN has an internal pulldown resistor, so it defaults to normal operation. The TESTEN is only used for factory testing, and is not intended for end-user control. Loopback Testing The transceiver can provide a self-test function by enabling (setting LOOPEN to high level) the internal loopback path. Enabling this function causes serial transmitted data to be routed internally to the receiver. The parallel data output can be compared to the parallel input data for functional verification. The external differential output is held in a high-impedance state during the loopback testing. Enable Function When held low, ENABLE disables all quiescent power in both the analog and digital circuitry. This allows an ultralow-power idle state when the link is not active. PRBS Function This device has a built-in 27–1 PRBS function. When the PRBSEN control bit is set high, the PRBS test is enabled. A PRBS is generated and fed into the 10-bit parallel transmitter input bus. Data from the normal parallel input source is ignored during PRBS test mode. The PRBS pattern is then fed through the transmit circuitry as if it were normal data and sent out to the transmitter. The output can be sent to a bit error rate tester (BERT) or to the receiver of another TLK1201AI. Since the PRBS is not really random and is really a predetermined sequence of 1s and 0s, the data can be captured and checked for errors by a BERT. This device also has a built-in BERT function on the receiver side that is enabled by PRBSEN. It can receive a PRBS pattern and check for errors, and then reports the errors by forcing the SYNC/PASS terminal low. The PRBS testing supports two modes (normal and latched), which are controlled by the SYNCEN input. When SYNCEN is low, the result of the PRBS bit error rate test is passed to the SYNC/PASS terminal. When SYNCEN is high the result of the PRBS verification is latched on the SYNC/PASS output (that is, a single failure forces SYNC/PASS to remain low). ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) TLK1201A/TLK1201AI Supply voltage, VDD (see (2)) –0.3 V to 3 V Input voltage range at TTL terminals, VI –0.5 V to 4 V Input voltage range at any other terminal –0.3 V to VDD +0.3 V Storage temperature, Tstg –65°C to 150°C Electrostatic discharge Characterized free-air operating temperature range (1) (2) CDM: 1 kV, HBM:2 kV TLK1201A 0°C to 70°C TLK1201AI –40°C to 85°C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. 9 TLK1201ARCP, TLK1201AIRCP ETHERNET TRANSCEIVERS www.ti.com SLLS580A – FEBRUARY 2004 – REVISED JUNE 2004 DISSIPATION RATING TABLE (1) (2) (3) (4) PACKAGE TA≤ 25°C POWER RATING OPERATING FACTOR (1) ABOVE TA = 25°C TA = 70°C POWER RATING RCP64 (2) 5.25 W 46.58 mW/°C 2.89 W RCP64 (3) 3.17 W 23.70 mW/°C 1.74 W RCP64 (4) 2.01 W 13.19 mW/°C 1.11 W This is the inverse of the traditional junction-to-ambient thermal resistance (RΘJA). 2 oz. Trace and copper pad with solder 2 oz. Trace and copper pad without solder Standard JEDEC high-K board Thermal Characteristics PARAMETER TEST CONDITION MIN TYP Board-mounted, no air flow, high conductivity TI recommended test board, chip soldered or greased to thermal land RΘJA Junction-to-free-air thermal resistance Junction-to-case-thermal resistance UNIT 21.47 °C/W Board-mounted, no air flow, high conductivity TI recommended test board with thermal land but no solder or grease thermal connection to thermal land 42.2 Board-mounted, no air flow, JEDEC test board RΘJC MAX 75.83 Board-mounted, no air flow, high conductivity TI recommended test board, chip soldered or greased to thermal land 0.38 Board-mounted, no air flow, high conductivity TI recommended test board with thermal land but no solder or grease thermal connection to thermal land 0.38 °C/W Board-mounted, no air flow, JEDEC test board 7.8 RECOMMENDED OPERATING CONDITIONS Supply voltage, VDD, VDD(A) Total supply current, IDD, IDD(A) Total power dissipation, PD MAX 2.3 2.5 2.7 V 90 mA Frequency = 1.25 Gbps, PRBS pattern 250 Frequency = 1.25 Gbps, worst case (1) Enable = 0, VDD(A), VDD = 2.7 V Startup lock time, PLL VDD, VDD(A) = 2.5 V, EN↑ to PLL acquire (1) NOM Frequency = 1.25 Gbps, PRBS pattern Total shutdown current, IDD, IDD(A) Operating free-air temperature, TA MIN UNIT mW 245 mW 50 µA 500 µs TLK1201A 0 70 TLK1201AI -40 85 °C The worst case pattern is a pattern that creates a maximum transition density on the serial transceiver. REFERENCE CLOCK (REFCLK) TIMING REQUIREMENTS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS Frequency Minimum data rate Frequency Maximum data rate MIN TYP MAX TLK1201A TYP–0.01% 60 TYP+0.01% TLK1201AI TYP–0.01% 60 TYP+0.01% TYP–0.01% 130 TYP+0.01% 50% 60% Accuracy 100 Duty cycle 40% Jitter 10 Random plus deterministic 100 40 UNIT MHz ppm ps TLK1201ARCP, TLK1201AIRCP ETHERNET TRANSCEIVERS www.ti.com SLLS580A – FEBRUARY 2004 – REVISED JUNE 2004 TTL ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VOH High-level output voltage IOH= –400 µA VOL Low-level output voltage IOL= 1 mA VIH High-level input voltage VIL Low-level input voltage IIH High-level Input current VDD= 2.3 V, VIN = 2 V IIL Low-level Input current VDD= 2.3 V, VIN = 0.4 V CIN Input capacitance MIN TYP VDD–0.2 2.3 GND 0.25 1.7 MAX UNIT V 0.5 V 3.6 V 0.8 V 40 µA –40 µA 4 pF 11 TLK1201ARCP, TLK1201AIRCP ETHERNET TRANSCEIVERS www.ti.com SLLS580A – FEBRUARY 2004 – REVISED JUNE 2004 TRANSMITTER/RECEIVER CHARACTERISTICS PARAMETER TEST CONDITIONS VOD = |TxD-TxN| V(cm) MAX 600 850 1100 800 1050 1200 1100 1250 1400 mV 1600 mV 2250 mV 350 µA 2 pF Differential output jitter, Random + deterministic, PRBS pattern, Rω = 125 MHz 0.24 UI Differential output jitter, Random + deterministic, PRBS pattern, Rω = 106.25 MHz 0.2 UI 0.10 UI 250 ps Rt = 75 Ω 200 Receiver common mode voltage range, (RxP + RxN)/2 1000 Ilkg(R) Receiver input leakage current -350 CI Receiver input capacitance Serial data total jitter (peak-to-peak) UNIT (1) Rt = 75 Ω Receiver input voltage requirement, VID = |RxP - RxN| t(TJ) TYP Rt = 50Ω Rt = 50Ω Transmit common mode voltage range MIN 1250 mV t(DJ) Serial data deterministic jitter (peak-to-peak) Differential output jitter, PRBS pattern, Rω = 125 MHz tr, tf Differential signal rise, fall time (20% to 80%) RL = 50 Ω, CL = 5 pF, See NoLabel and NoLabel 100 Differential input jitter, Random + deterministic, Rω = 125 MHz 0.25 UI 0.3 UI Serial data jitter tolerance minimum required eye opening, (per IEEE-802.3 specification) Differential input jitter, random + determinisitc, PRBS pattern at zero crossing Receiver data acquisition lock time from powerup 500 Data relock time from loss of synchronization td(Txlatency) Tx latency TBI modes 1024 Bit times See Figure 1 DDR mode TBI modes See Figure 6 DDR mode td(Rxlatency) (1) Rx latency 19 20 29 30 20 31 27 34 TBI mode 600–620 Mbps 24 28 DDR mode 600–620 Mbps 27 31 TBI mode 1228.8 Mbps 25 29 DDR mode 1228.8 Mbps 27 33 UI = serial bit time 80% 50% 20% TX+ 80% 50% 20% TX− tf ∼V ∼V ∼V tr ∼ 1V 80% VOD ∼V tf tr 20% 0V ∼ −1V Figure 7. Differential and Common-Mode Output Voltage Definitions 12 µs UI UI TLK1201ARCP, TLK1201AIRCP ETHERNET TRANSCEIVERS www.ti.com SLLS580A – FEBRUARY 2004 – REVISED JUNE 2004 CL 5 pF 50 Ω 50 Ω CL 5 pF Figure 8. Transmitter Test Setup LVTTL OUTPUT SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX Clock rise time tf(RBC) Clock fall time tr Data rise time tf Data fall time tsu(D1) Data setup time (RD0–RD9), Data valid prior to RBC0 rising TBI normal mode, (see Figure 3) 2.5 ns th(D1) Data hold time (RD0–RD9), Data valid after RBC0 rising TBI normal mode, (see Figure 3) 2 ns tsu(D2) Data setup time (RD0–RD4) DDR mode, Rω = 125 MHz, (see Figure 4) 2 ns th(D2) Data hold time (RD0–RD4) DDR mode, Rω = 125 MHz, (see Figure 4) 0.8 ns tsu(D3) Data setup time (RD0–RD9) TBI half-rate mode, Rω = 125 MHz, (see Figure 2) 2.5 ns th(D3) Data hold time (RD0–RD9) TBI half-rate mode, Rω = 125 MHz, (see Figure 2) 1.5 ns 80% to 20% output voltage, C = 5 pF (see Figure 9) 0.3 1.5 0.3 1.5 0.3 1.5 0.3 1.5 UNIT tr(RBC) ns ns 1.4 V CLOCK tf tr 80% 50% 20% DATA 2V 0.8 V tf tr Figure 9. TTL Data I/O Valid Levels for AC Measurement TRANSMITTER TIMING REQUIREMENTS over recommended operating conditions (unless otherwise noted) PARAMETER tsu(D4) Data setup time (TD0–TD9) th(D4) Data hold time (TD0–TD9) tsu(D5) Data setup time (TD0–TD9) th(D5) Data hold time (TD0–TD9) tr, tf TD[0,9] data rise and fall time TEST CONDITIONS TBI modes DDR modes See Figure 9 MIN TYP MAX 1.6 UNIT ns 0.8 0.7 ns 0.5 2 ns 13 TLK1201ARCP, TLK1201AIRCP ETHERNET TRANSCEIVERS www.ti.com SLLS580A – FEBRUARY 2004 – REVISED JUNE 2004 APPLICATION INFORMATION 8B/10B TRANSMISSION CODE The PCS maps GMII signals into 10-bit code groups and vice versa, using an 8b/10b block coding scheme. The PCS uses the transmission code to improve the transmission characteristics of information to be transferred across the link. The encoding defined by the transmission code ensures that sufficient transitions are present in the PHY bit stream to make clock recovery possible in the receiver. Such encoding also greatly increases the likelihood of detecting any single or multiple bit errors that may occur during transmission and reception of information. The 8b/10b transmission code specified for use has a high-transition density, is run length limited, and is dc-balanced. The transition density of the 8b/10b symbols range from 3 to 8 transitions per symbol. The definition of the 8b/10b transmission code is specified in IEEE 802.3 gigabit ethernet and ANSI X3.230-1994 (FC-PH), clause 11. The 8b/10b transmission code uses letter notation describing the bits of an unencoded information octet. The bit notation of A,B,C,D,E,F,G,H for an unencoded information octet is used in the description of the 8b/10b transmission code-groups, where A is the LSB. Each valid code group has been given a name using the following convention: /Dx.y/ for the 256 valid data code-groups and /Kx.y/ for the special control code-groups, where y is the decimal value of bits EDCBA and x is the decimal value of bits HGF (noted as K<HGF.EDCBA>). Thus, an octet value of FE representing a code-group value of K30.7 would be represented in bit notation as 111 11110. VDD TXP ZO 5 kΩ RXP 7.5 kΩ ZO GND + _ VDD ZO 5 kΩ ZO TXN RXN 7.5 kΩ GND Transmitter Media Receiver Figure 10. High-Speed I/O Directly-Coupled Mode 14 TLK1201ARCP, TLK1201AIRCP ETHERNET TRANSCEIVERS www.ti.com SLLS580A – FEBRUARY 2004 – REVISED JUNE 2004 APPLICATION INFORMATION (continued) VDD TXP ZO 5 kΩ RXP 7.5 kΩ ZO GND + _ VDD ZO 5 kΩ TXN ZO RXN 7.5 kΩ GND Transmitter Media Receiver Figure 11. High-Speed I/O AC-Coupled Mode 15 TLK1201ARCP, TLK1201AIRCP ETHERNET TRANSCEIVERS www.ti.com SLLS580A – FEBRUARY 2004 – REVISED JUNE 2004 APPLICATION INFORMATION (continued) 5 Ω at 100 MHz 2.5 V 2.5 V 18 VDD VDDA GND 0.01 µF VDDPLL GNDPLL 64 GNDA TLK1201AI TLK1201AII 17 TESTEN 10 TD0-TD9 22 16 TXP 62 Controlled Impedance Transmission Line 61 Controlled Impedance Transmission Line 54 Controlled Impedance Transmission Line REFCLK PRBSEN 19 LOOPEN 24 Host Protocol Device 47 10 SYNCEN TXN SYNC/PASS RD0-RD9 2 RBC0-RBC1 28 26 ENABLE RXP LOS 32 Rt 50 Ω Rt 50 Ω RBCMODE 15 MODESEL 49 55 48 JTAG Controller 56 27 TCK JTMS RXN 52 Controlled Impedance Transmission Line JTDI JTRSTN JTDO Figure 12. Typical Application Circuit (AC mode) DESIGNING WITH PowerPAD The TLK1201A/TLK1201AI is housed in a high-performance, thermally enhanced, 64-pin VQFP (RCP64) PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. Therefore, if not implementing PowerPAD PCB features, the use of solder masks (or other assembly techniques) may be required to prevent any inadvertent shorting by the exposed PowerPAD of connection etches or vias under the package. It is strongly recommended that the PowerPAD be soldered to the thermal land. The recommended convention, however, is to not run any etches or signal vias under the device, but to have only a grounded thermal land as explained below. Although the actual size of the exposed die pad may vary, the minimum size required for the keepout area for the 64-pin PFP PowerPAD package is 8 mm × 8 mm. It is recommended that there be a thermal land, which is an area of solder-tinned-copper, underneath the PowerPAD package. The thermal land varies in size depending on the PowerPAD package being used, the PCB construction, and the amount of heat that needs to be removed. In addition, the thermal land may or may not contain numerous thermal vias depending on PCB construction. 16 TLK1201ARCP, TLK1201AIRCP ETHERNET TRANSCEIVERS www.ti.com SLLS580A – FEBRUARY 2004 – REVISED JUNE 2004 APPLICATION INFORMATION (continued) Other requirements for thermal lands and thermal vias are detailed in the TI application note PowerPAD Thermally Enhanced Package Application Report, TI literature number SLMA002, available via the TI Web pages beginning at URL: http://www.ti.com. Figure 13. Example of a Thermal Land For the TLK1201AI, this thermal land must be grounded to the low-impedance ground plane of the device. This improves not only thermal performance but also the electrical grounding of the device. It is also recommended that the device ground terminal landing pads be connected directly to the grounded thermal land. The land size must be as large as possible without shorting device signal terminals. The thermal land may be soldered to the exposed PowerPAD using standard reflow soldering techniques. While the thermal land may be electrically floated and configured to remove heat to an external heat sink, it is recommended that the thermal land be connected to the low-impedance ground plane for the device. More information may be obtained from the TI application note PHY Layout, TI literature number SLLA020. 17 TLK1201ARCP, TLK1201AIRCP ETHERNET TRANSCEIVERS www.ti.com SLLS580A – FEBRUARY 2004 – REVISED JUNE 2004 MECHANICAL DATA RCP (S-PQFP-G84) PowerPAD™ PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 Thermal Pad (See Note D) 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,15 0,05 0,85 0,75 0° - 7° 0,75 0,45 Seating Plane 1,00 MAX 0,08 4147711/A 10/98 A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MS-026 #IMPLIED. Dummy target for KhKIz262casm #IMPLIED. Dummy target for BhKIz1f4casm 18 PACKAGE OPTION ADDENDUM www.ti.com 4-Feb-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) TLK1201AIRCP ACTIVE HVQFP RCP 64 160 None CU NIPDAU Level-3-235C-168 HR TLK1201AIRCPR ACTIVE HVQFP RCP 64 1000 None CU NIPDAU Level-3-235C-168 HR TLK1201ARCP ACTIVE HVQFP RCP 64 160 None CU NIPDAU Level-3-235C-168 HR TLK1201ARCPR ACTIVE HVQFP RCP 64 1000 None CU NIPDAU Level-3-235C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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