CYWUSB6932 CYWUSB6934 WirelessUSB™ LS 2.4 GHz DSSS Radio SoC WirelessUSB™ LS 2.4 GHz DSSS Radio SoC Features ■ Low standby current < 1 µA ■ Integrated 30-bit Manufacturing ID ■ Operating voltage from 2.7 V to 3.6 V ■ 2.4-GHz radio transceiver ■ Operates in the unlicensed Industrial, Scientific, and Medical (ISM) band (2.4 GHz to 2.483 GHz) ■ Operating temperature from 0 °C to 70 °C ■ Receive sensitivity: –90 dBm ■ Offered in a small footprint 48 quad flat pack no leads (QFN) ■ Up to 0 dBm output power Functional Description ■ Range of up to 10 meters or more ■ Data throughput of up to 62.5 kbits/sec ■ Highly integrated low cost, minimal number of external components required ■ Dual direct sequence spread spectrum (DSSS reconfigurable baseband correlators ■ SPI microcontroller interface (up to 2-MHz data rate) ■ 13-MHz ± 50-ppm input clock operation D es ig ns The CYWUSB6932[1]/CYWUSB6934 Integrated Circuits (ICs) are highly integrated 2.4-GHz DSSS radio system-on-chip (SoC) ICs. From the serial peripheral interface (SPI) to the antenna, these ICs are single-chip 2.4-GHz DSSS Gaussian Frequency Shift Keying (GFSK) baseband modems that connect directly to a microcontroller via simple serial interface. fo rN ew The CYWUSB6932 transmit-only IC and the CYWUSB6934 transceiver IC are available in a small footprint 48-pin QFN package. ed Logic Block Diagram – CYWUSB6932/CYWUSB6934 en d DIOVAL DIO SERDES B DSSS Baseband B m R Digital ot RESET PD DSSS Baseband A N SS SCK MISO MOSI SERDES A ec om IRQ GFSK Modulator RFOUT GFSK Demodulator RFIN Synthesizer X13IN X13 X13OUT CY WUSB6934Only Note 1. CYWUSB6932 is now obsolete and is no longer supported. Cypress Semiconductor Corporation Document Number: 38-16007 Rev. *M • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 25, 2013 CYWUSB6932 CYWUSB6934 Contents D es ig ns DC Characteristics ......................................................... 28 AC Characteristics[16] ..................................................... 29 Radio Parameters ..................................................... 31 Power Management Timing ...................................... 32 Ordering Information ...................................................... 35 Ordering Code Definitions ......................................... 35 Package Diagram ............................................................ 36 Acronyms ........................................................................ 37 Document Conventions ................................................. 37 Units of Measure ....................................................... 37 Document History Page ................................................. 38 Sales, Solutions, and Legal Information ...................... 39 Worldwide Sales and Design Support ....................... 39 Products .................................................................... 39 PSoC® Solutions ...................................................... 39 Cypress Developer Community ................................. 39 Technical Support ..................................................... 39 N ot R ec om m en d ed fo rN ew Applications ...................................................................... 3 Applications Support ................................................... 3 Functional Overview ........................................................ 3 2.4-GHz Radio ............................................................. 3 GFSK Modem .............................................................. 3 Dual DSSS Baseband ................................................. 3 Serializer/Deserializer (SERDES) ............................... 4 Application Interfaces .................................................. 4 Clocking and Power Management .............................. 4 Receive Signal Strength Indicator (RSSI) ................... 4 Application Interfaces ...................................................... 4 SPI Interface ................................................................ 4 DIO Interface ............................................................... 6 Interrupts ..................................................................... 6 Application Examples ...................................................... 7 Register Descriptions ...................................................... 9 Pin Definitions ................................................................ 26 Absolute Maximum Ratings .......................................... 28 Operating Conditions ..................................................... 28 Document Number: 38-16007 Rev. *M Page 2 of 39 CYWUSB6932 CYWUSB6934 Applications 2.4-GHz Radio ■ PC human interface devices (HIDs) ❐ Mice ❐ Keyboards ❐ Joysticks ■ Peripheral gaming devices ❐ Game controllers ❐ Console keyboards ■ General ❐ Presenter tools ❐ Remote controls ❐ Consumer electronics ❐ Barcode scanners ❐ POS peripherals ❐ Toys The receiver and transmitter are a single-conversion low-Intermediate Frequency (low-IF) architecture with fully integrated IF channel matched filters to achieve high performance in the presence of interference. An integrated Power Amplifier (PA) provides an output power control range of 30 dB in seven steps. Table 1. Internal PA Output Power Step Table Typical Output Power (dBm) 7 0 6 –2.4 5 –5.6 4 –9.7 –16.4 2 –20.8 The CYWUSB6932/CYWUSB6934 ICs are supported by the CY3632 WirelessUSB Development Kit. The development kit provides all of the materials and documents needed to cut the cord on wired applications such as: 1. Two radio modules that connect directly to two prototyping platform boards 2. Comprehensive WirelessUSB protocol code examples 3. A WirelessUSB Listener tool 4. All of the associated schematics, gerber files, and bill of materials. 1 –24.8 0 –29.0 ew D Applications Support es ig 3 ns PA Setting en d ed fo rN Both the receiver and transmitter integrated Voltage Controlled Oscillator (VCO) and synthesizer have the agility to cover the complete 2.4-GHz GFSK radio transmitter ISM band. The synthesizer provides the frequency-hopping local oscillator for the transmitter and receiver. The VCO loop filter is also integrated on-chip. ec om m The CY4632 WirelessUSB LS keyboard mouse reference design provides a production-worthy example of a wireless mouse and keyboard system. ot Functional Overview R The CY3633 WirelessUSB LS gaming development kit provides support for designing a wireless gamepad for the major gaming consoles and is offered as an accessory to the CY3632 WirelessUSB development kit. N The CYWUSB6932/CYWUSB6934 ICs provide a complete WirelessUSB LS SPI to antenna radio modem. The SoC is designed to implement wireless devices operating in the worldwide 2.4-GHz ISM frequency band (2.400 GHz to 2.4835 GHz). It is intended for systems compliant with world-wide regulations covered by ETSI EN 301 489-1 V1.4.1, ETSI EN 300 328-1 V1.3.1 (European countries); FCC CFR 47 Part 15 (USA and Industry Canada) and ARIB STD-T66 (Japan). The CYWUSB6934 IC contains a 2.4-GHz radio transceiver, a GFSK modem and a dual DSSS reconfigurable baseband. The CYWUSB6932 IC contains a 2.4-GHz radio transmit-only, a GFSK modem and a DSSS baseband. The radio and baseband are both code- and frequency-agile. Forty-nine spreading codes selected for optimal performance (Gold codes) are supported across 78 1-MHz channels yielding a theoretical spectral capacity of 3822 channels. Both ICs support a range of up to 10 meters or more. GFSK Modem The transmitter uses a DSP-based vector modulator to convert the 1-MHz chips to an accurate GFSK carrier. The receiver uses a fully integrated Frequency Modulator (FM) detector with automatic data slicer to demodulate the GFSK signal. Dual DSSS Baseband Data is converted to DSSS chips by a digital spreader. De-spreading is performed by an oversampled correlator. The DSSS baseband cancels spurious noise and assembles properly correlated data bytes. The DSSS baseband has three operating modes: 64 chips/bit Single Channel, 32 chips/bit Single Channel, and 32 chips/bit Single Channel Dual Data Rate (DDR). 64 Chips/Bit Single Channel The baseband supports a single data stream operating at 15.625 kbits/sec. The advantage of selecting this mode is its ability to tolerate a noisy environment. This is because the 15.625 kbits/sec data stream utilizes the longest PN Code resulting in the highest probability for recovering packets over the air. This mode can also be selected for systems requiring data transmissions over longer ranges. 32 Chips/Bit Single Channel The baseband supports a single data stream operating at 31.25 kbits/sec. Document Number: 38-16007 Rev. *M Page 3 of 39 CYWUSB6932 CYWUSB6934 Application Interfaces Both ICs have a fully synchronous SPI slave interface for connectivity to the application MCU. Configuration and byte-oriented data transfer can be performed over this interface. An interrupt is provided to trigger real time events. An optional SERDES Bypass mode (DIO) is provided for applications that require a synchronous serial bit-oriented data path. This interface is for data only. m en d A 13-MHz crystal (±50 ppm or better) is directly connected to X13IN and X13 without the need for external capacitors. Both ICs have a programmable trim capability for adjusting the on-chip load capacitance supplied to the crystal. ec om Below are the requirements for the crystal to be directly connected to X13IN and X13: Nominal frequency: 13 MHz ■ Operating mode: Fundamental mode ■ Resonance mode: Parallel resonant ot R ■ Frequency stability: 50 ppm ■ Series resistance: 100 ohms ■ Load capacitance: 10 pF ■ Drive level: 10 µW to 100 µW N ■ The Radio Frequency (RF) circuitry has on-chip decoupling capacitors. Both devices are powered from a 2.7 V to 3.6 V DC supply. Both devices can be shutdown to a fully static state using the PD pin. Receive Signal Strength Indicator (RSSI) The RSSI register (Reg 0x22) (applies only to the CYWUSB6934 IC) returns the relative signal strength of the ON-channel signal power and can be used to: 1. Determine the connection quality 2. Determine the value of the noise floor 3. Check for a quiet channel before transmitting. The internal RSSI voltage is sampled through a 5-bit analog-to-digital converter (ADC). A state machine controls the Document Number: 38-16007 Rev. *M ns Application Interfaces SPI Interface ed Clocking and Power Management es ig After a receive byte has been received it is loaded into the SERDES data register and can be read at any time until the next byte is received, at which time the old contents of the SERDES data register will be overwritten. The CYWUSB6932 IC only has a data serializer. To check for a quiet channel before transmitting, first set up receive mode properly and read the RSSI register (Reg 0x22). If the valid bit is zero, then force the Carrier Detect register (Reg 0x2F, bit 7=1) to initiate an ADC conversion. Then, wait greater than 50 s and read the RSSI register again. Next, clear the Carrier Detect Register (Reg 0x2F, bit 7=0) and turn the receiver OFF. Measuring the noise floor of a quiet channel is inherently a 'noisy' process so, for best results, this procedure should be repeated several times (~20) to compute an average noise floor level. A RSSI register value of 0-10 indicates a channel that is relatively quiet. A RSSI register value greater than 10 indicates the channel is probably being used. A RSSI register value greater than 28 indicates the presence of a strong signal. D The CYWUSB6934 IC has a data Serializer/Deserializer (SERDES), which provides byte-level framing of transmit and receive data. Bytes for transmission are loaded into the SERDES and receive bytes are read from the SERDES via the SPI interface. The SERDES provides double buffering of transmit and receive data. While one byte is being transmitted by the radio the next byte can be written to the SERDES data register insuring there are no breaks in transmitted data. ew Serializer/Deserializer (SERDES) rN The baseband spreads bits in pairs and supports a single data stream operating at 62.5 kbits/sec. conversion process. Under normal conditions, the RSSI state machine initiates a conversion when an ON-channel carrier is detected and remains above the noise floor for over 50 s. The conversion produces a 5-bit value in the RSSI register (Reg 0x22, bits 4:0) along with a valid bit, RSSI register (Reg 0x22, bit 5). The state machine then remains in HALT mode and does not reset for a new conversion until the receive mode is toggled off and on. Once a connection has been established, the RSSI register can be read to determine the relative connection quality of the channel. A RSSI register value lower than 10 indicates that the received signal strength is low, a value greater than 28 indicates a strong signal level. fo 32 Chips/Bit Single Channel Dual Data Rate (DDR) The CYWUSB6932/CYWUSB6934 ICs have a four-wire SPI communication interface between an application MCU and one or more slave devices. The SPI interface supports single-byte and multi-byte serial transfers. The four-wire SPI communications interface consists of Master Out-Slave In (MOSI), Master In-Slave Out (MISO), Serial Clock (SCK), and Slave Select (SS). The SPI receives SCK from an application MCU on the SCK pin. Data from the application MCU is shifted in on the MOSI pin. Data to the application MCU is shifted out on the MISO pin. The active-low Slave Select (SS) pin must be asserted to initiate a SPI transfer. The application MCU can initiate a SPI data transfer via a multi-byte transaction. The first byte is the Command/Address byte, and the following bytes are the data bytes as shown in Figure 2 through Figure 3. The SS signal should not be deasserted between bytes. The SPI communications is as follows: ■ Command Direction (bit 7) = “0” Enables SPI read transaction. A “1” enables SPI write transactions. ■ Command Increment (bit 6) = “1” Enables SPI auto address increment. When set, the address field automatically increments at the end of each data byte in a burst access, otherwise the same address is accessed. ■ Six bits of address. ■ Eight bits of data. The SPI communications interface has a burst mechanism, where the command byte can be followed by as many data bytes as desired. A burst transaction is terminated by deasserting the slave select (SS = 1). For burst read transactions, the application Page 4 of 39 CYWUSB6932 CYWUSB6934 MCU must abide by the timing shown in Figure 12. The SPI communications interface single read and burst read sequences are shown in Figure 1 and Figure 2, respectively. The SPI communications interface single write and burst write sequences are shown in Figure 3 and Figure 4, respectively. Table 2. SPI Transaction Format Byte 1 Byte 1+N Bit # 7 6 [5:0] [7:0] Bit Name DIR INC Address Data Figure 1. SPI Single Read Sequence ns SCK D IR 0 IN C 0 addr A5 A4 A3 A2 A1 A0 d a ta t o m c u M IS O D5 D6 D4 D3 D2 D1 D0 rN ew D7 D cm d MOSI es ig SS en d ed fo Figure 2. SPI Burst Read Sequence SCK D IR 0 addr IN C 1 A5 A4 M IS O ec om cm d MOSI m SS A3 A2 A1 A0 d a ta to m c u D6 D5 D4 D3 D2 d a ta to m c u 1 D1 D0 D7 D6 D5 D4 D3 D2 1+N D1 D0 N ot R D7 Figure 3. SPI Single Write Sequence SCK SS cm d M O SI DIR 1 IN C 0 addr A5 A4 A3 A2 data from m cu A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 M ISO Document Number: 38-16007 Rev. *M Page 5 of 39 CYWUSB6932 CYWUSB6934 Figure 4. SPI Burst Write Sequence SCK SS cm d MOSI D IR 1 a dd r d ata fro m m cu da ta from m cu 1 1+N IN C 1 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D5 D6 D4 D3 D2 D1 D0 M IS O Wake Interrupt The DIO communications interface is an optional SERDES bypass data-only transfer interface. In receive mode, DIO and DIOVAL are valid after the falling edge of IRQ, which clocks the data as shown in Figure 5. In transmit mode, DIO and DIOVAL are sampled on the falling edge of the IRQ, which clocks the data as shown in Figure 6. The application MCU samples the DIO and DIOVAL on the rising edge of IRQ. When the PD pin is low, the oscillator is stopped. After PD is deasserted, the oscillator takes time to start, and until it has done so, it is not safe to use the SPI interface. The wake interrupt indicates that the oscillator has started, and that the device is ready to receive SPI transfers. es ig D ew rN Transmit Interrupts m en d ed The CYWUSB6932/CYWUSB6934 ICs feature three sets of interrupts: transmit, receive (CYWUSB6934 only), and a wake interrupt. These interrupts all share a single pin (IRQ), but can be independently enabled/disabled. In transmit mode, all receive interrupts are automatically disabled, and in receive mode all transmit interrupts are automatically disabled. However, the contents of the enable registers are preserved when switching between transmit and receive modes. The wake interrupt is enabled by setting bit 0 of the Wake Enable register (Reg 0x1C, bit 0=1). Whether or not a wake interrupt is pending is indicated by the state of bit 0 of the Wake Status register (Reg 0x1D, bit 0). Reading the Wake Status register (Reg 0x1D) clears the interrupt. fo Interrupts ns DIO Interface R ec om Interrupts are enabled and the status read through 6 registers: Receive Interrupt Enable (Reg 0x07), Receive Interrupt Status (Reg 0x08), Transmit Interrupt Enable (Reg 0x0D), Transmit Interrupt Status (Reg 0x0E), Wake Enable (Reg 0x1C), Wake Status (Reg 0x1D). N ot If more than 1 interrupt is enabled at any time, it is necessary to read the relevant interrupt status register to determine which event caused the IRQ pin to assert. Even when a given interrupt source is disabled, the status of the condition that would otherwise cause an interrupt can be determined by reading the appropriate interrupt status register. It is therefore possible to use the devices without making use of the IRQ pin at all. Firmware can poll the interrupt status register(s) to wait for an event, rather than using the IRQ pin. The polarity of all interrupts can be set by writing to the Configuration register (Reg 0x05), and it is possible to configure the IRQ pin to be open drain (if active low) or open source (if active high). Document Number: 38-16007 Rev. *M Four interrupts are provided to flag the occurrence of transmit events. The interrupts are enabled by writing to the Transmit Interrupt Enable register (Reg 0x0D), and their status may be determined by reading the Transmit Interrupt Status register (Reg 0x0E). If more than 1 interrupt is enabled, it is necessary to read the Transmit Interrupt Status register (Reg 0x0E) to determine which event caused the IRQ pin to assert. The function and operation of these interrupts are described in detail in Register Descriptions on page 9. Receive Interrupts Eight interrupts are provided to flag the occurrence of receive events, four each for SERDES A and B. In 64 chips/bit and 32 chips/bit DDR modes, only the SERDES A interrupts are available, and the SERDES B interrupts will never trigger, even if enabled. The interrupts are enabled by writing to the Receive Interrupt Enable register (Reg 0x07), and their status may be determined by reading the Receive Interrupt Status register (Reg 0x08). If more than one interrupt is enabled, it is necessary to read the Receive Interrupt Status register (Reg 0x08) to determine which event caused the IRQ pin to assert. The function and operation of these interrupts are described in detail in Register Descriptions on page 9. Page 6 of 39 CYWUSB6932 CYWUSB6934 Figure 5. DIO Receive Sequence IRQ DIOVAL v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v... d10 d11 d12 d13 d14 d... data to mcu DIO d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 DIOVAL v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v... d11 d12 d13 d14 d... d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 rN DIO ew data from mcu D IRQ es ig ns Figure 6. DIO Transmit Sequence fo Application Examples en d ed Figure 7. CYWUSB6932 Transmit-Only Battery-Powered Device LDO/ DC2DC 3.3 V ec om Battery - PCB Trace Inverted “F” Antenna (PIFA) RESET Application MCU IRQ N PD Buttons Vcc 10pF RFOUT ot R Vcc Optical Mouse Sensor 0.1F m + SPI WUSB LS 13MHz Crystal 4 Document Number: 38-16007 Rev. *M Page 7 of 39 CYWUSB6932 CYWUSB6934 Figure 8. CYWUSB6934 USB Bridge Transceiver PCB Trace Antenna 3.3V 0.1F 2.0 pF 5V LDO 0.1µF 4.7µF 1µF 2.0 pF 1.2 pF RESET PD RFOUT IRQ 2.2 nH WirelessUSB LS 2.2K SCK SS D+/D2 N ot R ec om m en d ed fo rN ew MISO 13MHz Crystal Cypress enCoRe USB MCU D 2.2K MOSI 1.3K ns 27 pF RFIN USB I/F Vcc es ig 3.3 nH Document Number: 38-16007 Rev. *M Page 8 of 39 CYWUSB6932 CYWUSB6934 Register Descriptions Table 3 displays the list of registers inside the CYWUSB6932/CYWUSB6934 ICs that are addressable through the SPI interface. All registers are read and writable, except where noted. Table 3. CYWUSB6932/CYWUSB6934 Register Map[2] Address Page Default Access Revision ID Register Name REG_ID Mnemonic 0x00 page 10 0x07 RO Control REG_CONTROL 0x03 page 10 0x00 RW Data Rate REG_DATA_RATE 0x04 page 11 0x00 RW Configuration REG_CONFIG 0x05 page 11 0x01 RW SERDES Control REG_SERDES_CTL 0x06 page 12 0x03 RW REG_RX_INT_EN page 13 0x00 RW Receive SERDES Interrupt Status REG_RX_INT_STAT 0x08[3] page 14 0x00 RO Receive SERDES Data A REG_RX_DATA_A 0x09[3] page 16 0x00 RO Receive SERDES Valid A REG_RX_VALID_A 0x0A[3] page 16 0x00 RO Receive SERDES Data B REG_RX_DATA_B 0x0B[3] page 16 Receive SERDES Valid B REG_RX_VALID_B 0x0C[3] es ig ns Receive SERDES Interrupt Enable 0x07[3] RO 0x00 RO D 0x00 page 17 0x0D page 17 0x00 RW Transmit SERDES Interrupt Status REG_TX_INT_STAT 0x0E page 18 0x00 RO Transmit SERDES Data REG_TX_DATA 0x0F page 19 0x00 RW Transmit SERDES Valid REG_TX_VALID 0x10 page 19 0x00 RW PN Code REG_PN_CODE 0x18–0x11 page 19 0x1E8B6A3DE0E9B2 22 RW Threshold Low REG_THRESHOLD_L 0x19[3] page 20 0x08 RW Threshold High REG_THRESHOLD_H 0x1A[3] page 20 0x38 RW en d ed fo rN ew Transmit SERDES Interrupt Enable REG_TX_INT_EN REG_WAKE_EN 0x1C page 20 0x00 RW Wake Status REG_WAKE_STAT 0x1D page 21 0x01 RO REG_ANALOG_CTL 0x20 page 21 0x04 RW REG_CHANNEL 0x21 page 22 0x00 RW ec om m Wake Enable Analog Control Channel 0x22[3] page 22 0x00 RO REG_PA 0x23 page 22 0x00 RW REG_CRYSTAL_ADJ 0x24 page 23 0x00 RW REG_VCO_CAL 0x26 page 23 0x00 RW Reg Power Control REG_PWR_CTL 0x2E 23 0x00 RW Carrier Detect REG_CARRIER_DETECT 0x2F page 24 0x00 RW Crystal Adjust VCO Calibration REG_RSSI R N PA Bias ot Receive Signal Strength Indicator Clock Manual REG_CLOCK_MANUAL 0x32 page 24 0x00 RW Clock Enable REG_CLOCK_ENABLE 0x33 page 24 0x00 RW Synthesizer Lock Count REG_SYN_LOCK_CNT 0x38 page 24 0x64 RW Manufacturing ID REG_MID 0x3C–0x3F page 25 – RO Notes 2. All registers are accessed Little Endian. 3. Register not applicable to CYWUSB6932. Document Number: 38-16007 Rev. *M Page 9 of 39 CYWUSB6932 CYWUSB6934 Table 4. Revision ID Register Addr: 0x00 7 REG_ID 6 5 4 Default: 0x07 3 2 Silicon ID Bit 1 0 Product ID Name Description 7:4 Silicon ID These are the Silicon ID revision bits. 0000 = Rev A, 0001 = Rev B, etc. These bits are read-only. 3:0 Product ID These are the Product ID revision bits. Fixed at value 0111. These bits are read-only. REG_CONTROL 5 RX Enable TX Enable PN Code Select 4 3 Bypass Internal Auto Internal Syn Lock Signal PA Disable Default: 0x00 2 1 0 Internal PA Enable Reserved Reserved D 6 Bit rN ew 7 es ig Addr: 0x03 ns Table 5. Control Name Description RX Enable The Receive Enable bit is used to place the IC in receive mode. 1 = Receive Enabled 0 = Receive Disabled 6 TX Enable The Transmit Enable bit is used to place the IC in transmit mode. 1 = Transmit Enabled 0 = Transmit Disabled 5 PN Code Select The Pseudo-Noise Code Select bit selects between the upper or lower half of the 64 chips/bit PN code. 1 = 32 Most Significant Bits of PN code are used 0 = 32 Least Significant Bits of PN code are used This bit applies only when the Code Width bit is set to 32 chips/bit PN codes (Reg 0x04, bit 2=1). 4 Bypass Internal This bit controls whether the state machine waits for the internal Syn Lock Signal before waiting for the amount Syn Lock of time specified in the Syn Lock Count register (Reg 0x38), in units of 2 s. If the internal Syn Lock Signal is Signal used then set Syn Lock Count to 25 to provide additional assurance that the synthesizer has settled. 1 = Bypass the Internal Syn Lock Signal and wait the amount of time in Syn Lock Count register (Reg 0x38) 0 = Wait for the Syn Lock Signal and then wait the amount of time specified in Syn Lock Count register (Reg 0x38) It is recommended that the application MCU sets this bit to 1 in order to guarantee a consistent settle time for the synthesizer. 3 Auto Internal PA Disable The Auto Internal PA Disable bit is used to determine the method of controlling the Internal Power Amplifier. The two options are automatic control by the baseband or by firmware through register writes. For external PA usage, please see the description of the REG_ANALOG_CTL register (Reg 0x20). 1 = Register controlled Internal PA Enable 0 = Auto controlled Internal PA Enable When this bit is set to 1, the enabled state of the Internal PA is directly controlled by bit Internal PA Enable (Reg 0x03, bit 2). It is recommended that this bit is set to 0, leaving the PA control to the baseband. 2 Internal PA Enable The Internal PA Enable bit is used to enable or disable the Internal Power Amplifier. 1 = Internal Power Amplifier Enabled 0 = Internal Power Amplifier Disabled This bit only applies when the Auto Internal PA Disable bit is selected (Reg 0x03, bit 3=1), otherwise this bit is don’t care. 1 Reserved This bit is reserved and should be written with a zero. 0 Reserved This bit is reserved and should be written with a zero. N ot R ec om m en d ed fo 7 Document Number: 38-16007 Rev. *M Page 10 of 39 CYWUSB6932 CYWUSB6934 Table 6. Data Rate Addr: 0x04 7 REG_DATA_RATE 6 5 4 Default: 0x00 3 Reserved Bit Name 2 1 0 Code Width Data Rate Sample Rate Description These bits are reserved and should be written with zeroes. The Code Width bit is used to select between 32 chips/bit and 64 chips/bit PN codes. 1 = 32 chips/bit PN codes 0 = 64 chips/bit PN codes The number of chips/bit used impacts a number of factors such as data throughput, range and robustness to interference. By choosing a 32 chips/bit PN-code, the data throughput can be doubled or even quadrupled (when double data rate is set). A 64 chips/bit PN code offers improved range over its 32 chips/bit counterpart as well as more robustness to interference. By selecting to use a 32 chips/bit PN code a number of other register bits are impacted and need to be addressed. These are PN Code Select (Reg 0x03, bit 5), Data Rate (Reg 0x04, bit 1), and Sample Rate (Reg 0x04, bit 0). 1[4] Data Rate The Data Rate bit allows the user to select Double Data Rate mode of operation which delivers a raw data rate of 62.5 kbits/sec. 1 = Double Data Rate - 2 bits per PN code (No odd bit transmissions) 0 = Normal Data Rate - 1 bit per PN code This bit is applicable only when using 32 chips/bit PN codes which can be selected by setting the Code Width bit (Reg 0x04, bit 2=1). When using Double Data Rate, the raw data throughput is 62.5 kbits/sec because every 32 chips/bit PN code is interpreted as 2 bits of data. When using this mode a single 64 chips/bit PN code is placed in the PN code register. This 64 chips/bit PN code is then split into two and used by the baseband to offer the Double Data Rate capability. When using Normal Data Rate, the raw data throughput is 32kbits/sec. Additionally, Normal Data Rate enables the user to potentially correlate data using two differing 32 chips/bit PN codes. en d ed fo rN ew D es ig ns 7:3 Reserved 2[4] Code Width 6 ot Addr: 0x05 7 N Table 7. Configuration R ec om m 0[4] Sample Rate The Sample Rate bit allows the use of the 12x sampling when using 32 chips/bit PN codes and Normal Data Rate. 1 = 12x Oversampling 0 = 6x Oversampling Using 12x oversampling improves the correlators receive sensitivity. When using 64 chips/bit PN codes or Double Data Rate this bit is don’t care. The only time when 12x oversampling can be selected is when a 32 chips/bit PN code is being used with Normal Data Rate. REG_CONFIG 5 4 Default: 0x01 3 Reserved Bit Name 7:2 Reserved 2 1 0 IRQ Pin Select Description These bits are reserved and should be written with zeroes. 1:0 IRQ Pin Select The Interrupt Request Pin Select bits are used to determine the drive method of the IRQ pin. 11 = Open Source (IRQ asserted = 1, IRQ deasserted = Hi-Z) 10 = Open Drain (IRQ asserted = 0, IRQ deasserted = Hi-Z) 01 = CMOS (IRQ asserted = 1, IRQ deasserted = 0) 00 = CMOS Inverted (IRQ asserted = 0, IRQ deasserted = 1) Note 4. The following Reg 0x04, bits 2:0 values are not valid: • 001 – Not Valid • 010 – Not Valid • 011 – Not Valid • 111 – Not Valid. Document Number: 38-16007 Rev. *M Page 11 of 39 CYWUSB6932 CYWUSB6934 Table 8. SERDES Control Addr: 0x06 7 REG_SERDES_CTL 6 5 4 Reserved Bit SERDES Enable 1 0 EOF Length Description These bits are reserved and should be written with zeroes. The SERDES Enable bit is used to switch between bit-serial mode and SERDES mode. 1 = SERDES enabled. 0 = SERDES disabled, bit-serial mode enabled. When the SERDES is enabled data can be written to and read from the IC one byte at a time, through the use of the SERDES Data registers. The bit-serial mode requires bits to be written one bit at a time through the use of the DIO/DIOVAL pins, refer to section 3.2. It is recommended that SERDES mode be used to avoid the need to manage the timing required by the bit-serial mode. D The End of Frame Length bits are used to set the number of sequential bit times for an inter-frame gap without valid data before an EOF event will be generated. When in receive mode and a valid bit has been received the EOF event can then be identified by the number of bit times that expire without correlating any new data. The EOF event causes data to be moved to the proper SERDES Data Register and can also be used to generate interrupts. If 0 is the EOF length, an EOF condition will occur at the first invalid bit after a valid reception. N ot R ec om m en d ed fo rN ew 2:0 EOF Length es ig ns 3 2 SERDES Enable Name 7:4 Reserved Default: 0x03 3 Document Number: 38-16007 Rev. *M Page 12 of 39 CYWUSB6932 CYWUSB6934 Table 9. Receive SERDES Interrupt Enable Addr: 0x07 REG_RX_INT_EN Default: 0x00 7 6 5 4 3 2 1 0 Underflow B Overflow B EOF B Full B Underflow A Overflow A EOF A Full A Bit Name Description Underflow B The Underflow B bit is used to enable the interrupt associated with an underflow condition with the Receive SERDES Data B register (Reg 0x0B) 1 = Underflow B interrupt enabled for Receive SERDES Data B 0 = Underflow B interrupt disabled for Receive SERDES Data B An underflow condition occurs when attempting to read the Receive SERDES Data B register (Reg 0x0B) when it is empty. 6 Overflow B The Overflow B bit is used to enable the interrupt associated with an overflow condition with the Receive SERDES Data B register (Reg 0x0B) 1 = Overflow B interrupt enabled for Receive SERDES Data B 0 = Overflow B interrupt disabled for Receive SERDES Data B An overflow condition occurs when new received data is written into the Receive SERDES Data B register (Reg 0x0B) before the prior data is read out. 5 EOF B The End of Frame B bit is used to enable the interrupt associated with the Channel B Receiver EOF condition. 1 = EOF B interrupt enabled for Channel B Receiver. 0 = EOF B interrupt disabled for Channel B Receiver. The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit has been detected, and then the number of invalid bits in the frame exceeds the number in the EOF length field. If 0 is the EOF length, and EOF condition will occur at the first invalid bit after a valid reception. This IRQ is cleared by reading the receive status register 4 Full B The Full B bit is used to enable the interrupt associated with the Receive SERDES Data B register (Reg 0x0B) having data placed in it. 1 = Full B interrupt enabled for Receive SERDES Data B 0 = Full B interrupt disabled for Receive SERDES Data B A Full B condition occurs when data is transferred from the Channel B Receiver into the Receive SERDES Data B register (Reg 0x0B). This could occur when a complete byte is received or when an EOF event occurs whether or not a complete byte has been received. 3 Underflow A The Underflow A bit is used to enable the interrupt associated with an underflow condition with the Receive SERDES Data A register (Reg 0x09) 1 = Underflow A interrupt enabled for Receive SERDES Data A 0 = Underflow A interrupt disabled for Receive SERDES Data A An underflow condition occurs when attempting to read the Receive SERDES Data A register (Reg 0x09) when it is empty. 2 Overflow A The Overflow A bit is used to enable the interrupt associated with an overflow condition with the Receive SERDES Data A register (0x09) 1 = Overflow A interrupt enabled for Receive SERDES Data A 0 = Overflow A interrupt disabled for Receive SERDES Data A An overflow condition occurs when new receive data is written into the Receive SERDES Data A register (Reg 0x09) before the prior data is read out. 1 EOF A The End of Frame A bit is used to enable the interrupt associated with an End of Frame condition with the Channel A Receiver. 1 = EOF A interrupt enabled for Channel A Receiver. 0 = EOF A interrupt disabled for Channel A Receiver. The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit has been detected, and then the number of invalid bits in a frame exceeds the number in the EOF length field. If 0 is the EOF length, an EOF condition will occur at the first invalid bit after a valid reception. This IRQ is cleared by reading the receive status register. N ot R ec om m en d ed fo rN ew D es ig ns 7 Document Number: 38-16007 Rev. *M Page 13 of 39 CYWUSB6932 CYWUSB6934 Bit 0 Name Full A Description The Full A bit is used to enable the interrupt associated with the Receive SERDES Data A register (0x09) having data written into it. 1 = Full A interrupt enabled for Receive SERDES Data A 0 = Full A interrupt disabled for Receive SERDES Data A A Full A condition occurs when data is transferred from the Channel A Receiver into the Receive SERDES Data A register (Reg 0x09). This could occur when a complete byte is received or when an EOF event occurs whether or not a complete byte has been received. Table 10. Receive SERDES Interrupt Status[5] Addr: 0x08 REG_RX_INT_STAT Default: 0x00 6 5 4 3 2 1 0 Flow Violation B EOF B Full B Valid A Flow Violation A EOF A Full A N ot R ec om m en d ed fo rN ew D es ig ns 7 Valid B Note 5. All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be implemented without enabling IRQs. The status bits are affected by TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the receive status will read 0 if the IC is not in receive mode. These registers are read-only. Document Number: 38-16007 Rev. *M Page 14 of 39 CYWUSB6932 CYWUSB6934 Bit Name Description Valid B The Valid B bit is true when all the bits in the Receive SERDES Data B register (Reg 0x0B) are valid. 1 = All bits are valid for Receive SERDES Data B. 0 = Not all bits are valid for Receive SERDES Data B. When data is written into the Receive SERDES Data B register (Reg 0x0B) this bit is set if all of the bits within the byte that has been written are valid. This bit cannot generate an interrupt. 6 Flow Violation B The Flow Violation B bit is used to signal whether an overflow or underflow condition has occurred for the Receive SERDES Data B register (Reg 0x0B). 1 = Overflow/underflow interrupt pending for Receive SERDES Data B. 0 = No overflow/underflow interrupt pending for Receive SERDES Data B. Overflow conditions occur when the radio loads new data into the Receive SERDES Data B register (Reg 0x0B) before the prior data has been read. Underflow conditions occur when trying to read the Receive SERDES Data B register (Reg 0x0B) when the register is empty. This bit is cleared by reading the Receive Interrupt Status register (Reg 0x08) 5 EOF B The End of Frame B bit is used to signal whether an EOF event has occurred on the Channel B receive. 1 = EOF interrupt pending for Channel B. 0 = No EOF interrupt pending for Channel B. An EOF condition occurs for the Channel B Receiver when receive has begun and then the number of bit times specified in the SERDES Control register (Reg 0x06) elapse without any valid bits being received. This bit is cleared by reading the Receive Interrupt Status register (Reg 0x08) 4 Full B The Full B bit is used to signal when the Receive SERDES Data B register (Reg 0x0B) is filled with data. 1 = Receive SERDES Data B full interrupt pending. 0 = No Receive SERDES Data B full interrupt pending. A Full B condition occurs when data is transferred from the Channel B Receiver into the Receive SERDES Data B register (Reg 0x0B). This could occur when a complete byte is received or when an EOF event occurs whether or not a complete byte has been received. 3 Valid A The Valid A bit is true when all of the bits in the Receive SERDES Data A Register (Reg 0x09) are valid. 1 = All bits are valid for Receive SERDES Data A. 0 = Not all bits are valid for Receive SERDES Data A. When data is written into the Receive SERDES Data A register (Reg 0x09) this bit is set if all of the bits within the byte that has been written are valid. This bit cannot generate an interrupt. 2 Flow Violation A The Flow Violation A bit is used to signal whether an overflow or underflow condition has occurred for the Receive SERDES Data A register (Reg 0x09). 1 = Overflow/underflow interrupt pending for Receive SERDES Data A. 0 = No overflow/underflow interrupt pending for Receive SERDES Data A. Overflow conditions occur when the radio loads new data into the Receive SERDES Data A register (Reg 0x09) before the prior data has been read. Underflow conditions occur when trying to read the Receive SERDES Data A register (Reg 0x09) when the register is empty. This bit is cleared by reading the Receive Interrupt Status register (Reg 0x08) 1 EOF A The End of Frame A bit is used to signal whether an EOF event has occurred on the Channel A receive. 1 = EOF interrupt pending for Channel A. 0 = No EOF interrupt pending for Channel A. An EOF condition occurs for the Channel A Receiver when receive has begun and then the number of bit times specified in the SERDES Control register (0x06) elapse without any valid bits being received. This bit is cleared by reading the Receive Interrupt Status register (Reg 0x08). 0 Full A The Full A bit is used to signal when the Receive SERDES Data A register (Reg 0x09) is filled with data. 1 = Receive SERDES Data A full interrupt pending. 0 = No Receive SERDES Data A full interrupt pending. A Full A condition occurs when data is transferred from the Channel A Receiver into the Receive SERDES Data A Register (Reg 0x09). This could occur when a complete byte is received or when an EOF event occurs whether or not a complete byte has been received. N ot R ec om m en d ed fo rN ew D es ig ns 7 Document Number: 38-16007 Rev. *M Page 15 of 39 CYWUSB6932 CYWUSB6934 Table 11. Receive SERDES Data A Addr: 0x09 7 REG_RX_DATA_A 6 5 4 Default: 0x00 3 2 1 0 Data Bit 7:0 Name Data Description Received Data for Channel A. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only. REG_RX_VALID_A 6 5 4 3 2 Default: 0x00 1 0 Name Description These bits indicate which of the bits in the Receive SERDES Data A register (Reg 0x09) are valid. A “1” indicates that the corresponding data bit is valid for Channel A. If the Valid Data bit is set in the Receive Interrupt Status register (Reg 0x08) all eight bits in the Receive SERDES Data A register (Reg 0x0A) are valid. Therefore, it is not necessary to read the Receive SERDES Valid A register (Reg 0x0C). This register is read-only. en d ed fo 7:0 Valid rN Bit ew D Valid es ig Addr: 0x0A 7 ns Table 12. Receive SERDES Valid A ec om Addr: 0x0B 6 5 REG_RX_DATA_B 4 3 Default: 0x00 2 1 0 Data 7:0 Name Data N Bit ot R 7 m Figure 9. Receive SERDES Data B Description Received Data for Channel B. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only. Document Number: 38-16007 Rev. *M Page 16 of 39 CYWUSB6932 CYWUSB6934 Table 13. Receive SERDES Valid B Addr: 0x0C 7 REG_RX_VALID_B 6 5 4 Default: 0x00 3 2 1 0 Valid Bit Valid Description These bits indicate which of the bits in the Receive SERDES Data B register (Reg 0x0B) are valid. A “1” indicates that the corresponding data bit is valid for Channel B. If the Valid Data bit is set in the Receive Interrupt Status register (0x08) all eight bits in the Receive SERDES Data B register (Reg 0x0B) are valid. Therefore, it is not necessary to read the Receive SERDES Valid B register (Reg 0x0C). This register is read-only. es ig ns 7:0 Name Table 14. Transmit SERDES Interrupt Enable 6 5 4 3 ew 7 REG_TX_INT_EN Underflow Default: 0x00 2 1 0 Overflow Done Empty rN Reserved Name Description fo Bit D Addr: 0x0D Reserved These bits are reserved and should be written with zeroes. 3 Underflow The Underflow bit is used to enable the interrupt associated with an underflow condition associated with the Transmit SERDES Data register (Reg 0x0F) 1 = Underflow interrupt enabled. 0 = Underflow interrupt disabled. An underflow condition occurs when attempting to transmit while the Transmit SERDES Data register (Reg 0x0F) does not have any data. 2 Overflow The Overflow bit is used to enabled the interrupt associated with an overflow condition with the Transmit SERDES Data register (0x0F). 1 = Overflow interrupt enabled. 0 = Overflow interrupt disabled. An overflow condition occurs when attempting to write new data to the Transmit SERDES Data register (Reg 0x0F) before the preceding data has been transferred to the transmit shift register. 1 Done The Done bit is used to enable the interrupt that signals the end of the transmission of data. 1 = Done interrupt enabled. 0 = Done interrupt disabled. The Done condition occurs when the Transmit SERDES Data register (Reg 0x0F) has transmitted all of its data and there is no more data for it to transmit. 0 Empty The Empty bit is used to enable the interrupt that signals when the Transmit SERDES register (Reg 0x0F) is empty. 1 = Empty interrupt enabled. 0 = Empty interrupt disabled. The Empty condition occurs when the Transmit SERDES Data register (Reg 0x0F) is loaded into the transmit buffer and it's safe to load the next byte N ot R ec om m en d ed 7:4 Document Number: 38-16007 Rev. *M Page 17 of 39 CYWUSB6932 CYWUSB6934 Table 15. Transmit SERDES Interrupt Status[6] Addr: 0x0E 7 REG_TX_INT_STAT 6 5 4 Reserved Bit Name Default: 0x00 3 2 1 0 Underflow Overflow Done Empty Description 7:4 Reserved These bits are reserved. This register is read-only. Underflow The Underflow bit is used to signal when an underflow condition associated with the Transmit SERDES Data register (Reg 0x0F) has occurred. 1 = Underflow Interrupt pending. 0 = No Underflow Interrupt pending. This IRQ will assert during an underflow condition to the Transmit SERDES Data register (Reg 0x0F). An underflow occurs when the transmitter is ready to sample transmit data, but there is no data ready in the Transmit SERDES Data register (Reg 0x0F). This will only assert after the transmitter has transmitted at least one bit. This bit is cleared by reading the Transmit Interrupt Status register (Reg 0x0E). 2 Overflow The Overflow bit is used to signal when an overflow condition associated with the Transmit SERDES Data register (0x0F) has occurred. 1 = Overflow Interrupt pending. 0 = No Overflow Interrupt pending. This IRQ will assert during an overflow condition to the Transmit SERDES Data register (Reg 0x0F). An overflow occurs when the new data is loaded into the Transmit SERDES Data register (Reg 0x0F) before the previous data has been sent. This bit is cleared by reading the Transmit Interrupt Status register (Reg 0x0E). 1 Done The Done bit is used to signal the end of a data transmission. 1 = Done Interrupt pending. 0 = No Done Interrupt pending. This IRQ will assert when the data is finished sending a byte of data and there is no more data to be sent. This will only assert after the transmitter has transmitted as least one bit. This bit is cleared by reading the Transmit Interrupt Status register (Reg 0x0E) 0 Empty The Empty bit is used to signal when the Transmit SERDES Data register (Reg 0x0F) has been emptied. 1 = Empty Interrupt pending. 0 = No Empty Interrupt pending. This IRQ will assert when the transmit serdes is empty. When this IRQ is asserted it is ok to write to the Transmit SERDES Data register (Reg 0x0F). Writing the Transmit SERDES Data register (Reg 0x0F) will clear this IRQ. It will be set when the data is loaded into the transmitter, and it is ok to write new data. N ot R ec om m en d ed fo rN ew D es ig ns 3 Note 6. All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be implemented without enabling IRQs. The status bits are affected by the TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the transmit status will read 0 if the IC is not in transmit mode. These registers are read-only. Document Number: 38-16007 Rev. *M Page 18 of 39 CYWUSB6932 CYWUSB6934 Table 16. Transmit SERDES Data Addr: 0x0F 7 REG_TX_DATA 6 5 4 Default: 0x00 3 2 1 0 Data Bit Name 7:0 Data Description Transmit Data. The over-the-air transmitted order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. REG_TX_VALID 6 5 4 Default: 0x00 es ig Addr: 0x10 7 ns Table 17. Transmit SERDES Valid 3 2 0 Name Description rN Bit Valid[7] The Valid bits are used to determine which of the bits in the Transmit SERDES Data register (reg 0x0F) are valid. 1 = Valid transmit bit. 0 = Invalid transmit bit. en d ed fo 7:0 ew D Valid 1 Table 18. PN Code m Addr: 0x11-18 Default: 0x1E8B6A3DE0E9B222 REG_PN_CODE ec om 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Address 0x17 Address 0x16 Address 0x15 ot R Address 0x18 Address 0x14 Bit 63:0 N 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Name PN Codes Address 0x13 Address 0x12 8 7 6 5 4 3 2 1 0 Address 0x11 Description The value inside the 8 byte PN code register is used as the spreading code for DSSS communication. All 8 bytes can be used together for 64 chips/bit PN code communication, or the registers can be split into two sets of 32 chips/bit PN codes and these can be used alone or with each other to accomplish faster data rates. Not any 64 chips/bit value can be used as a PN code as there are certain characteristics that are needed to minimize the possibility of multiple PN codes interfering with each other or the possibility of invalid correlation. The over-the-air order is bit 0 followed by bit 1... followed by bit 62, followed by bit 63. Note 7. The Valid bit in the Transmit SERDES Valid register (Reg 0x10) is used to mark whether the radio will send data or preamble during that bit time of the data byte. Data is sent LSB first. The SERDES will continue to send data until there are no more VALID bits in the shifter. For example, writing 0x0F to the Transmit SERDES Valid register (Reg 0x10) will send half a byte. Document Number: 38-16007 Rev. *M Page 19 of 39 CYWUSB6932 CYWUSB6934 Table 19. Threshold Low Addr: 0x19 REG_THRESHOLD_L 7 6 5 4 Reserved Bit Default: 0x08 3 2 1 0 Threshold Low Name Description Reserved This bit is reserved and should be written with zero. 6:0 Threshold Low The Threshold Low value is used to determine the number of missed chips allowed when attempting to correlate a single data bit of value ‘0’. A perfect reception of a data bit of ‘0’ with a 64 chips/bit PN code would result in zero correlation matches, meaning the exact inverse of the PN code has been received. By setting the Threshold Low value to 0x08 for example, up to eight chips can be erroneous while still identifying the value of the received data bit. This value along with the Threshold High value determine the correlator count values for logic ‘1’ and logic ‘0’. The threshold values used determine the sensitivity of the receiver to interference and the dependability of the received data. By allowing a minimal number of erroneous chips the dependability of the received data increases while the robustness to interference decreases. On the other hand increasing the maximum number of missed chips means reduced data integrity but increased robustness to interference and increased range. D es ig ns 7 ew Table 20. Threshold High REG_THRESHOLD_H 6 5 rN Addr: 0x1A 7 4 3 0 Threshold High ed Name en d Bit 1 fo Reserved Default: 0x38 2 Description Reserved This bit is reserved and should be written with zero. 6:0 Threshold High The Threshold High value is used to determine the number of matched chips allowed when attempting to correlate a single data bit of value ‘1’. A perfect reception of a data bit of ‘1’ with a 64 chips/bit or a 32 chips/bit PN code would result in 64 chips/bit or 32 chips/bit correlation matches, respectively, meaning every bit was received perfectly. By setting the Threshold High value to 0x38 (64-8) for example, up to eight chips can be erroneous while still identifying the value of the received data bit. This value along with the Threshold Low value determine the correlator count values for logic ‘1’ and logic ‘0’. The threshold values used determine the sensitivity of the receiver to interference and the dependability of the received data. By allowing a minimal number of erroneous chips the dependability of the received data increases while the robustness to interference decreases. On the other hand increasing the maximum number of missed chips means reduced data integrity but increased robustness to interference and increased range. N ot R ec om m 7 Table 21. Wake Enable Addr: 0x1C 7 REG_WAKE_EN 6 5 4 3 Reserved Bit Name 7:1 Reserved 0 Default: 0x00 2 1 0 Wakeup Enable Description These bits are reserved and should be written with zeroes. Wakeup Enable Wakeup interrupt enable. 0 = disabled 1 = enabled A wakeup event is triggered when the PD pin is deasserted and once the IC is ready to receive SPI communications. Document Number: 38-16007 Rev. *M Page 20 of 39 CYWUSB6932 CYWUSB6934 Table 22. Wake Status Addr: 0x1D 7 REG_WAKE_STAT 6 5 4 Default: 0x01 3 2 1 0 Reserved Bit Wakeup Status Name Description 7:1 Reserved 0 Wakeup Status Wakeup status. 0 = Wake interrupt not pending 1 = Wake interrupt pending These bits are reserved. This register is read-only. Addr: 0x20 REG_ANALOG_CTL 6 5 4 3 Reserved Reg Write Control MID Read Enable Reserved Reserved rN Default: 0x00 2 1 0 PA Output Enable PA Invert Reset fo Bit ew 7 D Table 23. Analog Control es ig ns This IRQ will assert when a wakeup condition occurs. This bit is cleared by reading the Wake Status register (Reg 0x1D). This register is read-only. Name Description Reserved This bit is reserved and should be written with zero. 6 Reg Write Control Enables write access to Reg 0x2E and Reg 0x2F. 1 = Enables write access to Reg 0x2E and Reg 0x2F 0 = Reg 0x2E and Reg 0x2F are read-only 5 MID Read Enable The MID Read Enable bit must be set to read the contents of the Manufacturing ID register (Reg 0x3C-0x3F). Enabling the Manufacturing ID register (Reg 0x3C-0x3F) consumes power. This bit should only be set when reading the contents of the Manufacturing ID register (Reg 0x3C-0x3F). 1 = Enables read of MID registers 0 = Disables read of MID registers ec om m en d ed 7 Reserved 2 PA Output Enable The Power Amplifier Output Enable bit is used to enable the PACTL pin for control of an external power amplifier. 1 = PA Control Output Enabled on PACTL pin 0 = PA Control Output Disabled on PACTL pin These bits are reserved and should be written with zeroes. 1 PA Invert The Power Amplifier Invert bit is used to specify the polarity of the PACTL signal when the PA Output Enable bit is set high. PA Output Enable and PA Invert cannot be simultaneously changed. 1 = PACTL active low 0 = PACTL active high 0 Reset The Reset bit is used to generate a self-clearing device reset. 1 = Device Reset. All registers are restored to their default values. 0 = No Device Reset. N ot R 4:3 Document Number: 38-16007 Rev. *M Page 21 of 39 CYWUSB6932 CYWUSB6934 Table 24. Channel Addr: 0x21 7 REG_CHANNEL 6 5 4 3 Reserved Bit 7 Default: 0x00 2 1 0 Channel Name Description Reserved This bit is reserved and should be written with zero. The Channel register (Reg 0x21) is used to determine the Synthesizer frequency. A value of 2 corresponds to a communication frequency of 2.402 GHz, while a value of 79 corresponds to a frequency of 2.479GHz. The channels are separated from each other by 1 MHz intervals. Limit application usage to channels 2-79 to adhere to FCC regulations. FCC regulations require that channels 0 and 1 and any channel greater than 79 be avoided. Use of other channels may be restricted by other regulatory agencies. The application MCU must ensure that this register is modified before transmitting data over the air for the first time. es ig ns 6:0 Channel Addr: 0x22 6 5 3 2 1 0 RSSI Name Description fo Bit 4 Valid Default: 0x00 rN Reserved ew 7 REG_RSSI D Table 25. Receive Signal Strength Indicator (RSSI)[8] These bits are reserved. This register is read-only. 5 The Valid bit indicates whether the RSSI value in bits [4:0] are valid. This register is Read Only. 1 = RSSI value is valid 0 = RSSI value is invalid en d The Receive Strength Signal Indicator (RSSI) value indicates the strength of the received signal. This is a read only value with the higher values indicating stronger received signals meaning more reliable transmissions. m 4:0 RSSI ec om Valid ed 7:6 Reserved 6 N 7 ot Addr: 0x23 R Table 26. PA Bias Bit 5 REG_PA 4 Default: 0x00 3 Reserved Name 2 1 0 PA Bias Description 7:3 Reserved These bits are reserved and should be written with zeroes. 2:0 PA Bias The Power Amplifier Bias (PA Bias) bits are used to set the transmit power of the IC through increasing (values up to 7) or decreasing (values down to 0) the gain of the on-chip Power Amplifier. The higher the register value the higher the transmit power. By changing the PA Bias value signal strength management functions can be accomplished. For general purpose communication a value of 7 is recommended. Note 8. The RSSI will collect a single value each time the part is put into receive mode via Control register (Reg 0x03, bit 7=1). See Section for more details. Document Number: 38-16007 Rev. *M Page 22 of 39 CYWUSB6932 CYWUSB6934 Table 27. Crystal Adjust Addr: 0x24 REG_CRYSTAL_ADJ 7 6 Reserved Clock Output Disable Bit 5 4 Default: 0x00 3 2 1 0 Crystal Adjust Name Description Reserved This bit is reserved and should be written with zero. 6 Clock Output Disable The Clock Output Disable bit disables the 13 MHz clock driven on the X13OUT pin. 1 = No 13-MHz clock driven externally. 0 = 13-MHz clock driven externally. If the 13-MHz clock is driven on the X13OUT pin then receive sensitivity will be reduced by –4 dBm on channels 5+13n. By default the 13-MHz clock output pin is enabled. This pin is useful for adjusting the 13-MHz clock, but it interfere with every 13th channel beginning with 2.405GHz channel. Therefore, it is recommended that the 13-MHz clock output pin be disabled when not in use. es ig ns 7 The Crystal Adjust value is used to calibrate the on-chip parallel load capacitance supplied to the crystal. Each increment of the Crystal Adjust value typically adds 0.135 pF of parallel load capacitance. The total range is 8.5 pF, starting at 8.65 pF. These numbers do not include PCB parasitics, which can add an additional 1–2 pF. rN ew D 5:0 Crystal Adjust Table 28. VCO Calibration REG_VCO_CAL 5 4 en d VCO Slope Enable Name Default: 0x00 2 1 0 Reserved Description m Bit 3 ed 6 fo Addr: 0x26 7 ot R ec om 7:6 VCO Slope Enable The Voltage Controlled Oscillator (VCO) Slope Enable bits are used to specify the amount of variance (Write-Only) automatically added to the VCO. 11 = –5/+5 VCO adjust. The application MCU must configure this option during initialization. 10 = –2/+3 VCO adjust. 01 = Reserved. 00 = No VCO adjust. These bits are undefined for read operations. These bits are reserved and should be written with zeroes. N 5:0 Reserved Table 29. Reg Power Control Addr: 0x2E 7 REG_PWR_CTL 6 Reg Power Control Bit 5 4 3 Default: 0x00 2 1 0 Reserved Name Description 7 Reg Power Control When set, this bit disables unused circuitry and saves radio power. The user must set Reg 0x20, bit 6=1 to enable writes to Reg 0x2E. The application MCU must set this bit during initialization. 6:0 Reserved These bits are reserved and should be written with zeroes. Document Number: 38-16007 Rev. *M Page 23 of 39 CYWUSB6932 CYWUSB6934 Table 30. Carrier Detect Addr: 0x2F 7 REG_CARRIER_DETECT 6 5 4 3 Carrier Detect Override Bit Default: 0x00 2 1 0 Reserved Name Description 7 Carrier Detect Override When set, this bit overrides carrier detect. The user must set Reg 0x20, bit 6=1 to enable writes to Reg 0x2F. 6:0 Reserved Addr: 0x32 7 REG_CLOCK_MANUAL 6 5 4 3 2 Default: 0x00 1 0 Name Description fo Bit Manual Clock Overrides This register must be written with 0x41 after reset for correct operation en d ed 7:0 rN ew Manual Clock Overrides D Table 31. Clock Manual es ig ns These bits are reserved and should be written with zeroes. Table 32. Clock Enable 4 3 Name Default: 0x00 2 1 0 Manual Clock Enables R ec om 5 Description ot Bit Manual Clock Enables This register must be written with 0x41 after reset for correct operation N 7:0 REG_CLOCK_ENABLE 6 m Addr: 0x33 7 Table 33. Synthesizer Lock Count Addr: 0x38 7 REG_SYN_LOCK_CNT 6 5 4 3 Default: 0x64 2 1 0 Count Bit 7:0 Name Description Count Determines the length of delay in 2µs increments for the synthesizer to lock when auto synthesizer is enabled via Control register (0x03, bit 1=0) and not using the PLL lock signal. The default register setting is typically sufficient. Document Number: 38-16007 Rev. *M Page 24 of 39 CYWUSB6932 CYWUSB6934 Table 34. Manufacturing ID Addr: 0x3C-3F REG_MID 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Address 0x3F Bit 31:30 8 7 Address 0x3D 6 5 4 3 2 1 0 Address 0x3C Name Description Address[31:3 These bits are read back as zeroes. 0] Address[29:0] These bits are the Manufacturing ID (MID) for each IC. The contents of these bits cannot be read unless the MID Read Enable bit (bit 5) is set in the Analog Control register (Reg 0x20). Enabling the Manufacturing ID register (Reg 0x3C-0x3F) consumes power. The MID Read Enable bit in the Analog Control register (Reg 0x20, bit 5) should only be set when reading the contents of the Manufacturing ID register (Reg 0x3C-0x3F). This register is read-only. N ot R ec om m en d ed fo rN ew D es ig ns 29:0 Address 0x3E 9 Document Number: 38-16007 Rev. *M Page 25 of 39 CYWUSB6932 CYWUSB6934 Pin Definitions Table 35. Pin Description Table for the CYWUSB6932/CYWUSB6934 Pin QFN Name 46 RFIN 5 RFOUT 38 35 Type Default Description Input Input RF Input. Modulated RF signal received (CYWUSB6934 only). Output N/A RF Output. Modulated RF signal to be transmitted. X13 Input N/A Crystal Input. (refer to “Clocking and Power Management” on page 4). X13IN Input N/A Crystal Input. (refer to “Clocking and Power Management” on page 4). X13OUT 33 PD Input N/A Power Down. Asserting this input (low), will put the CYWUSB6932/CYWUSB6934 in the Suspend Mode (X13OUT is 0 when PD is low). 14 RESET Input N/A Active LOW Reset. Device reset. 34 PACTL I/O Input PACTL. External Power Amplifier control. Pull-down or make output. 20 DIO I/O Input Data Input/Output. SERDES Bypass Mode Data Transmit/Receive. 19 DIOVAL I/O Input Data I/O Valid. SERDES Bypass Mode Data Transmit/Receive Valid. 21 IRQ Output /Hi-Z Output System Clock. Buffered 13-MHz system clock. es ig D Output/Hi-Z ns 26 Output IRQ. Interrupt and SERDES Bypass Mode DIOCLK. MOSI Input N/A Master-Output-Slave-Input Data. SPI data input pin. 24 MISO Output/Hi-Z Hi-Z Master-Input-Slave-Output Data. SPI data output pin. 25 SCK Input N/A SPI Input Clock. SPI clock. 22 SS Input N/A VCC H VCC = 2.7 V to 3.6 V. GND L Ground = 0 V. N/A N/A Exposed Paddle GND rN fo ed en d m Must be tied to Ground. ec om 1, 2, 3, 4, 7, NC 8, 10, 11, 12, 15, 17, 18, 27, 30, 31, 36, 37, 39, 40, 43, 47, 48 R GND ot 13 Slave Select Enable. SPI enable. GND L Must be tied to Ground. N 6, 9, 16, 28, VCC 29, 32, 41, 42, 44, 45 ew 23 Document Number: 38-16007 Rev. *M Page 26 of 39 CYWUSB6932 CYWUSB6934 Figure 10. CYWUSB6934/CYWUSB6932, 48-pin QFN – Top View CYWUSB6934/CYWUSB6932 Top View* NC 37 X13 38 NC 39 NC 40 VC C 41 VC C 42 NC 43 VC C 44 VC C 45 **RFIN 46 NC 47 NC 48 36 NC NC 2 35 X13IN NC 3 34 PACTL NC 4 33 PD RFOUT 5 NC 7 32 VC C CYWUSB6934/CYWUSB6932 48 QFN 31 NC es ig VC C 6 ns NC 1 30 NC 29 VC C D NC 8 28 VC C ew VC C 9 NC 10 NC 12 fo 26 X13OUT en d 24 MISO ed 27 NC 25 SCK 23 MOSI 22 SS 21 IRQ 20 DIO 19 DIOVAL 18 NC 17 NC 16 VC C 15 NC 14 RESET 13 GND rN NC 11 m * E-PAD BOTTOM SIDE N ot R ec om ** CYWUSB6934 Only Document Number: 38-16007 Rev. *M Page 27 of 39 CYWUSB6932 CYWUSB6934 Static discharge voltage (Digital)[10] ........................ >2000 V Absolute Maximum Ratings Static discharge voltage (RF)[10] ................................. 500 V Storage temperature ................................ –65 °C to +150 °C Latch up current ......................................+200 mA, –200 mA Ambient temperature with power applied ................................... –55 °C to +125 °C Operating Conditions Supply voltage on VCC relative to VSS ........–0.2 V to +3.9 V VCC (supply voltage) ........................................2.7 V to 3.6 V DC voltage to logic inputs[9] ................. –0.2 V to VCC +0.2 V TA (ambient temperature under bias) ............ 0 °C to +70 °C DC voltage applied to outputs in High-Z state ......................... –0.2 V to VCC +0.2 V Ground voltage ................................................................ 0 V FOSC (oscillator or crystal frequency) ........ 13 MHz ±50 ppm DC Characteristics ns Over the Operating Range Table 36. DC Parameters Min Typ[12] Max Unit 2.7 3.0 3.6 V At IOH = –100.0 µA VCC – 0.1 VCC – V 2.4 3.0 – V – 0.0 0.4 V 2.0 – VCC[11] V 0.8 V es ig Parameter Description Conditions Supply voltage VOH1 Output high voltage condition 1 VOH2 Output high voltage condition 2 At IOH = –2.0 mA VOL Output low voltage At IOL = 2.0 mA VIH Input high voltage VIL Input low voltage IIL Input leakage current CIN Pin input capacitance (except X13, X13IN, RFIN) en d ed fo rN ew D VCC 0 < VIN < VCC –0.3 –1 0.26 +1 µA – 3.5 10 pF µA Current consumption during power-down mode PD = LOW – 0.24 IDLE ICC Current consumption without synthesizer PD = HIGH – 3 – mA m ISleep 10[15] STARTUP ICC ICC from PD high to oscillator stable. TX AVG ICC1 Average transmitter current consumption[13] TX AVG ICC2 Average transmitter current consumption[14] RX ICC (PEAK) TX ICC (PEAK) 1.8 – mA – 5.9 – mA With handshake – 8.1 – mA Current consumption during receive – 57.7 – mA Current consumption during transmit – 69.1 – mA – 28.7 – mA ot R ec om – No handshake N SYNTH SETTLE ICC Current consumption with synthesizer on, no transmit or receive Notes 9. It is permissible to connect voltages above Vcc to inputs through a series resistor limiting input current to 1 mA. This can’t be done during power down mode. AC timing not guaranteed. 10. Human Body Model (HBM). 11. It is permissible to connect voltages above Vcc to inputs through a series resistor limiting input current to 1 mA. 12. Typ. values measured with VCC = 3.0 V at 25 °C 13. Average Icc when transmitting a 5-byte packet (3 data bytes + 2 bytes of protocol) every 10 ms using the WirelessUSB LS 1-way protocol. 14. Average Icc when transmitting a 5-byte packet (3 data bytes + 2 bytes of protocol) every 10 ms using the WirelessUSB LS 2-way protocol. 15. Max value measured with VCC = 3.2 V. Document Number: 38-16007 Rev. *M Page 28 of 39 CYWUSB6932 CYWUSB6934 AC Characteristics[16] Table 37. SPI Interface[17] Min Typ Max Unit tSCK_CYC Parameter SPI clock period Description 476 – – ns tSCK_HI (BURST READ)[18] SPI clock high time 238 – – ns tSCK_HI SPI clock high time 158 – – ns tSCK_LO SPI clock low time 158 – – ns tDAT_SU SPI input data setup time 10 – – ns [17] tDAT_HLD SPI input data hold time 97 – – ns tDAT_VAL SPI output data valid time 77[17] – 174[17] ns SPI slave select setup time before first positive edge of tSS_HLD SPI slave select hold time after last negative edge of SCK – – ns 80 – – ns D Figure 11. SPI Timing Diagram 250 es ig tSS_SU ns SCK[19] tSCK_LO rN tSC K_H I ew tSC K_C YC tDAT_SU M PL D E tDAT_H LD R IV E tSS_HLD ed MOSI SA d a ta fro m m c u d a ta fro m m c u d a ta fro m m c u d a ta d a ta to m c u d a ta tDAT_VAL en d SS tSS_SU fo SCK M IS O ec om m d a ta to m c u Figure 12. SPI Burst Read Every 9th SCK HI Stretch Timing Diagram R t SC K_CYC N every 8 th SCK_HI t SCK_H I (BURST READ) every 9 th SCK_HI D SS M ISO t SCK_LO ot t SCK_HI SCK R every 10 th SCK_HI D IV E data to m cu data to m cu R IV D E data to m cu R IV E data t DAT_VAL Notes 16. AC values are not guaranteed if voltages on any pin exceed Vcc. 17. For FOSC = 13 MHz ±50 ppm, 3.2 V at 25°C. 18. This stretch only applies to every 9th SCK HI pulse for SPI Burst Reads only. 19. SCK must start low, otherwise the success of SPI transactions are not guaranteed. Document Number: 38-16007 Rev. *M Page 29 of 39 CYWUSB6932 CYWUSB6934 Table 38. DIO Interface Parameter Description Min Typ Max Unit DIOVAL setup time 2.1 – – µs tTX_DIO_SU DIO setup time 2.1 – – µs tTX_DIOVAL_HLD DIOVAL hold time 0 – – µs tTX_DIO_HLD DIO hold time 0 – – µs tTX_IRQ_HI Minimum IRQ high time - 32 chips/bit DDR – 8 – µs Minimum IRQ high time - 32 chips/bit – 16 – µs Minimum IRQ high time - 64 chips/bit – 32 – µs Minimum IRQ low time - 32 chips/bit DDR – 8 – µs Minimum IRQ low time - 32 chips/bit – 16 – µs Minimum IRQ low time - 64 chips/bit – 32 – µs –0.01 – 6.1 µs –0.01 – 8.2 µs –0.01 – 16.1 µs –0.01 – 6.1 µs –0.01 – 8.2 µs tTX_IRQ_LO es ig tTX_DIOVAL_SU ns Transmit Receive DIOVAL valid time - 32 chips/bit DDR D tRX_DIOVAL_VLD ew DIOVAL valid time - 32 chips/bit DIOVAL valid time - 64 chips/bit DIO valid time - 32 chips/bit DDR rN tRX_DIO_VLD fo DIO valid time - 32 chips/bit DIO valid time - 64 chips/bit –0.01 – 16.1 µs Minimum IRQ high time - 32 chips/bit DDR – 1 – µs Minimum IRQ high time - 32 chips/bit – 1 – µs Minimum IRQ high time - 64 chips/bit – 1 – µs Minimum IRQ low time - 32 chips/bit DDR – 8 – µs Minimum IRQ low time - 32 chips/bit – 16 – µs Minimum IRQ low time - 64 chips/bit – 32 – µs en d ed tRX_IRQ_HI ec om m tRX_IRQ_LO IR Q D IO / D IO V A L N ot R Figure 13. DIO Receive Timing Diagram SA M PL t R X _ IR Q _ H I t R X _ IR Q _ L O SA E d a ta M PL E d a ta d a ta t t R XR_XD_IOD VIOA_LV_LVDL D Figure 14. DIO Transmit Timing Diagram t TX _IR Q _ H I IR Q D IO / D IO V A L Document Number: 38-16007 Rev. *M t TX _IR Q _LO SA M PL SA E data t T X _D IO _S U t T X_D IO VA L_S U M PL E data t IO _H LD t T X_T X_D D IO V AL _H LD Page 30 of 39 CYWUSB6932 CYWUSB6934 Radio Parameters Table 39. Radio Parameters Parameter Description Conditions RF frequency range Min Note 20 Typ 2.400 Max Unit 2.483 GHz Radio Receiver (T = 25 °C, VCC = 3.2 V, fosc = 13.000 MHz, X13OUT off, 64 chips/bit, Threshold Low = 8, Threshold High = 56, BER < 10–3) Sensitivity – –90 – dBm –20 –10 – dBm RSSI value for PWRin > –40 dBm – 28–31 – RSSI value for PWRin < –95 dBm – 0–10 – Receive Ready[21] – – 35 µs – 11 – dB – 3 – dB – –30 – dB – –40 – dB – –20 – dB – –25 – dB C = –67 dBm – –30 – dBm 2498 MHz – 12.75 GHz, except (FO*N and FO*N±1 MHz) [23] C = –67 dBm – –20 – dBm – –39 – dBm – – – – – –57 dBm –54 dBm Maximum received signal C = –60 dBm Adjacent (2 MHz) channel selectivity C/I 2 MHz C = –60 dBm Adjacent (> 3 MHz) channel selectivity C/I > 3 MHz C = –67 dBm Image Frequency Interference, C/I Image C = –67 dBm C = –67 dBm rN Adjacent (1 MHz) interference to in-band image frequency, C/I image ±1 MHz fo [22] es ig Adjacent (1 MHz) channel selectivity C/I 1 MHz D C = –60 dBm ew Co-channel interference rejection Carrier-to-Interference (C/I) ns Interference Performance Out-of-Band Blocking Interference Signal Frequency en d ed 30 MHz – 2399 MHz, except (FO/N and FO/N±1 MHz)[23] C = –64 dBm, f = 5,10 MHz m Intermodulation ec om Spurious Emission 30 MHz–1 GHz 1 GHz–12.75 GHz except (4.8 GHz - 5.0 GHz) – – 4.8 GHz–5.0 GHz – – – 0 – dBm R –40[24] dBm PA = 7 – 30 – dB RF power range control step size seven steps, monotonic – 4.3 – dB Frequency Deviation PN Code Pattern 10101010 – 270 – kHz Frequency Deviation PN Code Pattern 11110000 – 320 – kHz N RF power control range ot Radio Transmitter (T = 25 °C, VCC = 3.2 V, fosc = 13.000 MHz) Maximum RF transmit power Zero crossing error Occupied bandwidth 100-kHz resolution bandwidth, –6 dBc – ± 125 – ns 500 – – kHz kHz Initial frequency offset – ±75 – In-band Spurious – – – Second channel power (± 2 MHz) – – –30 dBm > Third channel power (>3 MHz) – – –40 dBm Notes 20. Subject to regulation. 21. Max. time after receive enable and the synthesizer has settled before receiver is ready. 22. Image frequency is +4 MHz from desired channel (2 MHz low IF, high side injection). 23. FO = Tuned Frequency, N = Integer. 24. Antenna matching network and antenna will attenuate the output signal at these frequencies to meet regulatory requirements. Document Number: 38-16007 Rev. *M Page 31 of 39 CYWUSB6932 CYWUSB6934 Table 39. Radio Parameters (continued) Parameter Description Conditions Min Typ Max Non-Harmonically Related Spurs – – – 30 MHz – 12.75 GHz – – –54 Harmonic Spurs – – – Second harmonic – – –28 Unit dBm dBm Third harmonic – – –25 dBm Fourth and greater harmonics – – –42 dBm Power Management Timing Description Conditions tPDN_X13 Time from PD deassert to X13OUT tSPI_RDY Time from oscillator stable to start of SPI transactions tPWR_RST Power On to RESET deasserted tRST Minimum RESET asserted pulse width ew D VCC at 2.7 V PD deassert to clocks running[27] tPD Minimum PD asserted pulse width tSLEEP PD assert to low power mode IRQ[28] assert interrupt)[29] PD deassert to tSTABLE PD deassert to clock stable tSTABLE2 IRQ assert (wake interrupt) to clock stable ed tWAKE_INT Typ Max. Unit – 2000 – µs 1 – – µs 1300 – – µs 1 – – µs 1300 – – µs – 2000 – µs 10 – – µs – 50 – ns – 2000 – µs to within ±10 ppm – 2100 – µs to within ±10 ppm – 2100 – µs N ot R ec om m en d (wake fo Power On to PD tWAKE rN deasserted[26] tPWR_PD Min es ig Parameter ns Table 40. Power Management Timing (The values below are dependent upon oscillator network component selection)[25] Notes 25. Measured with CTS ATXN6077A crystal. 26. The PD pin must be asserted at power up to ensure proper crystal startup. 27. When X13OUT is enabled. 28. Both the polarity and the drive method of the IRQ pin are programmable. See page 11 for more details. Figure 16 illustrates default values for the Configuration register (Reg 0x05, bits 1:0). 29. A wakeup event is triggered when the PD pin is deasserted. Figure 16 illustrates a wakeup event configured to trigger an IRQ pin event via the Wake Enable register (Reg 0x1C, bit 0=1). Document Number: 38-16007 Rev. *M Page 32 of 39 CYWUSB6932 CYWUSB6934 Figure 15. Power On Reset/Reset Timing tPDN_X13 X13O U T S VCC t S P I_ R D Y A T R T tPW R_PD Figure 16. Sleep / Wake Timing IR Q fo tSLEEP rN KE t PD EP ew A W E SL PD D tWAKE X13OUT ed tWAKE_INT tSTABLE tSTABLE2 N ot R ec om m en d IRQ ns PD tRST es ig tPW R _R ST P U RESET Document Number: 38-16007 Rev. *M Page 33 of 39 CYWUSB6932 CYWUSB6934 Figure 17. AC Test Loads and Waveforms for Digital Pins AC Test Loads DC Test Load OUTPUT OUTPUT 30 pF INCLUDING JIG AND SCOPE R1 VCC 5 pF OUTPUT INCLUDING JIG AND Typical SCOPE Max R2 ALL INPUT PULSES VCC Unit V V 90% 90% 10% 10% GND Fall time: 1 V/ns ns Rise time: 1 V/ns THÉVENIN EQUIVALENT RTH VTH OUTPUT Equivalent to: es ig 1071 937 500 1.4 3.00 N ot R ec om m en d ed fo rN ew D Parameter R1 R2 RTH VTH VCC Document Number: 38-16007 Rev. *M Page 34 of 39 CYWUSB6932 CYWUSB6934 Ordering Information Table 41. Ordering Information Part Number CYWUSB6934-48LTXC Radio Package Name Transceiver Package Type Operating Range 48-pin QFN (Sawn) 48-pin QFN (Pb-free) Commercial Ordering Code Definitions CY WUSB 6934 48-LTX C es ig ns Temperature range: Commercial 48-pin Sawn QFN package X = Pb-free D Part Number N ot R ec om m en d ed fo rN Company ID: CY = Cypress ew Marketing Code: Wireless USB family Document Number: 38-16007 Rev. *M Page 35 of 39 CYWUSB6932 CYWUSB6934 Package Diagram 001-53698 *B N ot R ec om m en d ed fo rN ew D es ig ns Figure 18. 48-pin QFN 7 × 7 × 1.0 mm LT48C 4.5 × 4.5 E-Pad (Sawn) Package Outline, 001-53698 Document Number: 38-16007 Rev. *M Page 36 of 39 CYWUSB6932 CYWUSB6934 Acronyms Document Conventions Table 42. Acronyms Used in this Document Acronym Units of Measure Description Table 43. Units of Measure BER Bit Error Rate CMOS Complementary Metal Oxide Semiconductor °C degree Celsius CRC Cyclic Redundancy Check dB decibel FEC Forward Error Correction dBc decibel relative to carrier FER Frame Error Rate dBm decibel-milliwatt GFSK Gaussian Frequency-Shift Keying Hz hertz HBM Human Body Model KB 1024 bytes ISM Industrial, Scientific, and Medical Kbit 1024 bits IRQ Interrupt Request kHz kilohertz MCU Microcontroller Unit k kilohm NRZ Non Return to Zero MHz megahertz PLL Phase Locked Loop M megaohm QFN Quad Flat No-leads A RSSI Received Signal Strength Indication s RF Radio Frequency V Rx Receive Tx Transmit es ig D ew rN microsecond W microwatt mA milliampere ms millisecond mV millivolt nA nanoampere ns nanosecond nV nanovolt ohm pp peak-to-peak ppm parts per million ps picosecond sps samples per second V volt fo ed en d m ec om R ot N microampere microvolt Vrms Document Number: 38-16007 Rev. *M Unit of Measure ns Symbol microvolts root-mean-square Page 37 of 39 CYWUSB6932 CYWUSB6934 Document History Page Document Title: CYWUSB6932/CYWUSB6934, WirelessUSB™ LS 2.4 GHz DSSS Radio SoC Document Number: 38-16007 Revision ECN Orig. of Change Submission Date ** 123907 LXA 01/20/03 *A 125470 XGR 04/28/03 Preliminary release *B 127076 KKU 07/30/03 Updated pinouts, timing diagrams, AC Test loads, DC Characteristics, Radio Characteristics Removed die *C 128886 KKV 08/04/03 Minor change: removed table of contents and fixed layout of section 10. *D 129180 TGE 12/04/03 Updated AC and DC characteristics from char. results Updated register entries Changed package type from 56-pin QFN to 48-pin QFN Updated all pinouts and timing diagrams Updated block diagram and functional description Updated application interfaces Added Interrupt descriptions *E 131851 TGE 12/15/03 Changed Static Discharge Voltage (Digital) Specification of Section *F 241471 ZTK See ECN Removed Static Discharge Voltage (Digital) Specification of Section footnote Updated REG_DATA_RATE (0x04), 111—Not Valid Swapped bit field descriptions of REG_CONFIG Corrected Logic Block Diagram – CYWUSB6932/CYWUSB6934 and Figure 8 Minor edits throughout *G 284810 ZTK See ECN Removed SOIC package option Updated ordering information section Added Table 1 Internal PA Output Power Step Table Added tSTABLE2 Parameter to Table 40 and Figure 16 Corrected Figure 18 caption Corrected Figure 8 to show QFN matching network Removed Addr 0x01 and 0x02 - unused Updated Figure 10 Updated Spurious Emissions parameters *H 335758 TGE Description of Change ec om m en d ed fo rN ew D es ig ns New data sheet. Corrected Figure 8 - swap RFIN / RFOUT Corrected REG_CONTROL - bit 1 description Added Table 36 footnote 14 - Max. value measured with Vcc = 3.2 V TGE See ECN Added receive ready parameter to Table 39 DPT 09/29/09 Added 48QFN package diagram (Sawn) Saw Marketing part number in ordering information. Updated package diagram for spec 51-85152 Removed inactive parts from Ordering Information. Updated Packaging Information ot R See ECN 391306 2770967 *K 2897889 TGE 03/23/10 *L 3048368 HEMP 10/05/2010 Sunset review; no technical updates. Format updates per template. *M 4135696 DEJO 09/25/2013 Updated Package Diagram: spec 001-53698 – Changed revision from *A to *B. N *I *J Updated in new template. Completing Sunset Review. Document Number: 38-16007 Rev. *M Page 38 of 39 CYWUSB6932 CYWUSB6934 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive cypress.com/go/automotive Clocks & Buffers Interface Lighting & Power Control psoc.cypress.com/solutions cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP cypress.com/go/interface Cypress Developer Community cypress.com/go/powerpsoc Community | Forums | Blogs | Video | Training cypress.com/go/plc Memory Technical Support cypress.com/go/memory cypress.com/go/support cypress.com/go/psoc cypress.com/go/touch USB Controllers es ig Touch Sensing ns PSoC cypress.com/go/USB cypress.com/go/wireless N ot R ec om m en d ed fo rN ew D Wireless/RF © Cypress Semiconductor Corporation, 2003-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-16007 Rev. *M Revised September 25, 2013 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 39 of 39