CYPRESS CYWUSB6932_05

CYWUSB6932
CYWUSB6934
WirelessUSB™ LS 2.4-GHz DSSS Radio SoC
1.0
Features
2.0
• 2.4-GHz radio transceiver
• Operates in the unlicensed Industrial, Scientific, and
Medical (ISM) band (2.4 GHz–2.483 GHz)
• -90-dBm receive sensitivity
• Up to 0 dBm output power
• Range of up to 10 meters or more
• Data throughput of up to 62.5 kbits/sec
• Highly integrated low cost, minimal number of external
components required
• Dual DSSS reconfigurable baseband correlators
• SPI microcontroller interface (up to 2-MHz data rate)
Functional Description
The CYWUSB6932/CYWUSB6934 Integrated Circuits (ICs)
are highly integrated 2.4-GHz Direct Sequence Spread
Spectrum (DSSS) Radio System-on-Chip (SoC) ICs. From the
Serial Peripheral Interface (SPI) to the antenna, these ICs are
single-chip 2.4-GHz DSSS Gaussian Frequency Shift Keying
(GFSK) baseband modems that connect directly to a microcontroller via simple serial interface.
The CYWUSB6932 transmit-only IC and the CYWUSB6934
transceiver IC are available in a small footprint 48-pin QFN
package.
3.0
Applications
• PC Human Interface Devices (HIDs)
• 13-MHz ± 50-ppm input clock operation
— Mice
• Low standby current < 1 µA
— Keyboards
• Integrated 30-bit Manufacturing ID
— Joysticks
• Peripheral Gaming Devices
• Operating voltage from 2.7V to 3.6V
• Operating temperature from 0° to 70°C
— Game Controllers
• Offered in a small footprint 48 Quad Flat Pack No Leads
(QFN)
— Console Keyboards
• General
— Presenter Tools
— Remote Controls
— Consumer Electronics
— Barcode Scanners
— POS Peripherals
— Toys
DIOVAL
DIO
IRQ
SS
SCK
MISO
MOSI
Digital
SERDES
A
DSSS
Baseband
A
SERDES
B
DSSS
Baseband
B
RESET
PD
GFSK
Modulator
RFOUT
GFSK
Demodulator
RFIN
Synthesizer
X13IN
X13
X13OUT
CY WUSB6934Only
Figure 3-1. CYWUSB6932/CYWUSB6934 Simplified Block Diagram
Cypress Semiconductor Corporation
Document 38-16007 Rev. *I
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised August 3, 2005
CYWUSB6932
CYWUSB6934
3.1
Applications Support
The CYWUSB6932/CYWUSB6934 ICs are supported by the
CY3632 WirelessUSB Development Kit. The development kit
provides all of the materials and documents needed to cut the
cord on wired applications including two radio modules that
connect directly to two prototyping platform boards, comprehensive WirelessUSB protocol code examples a WirelessUSB
Listener tool and all of the associated schematics, gerber files
and bill of materials.
The CY4632 WirelessUSB LS Keyboard Mouse Reference
Design provides a production-worthy example of a wireless
mouse and keyboard system.
The CY3633 WirelessUSB LS Gaming Development Kit
provides support for designing a wireless gamepad for the
major gaming consoles and is offered as an accessory to the
CY3632 WirelessUSB.
4.0
Functional Overview
The CYWUSB6932/CYWUSB6934 ICs provide a complete
WirelessUSB LS SPI to antenna radio modem. The SoC is
designed to implement wireless devices operating in the
worldwide 2.4-GHz Industrial, Scientific, and Medical (ISM)
frequency band (2.400 GHz–2.4835 GHz). It is intended for
systems compliant with world-wide regulations covered by
ETSI EN 301 489-1 V1.4.1, ETSI EN 300 328-1 V1.3.1
(European Countries); FCC CFR 47 Part 15 (USA and
Industry Canada) and ARIB STD-T66 (Japan).
The CYWUSB6934 IC contains a 2.4-GHz radio transceiver, a
GFSK modem and a dual DSSS reconfigurable baseband.
The CYWUSB6932 IC contains a 2.4-GHz radio transmit-only,
a GFSK modem and a DSSS baseband. The radio and
baseband are both code- and frequency-agile. Forty-nine
spreading codes selected for optimal performance (Gold
codes) are supported across 78 1-MHz channels yielding a
theoretical spectral capacity of 3822 channels. Both ICs
support a range of up to 10 meters or more.
4.1
The receiver and transmitter are a single-conversion low-Intermediate Frequency (low-IF) architecture with fully integrated
IF channel matched filters to achieve high performance in the
presence of interference. An integrated Power Amplifier (PA)
provides an output power control range of 30 dB in seven
steps.
Table 4-1. Internal PA Output Power Step Table
Typical Output Power (dBm)
7
0
6
–2.4
5
–5.6
4
–9.7
3
–16.4
2
–20.8
1
–24.8
0
–29.0
Document 38-16007 Rev. *I
4.2
GFSK Modem
The transmitter uses a DSP-based vector modulator to
convert the 1-MHz chips to an accurate GFSK carrier.
The receiver uses a fully integrated Frequency Modulator (FM)
detector with automatic data slicer to demodulate the GFSK
signal.
4.3
Dual DSSS Baseband
Data is converted to DSSS chips by a digital spreader.
De-spreading is performed by an oversampled correlator. The
DSSS baseband cancels spurious noise and assembles
properly correlated data bytes.
The DSSS baseband has three operating modes: 64 chips/bit
Single Channel, 32 chips/bit Single Channel, and 32 chips/bit
Single Channel Dual Data Rate (DDR).
4.3.1
64 Chips/Bit Single Channel
The baseband supports a single data stream operating at
15.625 kbits/sec. The advantage of selecting this mode is its
ability to tolerate a noisy environment. This is because the
15.625 kbits/sec data stream utilizes the longest PN Code
resulting in the highest probability for recovering packets over
the air. This mode can also be selected for systems requiring
data transmissions over longer ranges.
4.3.2
32 Chips/Bit Single Channel
The baseband supports a single data stream operating at
31.25 kbits/sec.
4.3.3
2.4-GHz Radio
PA Setting
Both the receiver and transmitter integrated Voltage
Controlled Oscillator (VCO) and synthesizer have the agility to
cover the complete 2.4-GHz GFSK radio transmitter ISM
band. The synthesizer provides the frequency-hopping local
oscillator for the transmitter and receiver. The VCO loop filter
is also integrated on-chip.
32 Chips/Bit Single Channel Dual Data Rate (DDR)
The baseband spreads bits in pairs and supports a single data
stream operating at 62.5 kbits/sec.
4.4
Serializer/Deserializer (SERDES)
The CYWUSB6934 IC has a data Serializer/Deserializer
(SERDES), which provides byte-level framing of transmit and
receive data. Bytes for transmission are loaded into the
SERDES and receive bytes are read from the SERDES via the
SPI interface. The SERDES provides double buffering of
transmit and receive data. While one byte is being transmitted
by the radio the next byte can be written to the SERDES data
register insuring there are no breaks in transmitted data.
After a receive byte has been received it is loaded into the
SERDES data register and can be read at any time until the
next byte is received, at which time the old contents of the
SERDES data register will be overwritten. The CYWUSB6932
IC only has a data Serializer.
Page 2 of 30
CYWUSB6932
CYWUSB6934
4.5
Application Interfaces
Both ICs have a fully synchronous SPI slave interface for
connectivity to the application MCU. Configuration and
byte-oriented data transfer can be performed over this
interface. An interrupt is provided to trigger real time events.
An optional SERDES Bypass mode (DIO) is provided for applications that require a synchronous serial bit-oriented data
path. This interface is for data only.
4.6
Clocking and Power Management
A 13-MHz crystal (±50 ppm or better) is directly connected to
X13IN and X13 without the need for external capacitors. Both
ICs have a programmable trim capability for adjusting the
on-chip load capacitance supplied to the crystal. The Radio
Frequency (RF) circuitry has on-chip decoupling capacitors.
Both devices are powered from a 2.7V to 3.6V DC supply. Both
devices can be shutdown to a fully static state using the PD
pin.
Below are the requirements for the crystal to be directly
connected to X13IN and X13:
• Nominal Frequency: 13 MHz
• Operating Mode: Fundamental Mode
• Resonance Mode: Parallel Resonant
• Frequency Stability: ± 50 ppm
• Series Resistance: ≤ 100 ohms
• Load Capacitance: 10 pF
• Drive Level: 10 uW–100 uW
4.7
Receive Signal Strength Indicator (RSSI)
The RSSI register (Reg 0x22) (applies only to the
CYWUSB6934 IC) returns the relative signal strength of the
ON-channel signal power and can be used to:
1. Determine the connection quality
2. Determine the value of the noise floor
3. Check for a quiet channel before transmitting.
The internal RSSI voltage is sampled through a 5-bit
analog-to-digital converter (ADC). A state machine controls
the conversion process. Under normal conditions, the RSSI
state machine initiates a conversion when an ON-channel
carrier is detected and remains above the noise floor for over
50 µs. The conversion produces a 5-bit value in the RSSI
register (Reg 0x22, bits 4:0) along with a valid bit, RSSI
register (Reg 0x22, bit 5). The state machine then remains in
HALT mode and does not reset for a new conversion until the
receive mode is toggled off and on. Once a connection has
been established, the RSSI register can be read to determine
the relative connection quality of the channel. A RSSI register
value lower than 10 indicates that the received signal strength
is low, a value greater than 28 indicates a strong signal level.
To check for a quiet channel before transmitting, first set up
receive mode properly and read the RSSI register (Reg 0x22).
If the valid bit is zero, then force the Carrier Detect register
Document 38-16007 Rev. *I
(Reg 0x2F, bit 7=1) to initiate an ADC conversion. Then, wait
greater than 50 µs and read the RSSI register again. Next,
clear the Carrier Detect Register (Reg 0x2F, bit 7=0) and turn
the receiver OFF. Measuring the noise floor of a quiet channel
is inherently a 'noisy' process so, for best results, this
procedure should be repeated several times (~20) to compute
an average noise floor level. A RSSI register value of 0-10
indicates a channel that is relatively quiet. A RSSI register
value greater than 10 indicates the channel is probably being
used. A RSSI register value greater than 28 indicates the
presence of a strong signal.
5.0
5.1
Application Interfaces
SPI Interface
The CYWUSB6932/CYWUSB6934 ICs have a four-wire SPI
communication interface between an application MCU and
one or more slave devices. The SPI interface supports
single-byte and multi-byte serial transfers. The four-wire SPI
communications interface consists of Master Out-Slave In
(MOSI), Master In-Slave Out (MISO), Serial Clock (SCK), and
Slave Select (SS).
The SPI receives SCK from an application MCU on the SCK
pin. Data from the application MCU is shifted in on the MOSI
pin. Data to the application MCU is shifted out on the MISO
pin. The active-low Slave Select (SS) pin must be asserted to
initiate a SPI transfer.
The application MCU can initiate a SPI data transfer via a
multi-byte transaction. The first byte is the Command/Address
byte, and the following bytes are the data bytes as shown in
Figure 5-1 through Figure 5-4. The SS signal should not be
deasserted between bytes. The SPI communications is as
follows:
• Command Direction (bit 7) = “0” Enables SPI read transaction. A “1” enables SPI write transactions.
• Command Increment (bit 6) = “1” Enables SPI auto address
increment. When set, the address field automatically increments at the end of each data byte in a burst access, otherwise the same address is accessed.
• Six bits of address.
• Eight bits of data.
The SPI communications interface has a burst mechanism,
where the command byte can be followed by as many data
bytes as desired. A burst transaction is terminated by
deasserting the slave select (SS = 1). For burst read transactions, the application MCU must abide by the timing shown in
Figure 12-2.
The SPI communications interface single read and burst read
sequences are shown in Figure 5-2 and Figure 5-3, respectively.
The SPI communications interface single write and burst write
sequences are shown in Figure 5-4 and Figure 5-5, respectively.
Page 3 of 30
CYWUSB6932
CYWUSB6934
Byte 1
Byte 1+N
Bit #
7
6
[5:0]
[7:0]
Bit Name
DIR
INC
Address
Data
Figure 5-1. SPI Transaction Format
SCK
SS
cm d
MOSI
D IR
0
IN C
0
addr
A5
A4
A3
A2
A1
A0
d a ta t o m c u
M IS O
D7
D5
D6
D4
D3
D2
D1
D0
Figure 5-2. SPI Single Read Sequence
SCK
SS
cm d
MOSI
D IR
0
addr
IN C
1
A5
A4
A3
A2
A1
A0
d a ta to m c u
M IS O
D7
D6
D5
D4
D3
D2
d a ta to m c u
1
D1
D0
D7
D6
D5
D4
D3
1+N
D2
D1
D0
Figure 5-3. SPI Burst Read Sequence
SCK
SS
cm d
M O SI
DIR
1
INC
0
addr
A5
A4
A3
A2
data from m cu
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
M ISO
Figure 5-4. SPI Single Write Sequence
SCK
SS
cm d
MOSI
D IR
1
a dd r
d ata fro m m cu
IN C
1
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
da ta from m cu
1
D1
D0
D7
D6
D5
D4
D3
D2
1+N
D1
D0
M IS O
Figure 5-5. SPI Burst Write Sequence
Document 38-16007 Rev. *I
Page 4 of 30
CYWUSB6932
CYWUSB6934
5.2
DIO Interface
5.3.1
5.3
Wake Interrupt
When the PD pin is low, the oscillator is stopped. After PD is
deasserted, the oscillator takes time to start, and until it has
done so, it is not safe to use the SPI interface. The wake
interrupt indicates that the oscillator has started, and that the
device is ready to receive SPI transfers.
The DIO communications interface is an optional SERDES
bypass data-only transfer interface. In receive mode, DIO and
DIOVAL are valid after the falling edge of IRQ, which clocks
the data as shown in Figure 5-6. In transmit mode, DIO and
DIOVAL are sampled on the falling edge of the IRQ, which
clocks the data as shown in Figure 5-7. The application MCU
samples the DIO and DIOVAL on the rising edge of IRQ.
The wake interrupt is enabled by setting bit 0 of the Wake
Enable register (Reg 0x1C, bit 0=1). Whether or not a wake
interrupt is pending is indicated by the state of bit 0 of the Wake
Status register (Reg 0x1D, bit 0). Reading the Wake Status
register (Reg 0x1D) clears the interrupt.
Interrupts
The CYWUSB6932/CYWUSB6934 ICs feature three sets of
interrupts: transmit, receive (CYWUSB6934 only), and a wake
interrupt. These interrupts all share a single pin (IRQ), but can
be independently enabled/disabled. In transmit mode, all
receive interrupts are automatically disabled, and in receive
mode all transmit interrupts are automatically disabled.
However, the contents of the enable registers are preserved
when switching between transmit and receive modes.
5.3.2
Transmit Interrupts
Four interrupts are provided to flag the occurrence of transmit
events. The interrupts are enabled by writing to the Transmit
Interrupt Enable register (Reg 0x0D), and their status may be
determined by reading the Transmit Interrupt Status register
(Reg 0x0E). If more than 1 interrupt is enabled, it is necessary
to read the Transmit Interrupt Status register (Reg 0x0E) to
determine which event caused the IRQ pin to assert.
Interrupts are enabled and the status read through 6 registers:
Receive Interrupt Enable (Reg 0x07), Receive Interrupt Status
(Reg 0x08), Transmit Interrupt Enable (Reg 0x0D), Transmit
Interrupt Status (Reg 0x0E), Wake Enable (Reg 0x1C), Wake
Status (Reg 0x1D).
The function and operation of these interrupts are described in
detail in Section 7.0.
5.3.3
If more than 1 interrupt is enabled at any time, it is necessary
to read the relevant interrupt status register to determine which
event caused the IRQ pin to assert. Even when a given
interrupt source is disabled, the status of the condition that
would otherwise cause an interrupt can be determined by
reading the appropriate interrupt status register. It is therefore
possible to use the devices without making use of the IRQ pin
at all. Firmware can poll the interrupt status register(s) to wait
for an event, rather than using the IRQ pin.
Receive Interrupts
Eight interrupts are provided to flag the occurrence of receive
events, four each for SERDES A and B. In 64 chips/bit and 32
chips/bit DDR modes, only the SERDES A interrupts are
available, and the SERDES B interrupts will never trigger,
even if enabled. The interrupts are enabled by writing to the
Receive Interrupt Enable register (Reg 0x07), and their status
may be determined by reading the Receive Interrupt Status
register (Reg 0x08). If more than one interrupt is enabled, it is
necessary to read the Receive Interrupt Status register (Reg
0x08) to determine which event caused the IRQ pin to assert.
The polarity of all interrupts can be set by writing to the Configuration register (Reg 0x05), and it is possible to configure the
IRQ pin to be open drain (if active low) or open source (if active
high).
The function and operation of these interrupts are described in
detail in Section 7.0.
IRQ
DIOVAL
v0
v1
v2
v3
v4
v5
v6
v7
v8
v9
v10
v11
v12
v13
v14
v...
d10
d11
d12
d13
d14
d...
data to mcu
DIO
d0
d1
d2
d3
d4
d5
d6
d7
d8
d9
Figure 5-6. DIO Receive Sequence
IRQ
DIOVAL
v0
v1
v2
v3
v4
v5
v6
v7
v8
v9
v10
v11
v12
v13
v14
v...
d11
d12
d13
d14
d...
data from mcu
DIO
d0
d1
d2
d3
d4
d5
d6
d7
d8
d9
d10
Figure 5-7. DIO Transmit Sequence
Document 38-16007 Rev. *I
Page 5 of 30
CYWUSB6932
CYWUSB6934
6.0
Application Examples
LDO/
DC2DC
3.3 V
0.1µF
+
Battery -
PCB Trace
Inverted “F”
Antenna
(PIFA)
Vcc
Vcc
RESET
Optical
Mouse
Sensor
10pF
RFOUT
PD
WUSB LS
IRQ
Application MCU
13MHz
Crystal
SPI
Buttons
4
Figure 6-1. CYWUSB6932 Transmit-Only Battery-Powered Device
PCB Trace Antenna
3.3V
0.1µF
2.0 pF
LDO
1µF
2.0 pF
5V
0.1µF 4.7µF
1.2 pF
RESET
3.3 nH
27 pF
RFIN
PD
RFOUT
IRQ
2.2 nH
WirelessUSB LS
2.2K SCK
2.2K MOSI
Vcc
Cypress
enCoRe
USB MCU
USB I/F
1.3K
D+/D2
MISO
SS
13MHz
Crystal
Figure 6-2. CYWUSB6934 USB Bridge Transceiver
Document 38-16007 Rev. *I
Page 6 of 30
CYWUSB6932
CYWUSB6934
7.0
Register Descriptions
Table 7-1 displays the list of registers inside the
CYWUSB6932/CYWUSB6934 ICs that are addressable
through the SPI interface. All registers are read and writable,
except where noted.
Table 7-1. CYWUSB6932/CYWUSB6934 Register Map[2]
Address
Page
Default
Access
Revision ID
Register Name
REG_ID
Mnemonic
0x00
8
0x07
RO
Control
REG_CONTROL
0x03
8
0x00
RW
Data Rate
REG_DATA_RATE
0x04
9
0x00
RW
Configuration
REG_CONFIG
0x05
9
0x01
RW
SERDES Control
REG_SERDES_CTL
0x06
10
0x03
RW
Receive SERDES Interrupt Enable REG_RX_INT_EN
0x07[1]
11
0x00
RW
Receive SERDES Interrupt Status
REG_RX_INT_STAT
0x08[1]
12
0x00
RO
Receive SERDES Data A
REG_RX_DATA_A
0x09[1]
13
0x00
RO
Receive SERDES Valid A
REG_RX_VALID_A
0x0A[1]
13
0x00
RO
Receive SERDES Data B
REG_RX_DATA_B
0x0B[1]
13
0x00
RO
Receive SERDES Valid B
REG_RX_VALID_B
0x0C[1]
13
0x00
RO
Transmit SERDES Interrupt Enable REG_TX_INT_EN
0x0D
14
0x00
RW
Transmit SERDES Interrupt Status REG_TX_INT_STAT
0x0E
15
0x00
RO
Transmit SERDES Data
REG_TX_DATA
0x0F
16
0x00
RW
Transmit SERDES Valid
REG_TX_VALID
0x10
16
0x00
PN Code
REG_PN_CODE
0x18–0x11
16
0x1E8B6A3DE0E9B222
RW
RW
Threshold Low
REG_THRESHOLD_L
0x19[1]
17
0x08
RW
Threshold High
REG_THRESHOLD_H
0x1A[1]
17
0x38
RW
Wake Enable
REG_WAKE_EN
0x1C
17
0x00
RW
Wake Status
REG_WAKE_STAT
0x1D
18
0x01
RO
Analog Control
REG_ANALOG_CTL
0x20
18
0x04
RW
Channel
REG_CHANNEL
Receive Signal Strength Indicator
REG_RSSI
0x21
19
0x00
RW
0x22[1]
19
0x00
RO
PA Bias
REG_PA
0x23
19
0x00
RW
Crystal Adjust
REG_CRYSTAL_ADJ
0x24
20
0x00
RW
VCO Calibration
REG_VCO_CAL
0x26
20
0x00
RW
Reg Power Control
REG_PWR_CTL
0x2E
20
0x00
RW
Carrier Detect
REG_CARRIER_DETECT
0x2F
21
0x00
RW
Clock Manual
REG_CLOCK_MANUAL
0x32
21
0x00
RW
Clock Enable
REG_CLOCK_ENABLE
0x33
21
0x00
RW
Synthesizer Lock Count
REG_SYN_LOCK_CNT
0x38
21
0x64
RW
Manufacturing ID
REG_MID
0x3C–0x3F
21
–
RO
Notes:
1. Register not applicable to CYWUSB6932.
2. All registers are accessed Little Endian.
Document 38-16007 Rev. *I
Page 7 of 30
CYWUSB6932
CYWUSB6934
Figure 7-1. Revision ID Register
Addr: 0x00
7
REG_ID
6
5
4
Default: 0x07
3
2
Silicon ID
1
0
Product ID
Bit
Name
Description
7:4
Silicon ID
These are the Silicon ID revision bits. 0000 = Rev A, 0001 = Rev B, etc. These bits are read-only.
3:0
Product ID
These are the Product ID revision bits. Fixed at value 0111. These bits are read-only.
Figure 7-2. Control
Addr: 0x03
REG_CONTROL
Default: 0x00
7
6
5
4
3
2
1
0
RX
Enable
TX
Enable
PN Code
Select
Bypass Internal
Syn Lock Signal
Auto Internal
PA
Disable
Internal PA
Enable
Reserved
Reserved
Bit Name
Description
7
RX Enable
The Receive Enable bit is used to place the IC in receive mode.
1 = Receive Enabled
0 = Receive Disabled
6
TX Enable
The Transmit Enable bit is used to place the IC in transmit mode.
1 = Transmit Enabled
0 = Transmit Disabled
5
PN Code Select The Pseudo-Noise Code Select bit selects between the upper or lower half of the 64 chips/bit PN code.
1 = 32 Most Significant Bits of PN code are used
0 = 32 Least Significant Bits of PN code are used
This bit applies only when the Code Width bit is set to 32 chips/bit PN codes (Reg 0x04, bit 2=1).
4
Bypass Internal This bit controls whether the state machine waits for the internal Syn Lock Signal before waiting for the amount of time
Syn Lock Signal specified in the Syn Lock Count register (Reg 0x38), in units of 2 µs. If the internal Syn Lock Signal is used then set Syn
Lock Count to 25 to provide additional assurance that the synthesizer has settled.
1 = Bypass the Internal Syn Lock Signal and wait the amount of time in Syn Lock Count register (Reg 0x38)
0 = Wait for the Syn Lock Signal and then wait the amount of time specified in Syn Lock Count register (Reg 0x38)
It is recommended that the application MCU sets this bit to 1 in order to guarantee a consistent settle time for the
synthesizer.
3
Auto Internal PA The Auto Internal PA Disable bit is used to determine the method of controlling the Internal Power Amplifier. The two
Disable
options are automatic control by the baseband or by firmware through register writes. For external PA usage, please
see the description of the REG_ANALOG_CTL register (Reg 0x20).
1 = Register controlled Internal PA Enable
0 = Auto controlled Internal PA Enable
When this bit is set to 1, the enabled state of the Internal PA is directly controlled by bit Internal PA Enable (Reg 0x03,
bit 2). It is recommended that this bit is set to 0, leaving the PA control to the baseband.
2
Internal PA
Enable
The Internal PA Enable bit is used to enable or disable the Internal Power Amplifier.
1 = Internal Power Amplifier Enabled
0 = Internal Power Amplifier Disabled
This bit only applies when the Auto Internal PA Disable bit is selected (Reg 0x03, bit 3=1), otherwise this bit is don’t care.
1
Reserved
This bit is reserved and should be written with a zero.
0
Reserved
This bit is reserved and should be written with a zero.
Document 38-16007 Rev. *I
Page 8 of 30
CYWUSB6932
CYWUSB6934
Addr: 0x04
7
REG_DATA_RATE
6
5
4
3
Reserved
Default: 0x00
2
1
0
Code Width
Data Rate
Sample Rate
Figure 7-3. Data Rate
Bit
Name
Description
7:3
Reserved
These bits are reserved and should be written with zeroes.
2[3]
Code Width
The Code Width bit is used to select between 32 chips/bit and 64 chips/bit PN codes.
1 = 32 chips/bit PN codes
0 = 64 chips/bit PN codes
The number of chips/bit used impacts a number of factors such as data throughput, range and robustness to interference. By choosing a 32 chips/bit PN-code, the data throughput can be doubled or even quadrupled (when double
data rate is set). A 64 chips/bit PN code offers improved range over its 32 chips/bit counterpart as well as more
robustness to interference. By selecting to use a 32 chips/bit PN code a number of other register bits are impacted
and need to be addressed. These are PN Code Select (Reg 0x03, bit 5), Data Rate (Reg 0x04, bit 1), and Sample
Rate (Reg 0x04, bit 0).
1[3]
Data Rate
The Data Rate bit allows the user to select Double Data Rate mode of operation which delivers a raw data rate of
62.5 kbits/sec.
1 = Double Data Rate - 2 bits per PN code (No odd bit transmissions)
0 = Normal Data Rate - 1 bit per PN code
This bit is applicable only when using 32 chips/bit PN codes which can be selected by setting the Code Width bit (Reg
0x04, bit 2=1). When using Double Data Rate, the raw data throughput is 62.5 kbits/sec because every 32 chips/bit
PN code is interpreted as 2 bits of data. When using this mode a single 64 chips/bit PN code is placed in the PN code
register. This 64 chips/bit PN code is then split into two and used by the baseband to offer the Double Data Rate
capability. When using Normal Data Rate, the raw data throughput is 32kbits/sec. Additionally, Normal Data Rate
enables the user to potentially correlate data using two differing 32 chips/bit PN codes.
0[3]
Sample
Rate
The Sample Rate bit allows the use of the 12x sampling when using 32 chips/bit PN codes and Normal Data Rate.
1 = 12x Oversampling
0 = 6x Oversampling
Using 12x oversampling improves the correlators receive sensitivity. When using 64 chips/bit PN codes or Double
Data Rate this bit is don’t care. The only time when 12x oversampling can be selected is when a 32 chips/bit PN code
is being used with Normal Data Rate.
Figure 7-4. Configuration
Addr: 0x05
7
REG_CONFIG
6
5
4
3
Default: 0x01
2
1
Reserved
Bit
Name
7:2
Reserved
These bits are reserved and should be written with zeroes.
1:0
IRQ Pin Select
The Interrupt Request Pin Select bits are used to determine the drive method of the IRQ pin.
0
IRQ Pin Select
Description
11 = Open Source (IRQ asserted = 1, IRQ deasserted = Hi-Z)
10 = Open Drain (IRQ asserted = 0, IRQ deasserted = Hi-Z)
01 = CMOS (IRQ asserted = 1, IRQ deasserted = 0)
00 = CMOS Inverted (IRQ asserted = 0, IRQ deasserted = 1)
Note:
3. The following Reg 0x04, bits 2:0 values are not valid:
• 001 – Not Valid
• 010 – Not Valid
• 011 – Not Valid
• 111 – Not Valid.
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Addr: 0x06
7
REG_SERDES_CTL
6
5
Reserved
4
3
SERDES
Enable
Default: 0x03
2
1
0
EOF Length
Figure 7-5. SERDES Control
Bit
Name
Description
7:4
Reserved
These bits are reserved and should be written with zeroes.
3
SERDES Enable
The SERDES Enable bit is used to switch between bit-serial mode and SERDES mode.
1 = SERDES enabled.
0 = SERDES disabled, bit-serial mode enabled.
When the SERDES is enabled data can be written to and read from the IC one byte at a time, through the use of the
SERDES Data registers. The bit-serial mode requires bits to be written one bit at a time through the use of the
DIO/DIOVAL pins, refer to section 3.2. It is recommended that SERDES mode be used to avoid the need to manage
the timing required by the bit-serial mode.
2:0
EOF Length
The End of Frame Length bits are used to set the number of sequential bit times for an inter-frame gap without valid
data before an EOF event will be generated. When in receive mode and a valid bit has been received the EOF event
can then be identified by the number of bit times that expire without correlating any new data. The EOF event causes
data to be moved to the proper SERDES Data Register and can also be used to generate interrupts. If 0 is the EOF
length, an EOF condition will occur at the first invalid bit after a valid reception.
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Addr: 0x07
REG_RX_INT_EN
Default: 0x00
7
6
5
4
3
2
1
0
Underflow B
Overflow B
EOF B
Full B
Underflow A
Overflow A
EOF A
Full A
Figure 7-6. Receive SERDES Interrupt Enable
Bit
Name
Description
7
Underflow B
The Underflow B bit is used to enable the interrupt associated with an underflow condition with the Receive SERDES
Data B register (Reg 0x0B)
1 = Underflow B interrupt enabled for Receive SERDES Data B
0 = Underflow B interrupt disabled for Receive SERDES Data B
An underflow condition occurs when attempting to read the Receive SERDES Data B register (Reg 0x0B) when it is
empty.
6
Overflow B
The Overflow B bit is used to enable the interrupt associated with an overflow condition with the Receive SERDES Data
B register (Reg 0x0B)
1 = Overflow B interrupt enabled for Receive SERDES Data B
0 = Overflow B interrupt disabled for Receive SERDES Data B
An overflow condition occurs when new received data is written into the Receive SERDES Data B register (Reg 0x0B)
before the prior data is read out.
5
EOF B
The End of Frame B bit is used to enable the interrupt associated with the Channel B Receiver EOF condition.
1 = EOF B interrupt enabled for Channel B Receiver.
0 = EOF B interrupt disabled for Channel B Receiver.
The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit has been
detected, and then the number of invalid bits in the frame exceeds the number in the EOF length field. If 0 is the EOF
length, and EOF condition will occur at the first invalid bit after a valid reception. This IRQ is cleared by reading the
receive status register
4
Full B
The Full B bit is used to enable the interrupt associated with the Receive SERDES Data B register (Reg 0x0B) having
data placed in it.
1 = Full B interrupt enabled for Receive SERDES Data B
0 = Full B interrupt disabled for Receive SERDES Data B
A Full B condition occurs when data is transferred from the Channel B Receiver into the Receive SERDES Data B
register (Reg 0x0B). This could occur when a complete byte is received or when an EOF event occurs whether or not
a complete byte has been received.
3
Underflow A
The Underflow A bit is used to enable the interrupt associated with an underflow condition with the Receive SERDES
Data A register (Reg 0x09)
1 = Underflow A interrupt enabled for Receive SERDES Data A
0 = Underflow A interrupt disabled for Receive SERDES Data A
An underflow condition occurs when attempting to read the Receive SERDES Data A register (Reg 0x09) when it is
empty.
2
Overflow A
The Overflow A bit is used to enable the interrupt associated with an overflow condition with the Receive SERDES Data
A register (0x09)
1 = Overflow A interrupt enabled for Receive SERDES Data A
0 = Overflow A interrupt disabled for Receive SERDES Data A
An overflow condition occurs when new receive data is written into the Receive SERDES Data A register (Reg 0x09)
before the prior data is read out.
1
EOF A
The End of Frame A bit is used to enable the interrupt associated with an End of Frame condition with the Channel A
Receiver.
1 = EOF A interrupt enabled for Channel A Receiver.
0 = EOF A interrupt disabled for Channel A Receiver.
The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit has been
detected, and then the number of invalid bits in a frame exceeds the number in the EOF length field. If 0 is the EOF
length, an EOF condition will occur at the first invalid bit after a valid reception. This IRQ is cleared by reading the receive
status register.
0
Full A
The Full A bit is used to enable the interrupt associated with the Receive SERDES Data A register (0x09) having data
written into it.
1 = Full A interrupt enabled for Receive SERDES Data A
0 = Full A interrupt disabled for Receive SERDES Data A
A Full A condition occurs when data is transferred from the Channel A Receiver into the Receive SERDES Data A
register (Reg 0x09). This could occur when a complete byte is received or when an EOF event occurs whether or not
a complete byte has been received.
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Addr: 0x08
REG_RX_INT_STAT
Default: 0x00
7
6
5
4
3
2
1
0
Valid B
Flow Violation
B
EOF B
Full B
Valid A
Flow Violation
A
EOF A
Full A
Figure 7-7. Receive SERDES Interrupt Status[4]
Bit
Name
Description
7
Valid B
The Valid B bit is true when all the bits in the Receive SERDES Data B register (Reg 0x0B) are valid.
1 = All bits are valid for Receive SERDES Data B.
0 = Not all bits are valid for Receive SERDES Data B.
When data is written into the Receive SERDES Data B register (Reg 0x0B) this bit is set if all of the bits within the byte
that has been written are valid. This bit cannot generate an interrupt.
6
Flow Violation
B
The Flow Violation B bit is used to signal whether an overflow or underflow condition has occurred for the Receive
SERDES Data B register (Reg 0x0B).
1 = Overflow/underflow interrupt pending for Receive SERDES Data B.
0 = No overflow/underflow interrupt pending for Receive SERDES Data B.
Overflow conditions occur when the radio loads new data into the Receive SERDES Data B register (Reg 0x0B) before
the prior data has been read. Underflow conditions occur when trying to read the Receive SERDES Data B register
(Reg 0x0B) when the register is empty. This bit is cleared by reading the Receive Interrupt Status register (Reg 0x08)
5
EOF B
The End of Frame B bit is used to signal whether an EOF event has occurred on the Channel B receive.
1 = EOF interrupt pending for Channel B.
0 = No EOF interrupt pending for Channel B.
An EOF condition occurs for the Channel B Receiver when receive has begun and then the number of bit times
specified in the SERDES Control register (Reg 0x06) elapse without any valid bits being received. This bit is cleared
by reading the Receive Interrupt Status register (Reg 0x08)
4
Full B
The Full B bit is used to signal when the Receive SERDES Data B register (Reg 0x0B) is filled with data.
1 = Receive SERDES Data B full interrupt pending.
0 = No Receive SERDES Data B full interrupt pending.
A Full B condition occurs when data is transferred from the Channel B Receiver into the Receive SERDES Data B
register (Reg 0x0B). This could occur when a complete byte is received or when an EOF event occurs whether or not
a complete byte has been received.
3
Valid A
The Valid A bit is true when all of the bits in the Receive SERDES Data A Register (Reg 0x09) are valid.
1 = All bits are valid for Receive SERDES Data A.
0 = Not all bits are valid for Receive SERDES Data A.
When data is written into the Receive SERDES Data A register (Reg 0x09) this bit is set if all of the bits within the byte
that has been written are valid. This bit cannot generate an interrupt.
2
Flow Violation
A
The Flow Violation A bit is used to signal whether an overflow or underflow condition has occurred for the Receive
SERDES Data A register (Reg 0x09).
1 = Overflow/underflow interrupt pending for Receive SERDES Data A.
0 = No overflow/underflow interrupt pending for Receive SERDES Data A.
Overflow conditions occur when the radio loads new data into the Receive SERDES Data A register (Reg 0x09) before
the prior data has been read. Underflow conditions occur when trying to read the Receive SERDES Data A register
(Reg 0x09) when the register is empty. This bit is cleared by reading the Receive Interrupt Status register (Reg 0x08)
1
EOF A
The End of Frame A bit is used to signal whether an EOF event has occurred on the Channel A receive.
1 = EOF interrupt pending for Channel A.
0 = No EOF interrupt pending for Channel A.
An EOF condition occurs for the Channel A Receiver when receive has begun and then the number of bit times
specified in the SERDES Control register (0x06) elapse without any valid bits being received. This bit is cleared by
reading the Receive Interrupt Status register (Reg 0x08).
0
Full A
The Full A bit is used to signal when the Receive SERDES Data A register (Reg 0x09) is filled with data.
1 = Receive SERDES Data A full interrupt pending.
0 = No Receive SERDES Data A full interrupt pending.
A Full A condition occurs when data is transferred from the Channel A Receiver into the Receive SERDES Data A
Register (Reg 0x09). This could occur when a complete byte is received or when an EOF event occurs whether or not
a complete byte has been received.
Note:
4. All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be implemented without enabling IRQs. The
status bits are affected by TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the receive status will read 0 if the IC is not in receive mode. These
registers are read-only.
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Addr: 0x09
7
REG_RX_DATA_A
6
5
4
3
Default: 0x00
2
1
0
Data
Figure 7-8. Receive SERDES Data A
Bit
Name
Description
7:0
Data
Received Data for Channel A. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3,
followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
Addr: 0x0A
7
REG_RX_VALID_A
6
5
4
3
Default: 0x00
2
1
0
Valid
Figure 7-9. Receive SERDES Valid A
Bit
7:0
Name
Description
Valid
These bits indicate which of the bits in the Receive SERDES Data A register (Reg 0x09) are valid. A “1” indicates that the
corresponding data bit is valid for Channel A.
If the Valid Data bit is set in the Receive Interrupt Status register (Reg 0x08) all eight bits in the Receive SERDES Data A register
(Reg 0x0A) are valid. Therefore, it is not necessary to read the Receive SERDES Valid A register (Reg 0x0C). This register is
read-only.
Addr: 0x0B
7
REG_RX_DATA_B
6
5
4
3
Default: 0x00
2
1
0
Data
Figure 7-10. Receive SERDES Data B
Bit
Name
Description
7:0
Data
Received Data for Channel B. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3,
followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
Figure 7-11. Receive SERDES Valid B
Addr: 0x0C
7
REG_RX_VALID_B
6
5
4
3
Default: 0x00
2
1
0
Valid
Bit
Name
Description
7:0
Valid
These bits indicate which of the bits in the Receive SERDES Data B register (Reg 0x0B) are valid. A “1” indicates that the
corresponding data bit is valid for Channel B.
If the Valid Data bit is set in the Receive Interrupt Status register (0x08) all eight bits in the Receive SERDES Data B register
(Reg 0x0B) are valid. Therefore, it is not necessary to read the Receive SERDES Valid B register (Reg 0x0C). This register is
read-only.
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Addr: 0x0D
7
REG_TX_INT_EN
6
5
Reserved
4
Default: 0x00
3
2
1
0
Underflow
Overflow
Done
Empty
Figure 7-12. Transmit SERDES Interrupt Enable
Bit
Name
Description
7:4
Reserved
These bits are reserved and should be written with zeroes.
3
Underflow
The Underflow bit is used to enable the interrupt associated with an underflow condition associated with the Transmit
SERDES Data register (Reg 0x0F)
1 = Underflow interrupt enabled.
0 = Underflow interrupt disabled.
An underflow condition occurs when attempting to transmit while the Transmit SERDES Data register (Reg 0x0F) does not
have any data.
2
Overflow
The Overflow bit is used to enabled the interrupt associated with an overflow condition with the Transmit SERDES Data
register (0x0F).
1 = Overflow interrupt enabled.
0 = Overflow interrupt disabled.
An overflow condition occurs when attempting to write new data to the Transmit SERDES Data register (Reg 0x0F) before
the preceding data has been transferred to the transmit shift register.
1
Done
The Done bit is used to enable the interrupt that signals the end of the transmission of data.
1 = Done interrupt enabled.
0 = Done interrupt disabled.
The Done condition occurs when the Transmit SERDES Data register (Reg 0x0F) has transmitted all of its data and there
is no more data for it to transmit.
0
Empty
The Empty bit is used to enable the interrupt that signals when the Transmit SERDES register (Reg 0x0F) is empty.
1 = Empty interrupt enabled.
0 = Empty interrupt disabled.
The Empty condition occurs when the Transmit SERDES Data register (Reg 0x0F) is loaded into the transmit buffer and
it's safe to load the next byte
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Addr: 0x0E
7
REG_TX_INT_STAT
6
5
4
Reserved
Default: 0x00
3
2
1
0
Underflow
Overflow
Done
Empty
Figure 7-13. Transmit SERDES Interrupt Status[5]
Bit
Name
Description
7:4
Reserved
These bits are reserved. This register is read-only.
3
Underflow
The Underflow bit is used to signal when an underflow condition associated with the Transmit SERDES Data register (Reg
0x0F) has occurred.
1 = Underflow Interrupt pending.
0 = No Underflow Interrupt pending.
This IRQ will assert during an underflow condition to the Transmit SERDES Data register (Reg 0x0F). An underflow occurs
when the transmitter is ready to sample transmit data, but there is no data ready in the Transmit SERDES Data register (Reg
0x0F). This will only assert after the transmitter has transmitted at least one bit. This bit is cleared by reading the Transmit
Interrupt Status register (Reg 0x0E).
2
Overflow
The Overflow bit is used to signal when an overflow condition associated with the Transmit SERDES Data register (0x0F)
has occurred.
1 = Overflow Interrupt pending.
0 = No Overflow Interrupt pending.
This IRQ will assert during an overflow condition to the Transmit SERDES Data register (Reg 0x0F). An overflow occurs
when the new data is loaded into the Transmit SERDES Data register (Reg 0x0F) before the previous data has been sent.
This bit is cleared by reading the Transmit Interrupt Status register (Reg 0x0E).
1
Done
The Done bit is used to signal the end of a data transmission.
1 = Done Interrupt pending.
0 = No Done Interrupt pending.
This IRQ will assert when the data is finished sending a byte of data and there is no more data to be sent. This will only assert
after the transmitter has transmitted as least one bit. This bit is cleared by reading the Transmit Interrupt Status register (Reg
0x0E)
0
Empty
The Empty bit is used to signal when the Transmit SERDES Data register (Reg 0x0F) has been emptied.
1 = Empty Interrupt pending.
0 = No Empty Interrupt pending.
This IRQ will assert when the transmit serdes is empty. When this IRQ is asserted it is ok to write to the Transmit SERDES
Data register (Reg 0x0F). Writing the Transmit SERDES Data register (Reg 0x0F) will clear this IRQ. It will be set when the
data is loaded into the transmitter, and it is ok to write new data.
Note:
5. All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be implemented without enabling IRQs. The
status bits are affected by the TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the transmit status will read 0 if the IC is not in transmit mode. These
registers are read-only.
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Addr: 0x0F
7
REG_TX_DATA
6
5
4
Default: 0x00
3
2
1
0
Data
Figure 7-14. Transmit SERDES Data
Bit
Name
Description
7:0
Data
Transmit Data. The over-the-air transmitted order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4,
followed by bit 5, followed by bit 6, followed by bit 7.
Addr: 0x10
7
REG_TX_VALID
6
5
4
Default: 0x00
3
2
1
0
Valid
Figure 7-15. Transmit SERDES Valid
Bit
Name
Description
7:0
Valid[6]
The Valid bits are used to determine which of the bits in the Transmit SERDES Data register (reg 0x0F) are valid.
1 = Valid transmit bit.
0 = Invalid transmit bit.
Addr: 0x11-18
6
3
6
2
6
1
6
0
5
9
5
8
5
7
Default:
0x1E8B6A3DE0E9B222
REG_PN_CODE
5
6
5
5
5
4
Address 0x18
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
Address 0x17
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
Address 0x16
3
7
3
6
3
5
3
4
3
3
3
2
1
0
Address 0x15
Figure 7-16. PN Code
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
Address 0x14
2
3
2
2
2
1
2
0
1
9
1
8
Address 0x13
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
Address 0x12
9
8
7
6
5
4
3
2
Address 0x11
Bit
Name
Description
63:0
PN Codes
The value inside the 8 byte PN code register is used as the spreading code for DSSS communication. All 8 bytes can
be used together for 64 chips/bit PN code communication, or the registers can be split into two sets of 32 chips/bit PN
codes and these can be used alone or with each other to accomplish faster data rates. Not any 64 chips/bit value can
be used as a PN code as there are certain characteristics that are needed to minimize the possibility of multiple PN
codes interfering with each other or the possibility of invalid correlation. The over-the-air order is bit 0 followed by bit 1...
followed by bit 62, followed by bit 63.
Note:
6. The Valid bit in the Transmit SERDES Valid register (Reg 0x10) is used to mark whether the radio will send data or preamble during that bit time of the data
byte. Data is sent LSB first. The SERDES will continue to send data until there are no more VALID bits in the shifter. For example, writing 0x0F to the Transmit
SERDES Valid register (Reg 0x10) will send half a byte.
Document 38-16007 Rev. *I
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CYWUSB6934
Addr: 0x19
7
REG_THRESHOLD_L
6
5
4
Reserved
3
Default: 0x08
2
1
0
Threshold Low
Figure 7-17. Threshold Low
Bit
Name
Description
7
Reserved
This bit is reserved and should be written with zero.
6:0
Threshold Low
The Threshold Low value is used to determine the number of missed chips allowed when attempting to correlate a
single data bit of value ‘0’. A perfect reception of a data bit of ‘0’ with a 64 chips/bit PN code would result in zero
correlation matches, meaning the exact inverse of the PN code has been received. By setting the Threshold Low
value to 0x08 for example, up to eight chips can be erroneous while still identifying the value of the received data
bit. This value along with the Threshold High value determine the correlator count values for logic ‘1’ and logic ‘0’.
The threshold values used determine the sensitivity of the receiver to interference and the dependability of the
received data. By allowing a minimal number of erroneous chips the dependability of the received data increases
while the robustness to interference decreases. On the other hand increasing the maximum number of missed chips
means reduced data integrity but increased robustness to interference and increased range.
Addr: 0x1A
7
REG_THRESHOLD_H
6
5
4
Reserved
3
Default: 0x38
2
1
0
Threshold High
Figure 7-18. Threshold High
Bit
Name
Description
7
Reserved
This bit is reserved and should be written with zero.
6:0
Threshold High
The Threshold High value is used to determine the number of matched chips allowed when attempting to correlate
a single data bit of value ‘1’. A perfect reception of a data bit of ‘1’ with a 64 chips/bit or a 32 chips/bit PN code would
result in 64 chips/bit or 32 chips/bit correlation matches, respectively, meaning every bit was received perfectly. By
setting the Threshold High value to 0x38 (64-8) for example, up to eight chips can be erroneous while still identifying
the value of the received data bit. This value along with the Threshold Low value determine the correlator count
values for logic ‘1’ and logic ‘0’. The threshold values used determine the sensitivity of the receiver to interference
and the dependability of the received data. By allowing a minimal number of erroneous chips the dependability of
the received data increases while the robustness to interference decreases. On the other hand increasing the
maximum number of missed chips means reduced data integrity but increased robustness to interference and
increased range.
Addr: 0x1C
7
REG_WAKE_EN
6
5
4
3
Reserved
Default: 0x00
2
1
0
Wakeup Enable
Figure 7-19. Wake Enable
Bit
Name
Description
7:1
Reserved
These bits are reserved and should be written with zeroes.
0
Wakeup Enable
Wakeup interrupt enable.
0 = disabled
1 = enabled
A wakeup event is triggered when the PD pin is deasserted and once the IC is ready to receive SPI communications.
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Addr: 0x1D
7
REG_WAKE_STAT
6
5
4
Default: 0x01
3
2
1
0
Wakeup Status
Reserved
Figure 7-20. Wake Status
Bit
Name
Description
7:1
Reserved
These bits are reserved. This register is read-only.
0
Wakeup Status
Wakeup status.
0 = Wake interrupt not pending
1 = Wake interrupt pending
This IRQ will assert when a wakeup condition occurs. This bit is cleared by reading the Wake Status register (Reg
0x1D). This register is read-only.
Addr: 0x20
REG_ANALOG_CTL
Default: 0x00
7
6
5
4
3
2
1
0
Reserved
Reg Write
Control
MID Read
Enable
Reserved
Reserved
PA Output
Enable
PA Invert
Reset
Figure 7-21. Analog Control
Bit
Name
Description
7
Reserved
This bit is reserved and should be written with zero.
6
Reg Write Control
Enables write access to Reg 0x2E and Reg 0x2F.
1 = Enables write access to Reg 0x2E and Reg 0x2F
0 = Reg 0x2E and Reg 0x2F are read-only
5
MID Read Enable
The MID Read Enable bit must be set to read the contents of the Manufacturing ID register (Reg 0x3C-0x3F).
Enabling the Manufacturing ID register (Reg 0x3C-0x3F) consumes power. This bit should only be set when reading
the contents of the Manufacturing ID register (Reg 0x3C-0x3F).
1 = Enables read of MID registers
0 = Disables read of MID registers
4:3
Reserved
These bits are reserved and should be written with zeroes.
2
PA Output Enable
The Power Amplifier Output Enable bit is used to enable the PACTL pin for control of an external power amplifier.
1 = PA Control Output Enabled on PACTL pin
0 = PA Control Output Disabled on PACTL pin
1
PA Invert
The Power Amplifier Invert bit is used to specify the polarity of the PACTL signal when the PA Output Enable bit is
set high. PA Output Enable and PA Invert cannot be simultaneously changed.
1 = PACTL active low
0 = PACTL active high
0
Reset
The Reset bit is used to generate a self-clearing device reset.
1 = Device Reset. All registers are restored to their default values.
0 = No Device Reset.
Document 38-16007 Rev. *I
Page 18 of 30
CYWUSB6932
CYWUSB6934
Addr: 0x21
7
REG_CHANNEL
6
5
4
3
Reserved
Default: 0x00
2
1
0
Channel
Figure 7-22. Channel
Bit
Name
Description
7
Reserved
This bit is reserved and should be written with zero.
6:0
Channel
The Channel register (Reg 0x21) is used to determine the Synthesizer frequency. A value of 2 corresponds to a communication
frequency of 2.402 GHz, while a value of 79 corresponds to a frequency of 2.479GHz. The channels are separated from each
other by 1 MHz intervals.
Limit application usage to channels 2-79 to adhere to FCC regulations. FCC regulations require that channels 0 and 1 and
any channel greater than 79 be avoided. Use of other channels may be restricted by other regulatory agencies. The application
MCU must ensure that this register is modified before transmitting data over the air for the first time.
Addr: 0x22
7
REG_RSSI
6
Reserved
5
4
Default: 0x00
3
Valid
2
1
0
RSSI
Figure 7-23. Receive Signal Strength Indicator (RSSI)[7]
Bit
Name
Description
7:6
Reserved
These bits are reserved. This register is read-only.
5
Valid
The Valid bit indicates whether the RSSI value in bits [4:0] are valid. This register is Read Only.
1 = RSSI value is valid
0 = RSSI value is invalid
4:0
RSSI
The Receive Strength Signal Indicator (RSSI) value indicates the strength of the received signal. This is a read only
value with the higher values indicating stronger received signals meaning more reliable transmissions.
Addr: 0x23
7
REG_PA
6
5
4
Default: 0x00
3
Reserved
2
1
0
PA Bias
Figure 7-24. PA Bias
Bit
Name
Description
7:3
Reserved
These bits are reserved and should be written with zeroes.
2:0
PA Bias
The Power Amplifier Bias (PA Bias) bits are used to set the transmit power of the IC through increasing (values up to 7) or
decreasing (values down to 0) the gain of the on-chip Power Amplifier. The higher the register value the higher the transmit
power. By changing the PA Bias value signal strength management functions can be accomplished. For general purpose
communication a value of 7 is recommended.
Note:
7. The RSSI will collect a single value each time the part is put into receive mode via Control register (Reg 0x03, bit 7=1). See Section 4.7 for more details.
Document 38-16007 Rev. *I
Page 19 of 30
CYWUSB6932
CYWUSB6934
Addr: 0x24
REG_CRYSTAL_ADJ
7
6
5
Reserved
Clock Output
Disable
4
Default: 0x00
3
2
1
0
Crystal Adjust
Figure 7-25. Crystal Adjust
Bit
Name
Description
7
Reserved
This bit is reserved and should be written with zero.
6
Clock Output
Disable
The Clock Output Disable bit disables the 13 MHz clock driven on the X13OUT pin.
1 = No 13-MHz clock driven externally.
0 = 13-MHz clock driven externally.
If the 13-MHz clock is driven on the X13OUT pin then receive sensitivity will be reduced by –4 dBm on channels
5+13n. By default the 13-MHz clock output pin is enabled. This pin is useful for adjusting the 13-MHz clock, but it
interfere with every 13th channel beginning with 2.405GHz channel. Therefore, it is recommended that the 13-MHz
clock output pin be disabled when not in use.
5:0
Crystal Adjust
The Crystal Adjust value is used to calibrate the on-chip parallel load capacitance supplied to the crystal. Each
increment of the Crystal Adjust value typically adds 0.135 pF of parallel load capacitance. The total range is 8.5
pF, starting at 8.65 pF. These numbers do not include PCB parasitics, which can add an additional 1–2 pF.
Addr: 0x26
7
REG_VCO_CAL
6
5
4
Default: 0x00
3
VCO Slope Enable
2
1
0
Reserved
Figure 7-26. VCO Calibration
Bit
Name
Description
7:6
VCO Slope Enable
(Write-Only)
The Voltage Controlled Oscillator (VCO) Slope Enable bits are used to specify the amount of variance automatically
added to the VCO.
11 = –5/+5 VCO adjust. The application MCU must configure this option during initialization.
10 = –2/+3 VCO adjust.
01 = Reserved.
00 = No VCO adjust.
These bits are undefined for read operations.
5:0
Reserved
These bits are reserved and should be written with zeroes.
Addr: 0x2E
7
REG_PWR_CTL
6
Reg Power
Control
5
4
3
Default: 0x00
2
1
0
Reserved
Figure 7-27. Reg Power Control
Bit
Name
Description
7
Reg Power
Control
When set, this bit disables unused circuitry and saves radio power. The user must set Reg 0x20, bit 6=1 to enable writes
to Reg 0x2E. The application MCU must set this bit during initialization.
6:0
Reserved
These bits are reserved and should be written with zeroes.
Document 38-16007 Rev. *I
Page 20 of 30
CYWUSB6932
CYWUSB6934
Addr: 0x2F
7
REG_CARRIER_DETECT
6
5
4
Default: 0x00
3
2
1
0
Reserved
Carrier Detect
Override
Figure 7-28. Carrier Detect
Bit
Name
Description
7
Carrier Detect Override
When set, this bit overrides carrier detect. The user must set Reg 0x20, bit 6=1 to enable writes to Reg 0x2F.
6:0
Reserved
These bits are reserved and should be written with zeroes.
Addr: 0x32
7
REG_CLOCK_MANUAL
6
5
4
Default: 0x00
3
2
1
0
Manual Clock Overrides
Figure 7-29. Clock Manual
Bit
Name
Description
7:0
Manual Clock Overrides
This register must be written with 0x41 after reset for correct operation
Addr: 0x33
7
REG_CLOCK_ENABLE
6
5
4
Default: 0x00
3
2
1
0
Manual Clock Enables
Figure 7-30. Clock Enable
Bit
Name
Description
7:0
Manual Clock Enables
This register must be written with 0x41 after reset for correct operation
Addr: 0x38
7
REG_SYN_LOCK_CNT
6
5
4
Default: 0x64
3
2
1
0
Count
Figure 7-31. Synthesizer Lock Count
Bit
Name
Description
7:0
Count
Determines the length of delay in 2µs increments for the synthesizer to lock when auto synthesizer is enabled via Control register
(0x03, bit 1=0) and not using the PLL lock signal. The default register setting is typically sufficient.
Addr: 0x3C-3F
3
1
3
0
2
9
2
8
2
7
2
6
2
5
REG_MID
2
4
2
3
Address 0x3F
2
2
2
1
2
0
1
9
1
8
Address 0x3E
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
Address 0x3D
9
8
7
6
5
4
3
2
1
0
Address 0x3C
Figure 7-32. Manufacturing ID
Bit
Name
Description
31:30 Address[31:30] These bits are read back as zeroes.
29:0
Address[29:0]
These bits are the Manufacturing ID (MID) for each IC. The contents of these bits cannot be read unless the MID Read
Enable bit (bit 5) is set in the Analog Control register (Reg 0x20). Enabling the Manufacturing ID register (Reg
0x3C-0x3F) consumes power. The MID Read Enable bit in the Analog Control register (Reg 0x20, bit 5) should only
be set when reading the contents of the Manufacturing ID register (Reg 0x3C-0x3F). This register is read-only.
Document 38-16007 Rev. *I
Page 21 of 30
CYWUSB6932
CYWUSB6934
8.0
Pin Definitions
Table 8-1. Pin Description Table for the CYWUSB6932/CYWUSB6934
Pin QFN
Name
Type
Default
Input
Input
RF Input. Modulated RF signal received (CYWUSB6934 only).
Description
Output
N/A
RF Output. Modulated RF signal to be transmitted.
Input
N/A
Crystal Input. (refer to Section 4.6).
N/A
Crystal Input. (refer to Section 4.6).
46
RFIN
5
RFOUT
38
X13
35
X13IN
26
X13OUT
33
PD
Input
N/A
Power Down. Asserting this input (low), will put the
CYWUSB6932/CYWUSB6934 in the Suspend Mode (X13OUT is 0 when PD
is low).
14
RESET
Input
N/A
Active LOW Reset. Device reset.
34
PACTL
I/O
Input
PACTL. External Power Amplifier control. Pull-down or make output.
20
DIO
I/O
Input
Data Input/Output. SERDES Bypass Mode Data Transmit/Receive.
Input
Data I/O Valid. SERDES Bypass Mode Data Transmit/Receive Valid.
Input
Output/Hi-Z
I/O
Output System Clock. Buffered 13-MHz system clock.
19
DIOVAL
21
IRQ
23
MOSI
Input
N/A
Master-Output-Slave-Input Data. SPI data input pin.
24
MISO
Output/Hi-Z
Hi-Z
Master-Input-Slave-Output Data. SPI data output pin.
Output /Hi-Z
Output IRQ. Interrupt and SERDES Bypass Mode DIOCLK.
25
SCK
Input
N/A
SPI Input Clock. SPI clock.
22
SS
Input
N/A
Slave Select Enable. SPI enable.
VCC
H
VCC = 2.7V to 3.6V.
GND
L
Ground = 0V.
N/A
N/A
Must be tied to Ground.
GND
L
Must be tied to Ground.
6, 9, 16, 28, VCC
29, 32, 41,
42, 44, 45
13
GND
1, 2, 3, 4, 7, NC
8, 10, 11,
12, 15, 17,
18, 27, 30,
31, 36, 37,
39, 40, 43,
47, 48
Exposed
Paddle
GND
Document 38-16007 Rev. *I
Page 22 of 30
CYWUSB6932
CYWUSB6934
CYWUSB6934/CYWUSB6932
Top View*
NC 37
X13 38
NC 39
NC 40
VC C 41
VC C 42
NC 43
VC C 44
VC C 45
**RFIN 46
NC 47
NC 48
NC 1
36 NC
NC 2
35 X13IN
NC 3
34 PACTL
NC 4
33 PD
RFOUT 5
VC C 6
NC 7
32 VC C
CYWUSB6934/CYWUSB6932
48 QFN
31 NC
30 NC
NC 8
29 VC C
VC C 9
28 VC C
NC 10
27 NC
NC 11
26 X13OUT
NC 12
25 SCK
24 MISO
23 MOSI
22 SS
21 IRQ
20 DIO
19 DIOVAL
18 NC
17 NC
16 VC C
15 NC
14 RESET
13 GND
* E-PAD BOTTOM SIDE
** CYWUSB6934 Only
Figure 8-1. CYWUSB6934/CYWUSB6932, 48 QFN – Top View
Document 38-16007 Rev. *I
Page 23 of 30
CYWUSB6932
CYWUSB6934
9.0
Absolute Maximum Ratings
Storage Temperature ............................................................................................................................................–65°C to +150°C
Ambient Temperature with Power Applied ............................................................................................................–55°C to +125°C
Supply Voltage on VCC relative to VSS....................................................................................................................–0.3V to +3.9V
DC Voltage to Logic Inputs[8] ........................................................................................................................... –0.3V to VCC +0.3V
DC Voltage applied to
Outputs in High-Z State.................................................................................................................................... –0.3V to VCC +0.3V
Static Discharge Voltage (Digital)[9] .................................................................................................................................... >2000V
Static Discharge Voltage (RF)[9]............................................................................................................................................. 500V
Latch-up Current ...............................................................................................................................................+200 mA, –200 mA
10.0
Operating Conditions
VCC (Supply Voltage) ................................................................................................................................................... 2.7V to 3.6V
TA (Ambient Temperature Under Bias) .......................................................................................................................0°C to +70°C
Ground Voltage ........................................................................................................................................................................... 0V
FOSC (Oscillator or Crystal Frequency) ................................................................................................................ 13 MHz ±50 ppm
11.0
DC Characteristics (Over the Operating Range)
Table 11-1. DC Parameters
Parameter
Description
Conditions
Min.
2.7
Typ.[11]
Max.
Unit
3.0
3.6
V
VCC
Supply Voltage
VOH1
Output High Voltage condition 1
At IOH = –100.0 µA VCC – 0.1
VCC
V
VOH2
Output High Voltage condition 2
At IOH = –2.0 mA
3.0
V
VOL
Output Low Voltage
At IOL = 2.0 mA
2.4
0.0
0.4
V
V
VIH
Input High Voltage
2.0
VCC[10]
VIL
Input Low Voltage
–0.3
0.8
V
IIL
Input Leakage Current
0.26
+1
µA
CIN
Pin Input Capacitance (except X13, X13IN,
RFIN)
3.5
10
pF
ISleep
Current consumption during power-down mode PD = LOW
0.24
10[14]
µA
IDLE ICC
Current consumption without synthesizer
STARTUP ICC
ICC from PD high to oscillator stable.
TX AVG ICC1
0 < VIN < VCC
[12]
Average transmitter current consumption
consumption[13]
PD = HIGH
no handshake
with handshaking
–1
3
mA
1.8
mA
5.9
mA
TX AVG ICC2
Average transmitter current
8.1
mA
RX ICC (PEAK)
Current consumption during receive
57.7
mA
TX ICC (PEAK)
Current consumption during transmit
69.1
mA
28.7
mA
SYNTH SETTLE ICC Current consumption with Synthesizer on, No
Transmit or Receive
Notes:
8. It is permissible to connect voltages above Vcc to inputs through a series resistor limiting input current to 1 mA. This can’t be done during power down mode.
AC timing not guaranteed.
9. Human Body Model (HBM).
10. It is permissible to connect voltages above Vcc to inputs through a series resistor limiting input current to 1 mA.
11. Typ. values measured with VCC = 3.0V @ 25°C
12. Average Icc when transmitting a 5-byte packet (3 data bytes + 2 bytes of protocol) every 10 ms using the WirelessUSB LS 1-way protocol.
13. Average Icc when transmitting a 5-byte packet (3 data bytes + 2 bytes of protocol) every 10 ms using the WirelessUSB LS 2-way protocol.
14. Max. value measured with VCC = 3.3V
Document 38-16007 Rev. *I
Page 24 of 30
CYWUSB6932
CYWUSB6934
AC Characteristics [15]
12.0
Table 12-1. SPI Interface[17]
Parameter
Description
tSCK_CYC
Min.
SPI Clock Period
tSCK_HI (BURST READ)[16] SPI Clock High Time
Typ.
Max.
Unit
476
ns
238
ns
tSCK_HI
SPI Clock High Time
158
ns
tSCK_LO
SPI Clock Low Time
158
ns
tDAT_SU
SPI Input Data Set-up Time
10
ns
tDAT_HLD
SPI Input Data Hold Time
97[17]
ns
[17]
[17]
tDAT_VAL
SPI Output Data Valid Time
tSS_SU
SPI Slave Select Set-up Time before first positive edge of SCK[18]
250
ns
tSS_HLD
SPI Slave Select Hold Time after last negative edge of SCK
80
ns
77
174
ns
tSCK_CYC
tSCK_HI
tSCK_LO
SCK
SS
MOSI
SA
tSS_SU
tDAT_SU
M
PL
D
E
tDAT_HLD
R
IV
tSS_HLD
E
d a ta fro m m c u
d a ta fro m m c u
d a ta fro m m c u
d a ta
d a ta to m c u
d a ta
tD AT_VAL
M IS O
d a ta to m c u
Figure 12-1. SPI Timing Diagram
t SCK_CYC
t SCK_HI
SCK
t SC K_HI (BU RST READ)
every 9 th SC K_HI
D
SS
M ISO
t SCK_LO
every 8 th SC K_HI
R
every 10 th SCK_HI
D
IV
E
data to m cu
data to m cu
R
IV
D
E
data to m cu
R
IV
E
data
t DAT_VAL
Figure 12-2. SPI Burst Read Every 9th SCK HI Stretch Timing Diagram
Notes:
15. AC values are not guaranteed if voltages on any pin exceed Vcc.
16. This stretch only applies to every 9th SCK HI pulse for SPI Burst Reads only.
17. For FOSC = 13 MHz ±50 ppm, 3.3v @ 25°C.
18. SCK must start low, otherwise the success of SPI transactions are not guaranteed.
Document 38-16007 Rev. *I
Page 25 of 30
CYWUSB6932
CYWUSB6934
Table 12-2. DIO Interface
Parameter
Description
Transmit
Min.
Typ.
Max.
Unit
tTX_DIOVAL_SU
DIOVAL Set-up Time
2.1
µs
tTX_DIO_SU
DIO Set-up Time
2.1
µs
tTX_DIOVAL_HLD
DIOVAL Hold Time
0
µs
tTX_DIO_HLD
DIO Hold Time
0
tTX_IRQ_HI
Minimum IRQ High Time - 32 chips/bit DDR
8
µs
Minimum IRQ High Time - 32 chips/bit
16
µs
Minimum IRQ High Time - 64 chips/bit
32
µs
Minimum IRQ Low Time - 32 chips/bit DDR
8
µs
Minimum IRQ Low Time - 32 chips/bit
16
µs
tTX_IRQ_LO
µs
Minimum IRQ Low Time - 64 chips/bit
32
Receive
tRX_DIOVAL_VLD
tRX_DIO_VLD
tRX_IRQ_HI
tRX_IRQ_LO
Min.
Typ.
µs
Max.
Unit
DIOVAL Valid Time - 32 chips/bit DDR
–0.01
6.1
µs
DIOVAL Valid Time - 32 chips/bit
–0.01
8.2
µs
DIOVAL Valid Time - 64 chips/bit
–0.01
16.1
µs
DIO Valid Time - 32 chips/bit DDR
–0.01
6.1
µs
DIO Valid Time - 32 chips/bit
–0.01
8.2
µs
DIO Valid Time - 64 chips/bit
–0.01
16.1
µs
Minimum IRQ High Time - 32 chips/bit DDR
1
µs
Minimum IRQ High Time - 32 chips/bit
1
µs
Minimum IRQ High Time - 64 chips/bit
1
µs
Minimum IRQ Low Time - 32 chips/bit DDR
8
µs
Minimum IRQ Low Time - 32 chips/bit
16
µs
Minimum IRQ Low Time - 64 chips/bit
32
µs
t R X _ IR Q _ H I
IR Q
D IO /
D IO V A L
SA
M
PL
t R X _ IR Q _ L O
SA
E
d a ta
M
PL
E
d a ta
d a ta
t
t R XR_XD_IOD VIOA_LV_LVDL D
Figure 12-3. DIO Receive Timing Diagram
t TX _IR Q _H I
IR Q
D IO /
D IO V A L
t T X _IR Q _LO
SA
M
PL
SA
E
data
t T X _D IO _S U
t TX _D IO V A L_S U
M
PL
E
data
t T X _D IO _H LD
t T X _D IO V A L_H LD
Figure 12-4. DIO Transmit Timing Diagram
Document 38-16007 Rev. *I
Page 26 of 30
CYWUSB6932
CYWUSB6934
12.1
Radio Parameters
Table 12-3. Radio Parameters
Parameter Description
Conditions
Min.
Typ.
Max.
[19]
RF Frequency Range
2.400
2.483
Radio Receiver (T = 25°C, VCC = 3.3V, fosc = 13.000 MHz, X13OUT off, 64 chips/bit, Threshold Low = 8, Threshold High = 56, BER < 10–3)
Sensitivity
–90
Maximum Received Signal
–20
–10
RSSI value for PWRin > –40 dBm
28–31
0–10
RSSI value for PWRin < –95 dBm
Receive Ready[20]
Interference Performance
Co-channel Interference rejection
C = –60 dBm
Carrier-to-Interference (C/I)
Adjacent (1 MHz) channel selectivity C/I 1 MHz
C = –60 dBm
Adjacent (2 MHz) channel selectivity C/I 2 MHz
C = –60 dBm
Adjacent (> 3 MHz) channel selectivity C/I > 3 MHz
C = –67 dBm
Image[21] Frequency Interference, C/I Image
C = –67 dBm
Adjacent (1 MHz) interference to in-band image
C = –67 dBm
frequency, C/I image ±1 MHz
Out-of-Band Blocking Interference Signal Frequency
30 MHz – 2399 MHz, except (FO/N & FO/N±1 MHz)[22] C = –67 dBm
2498 MHz – 12.75 GHz, except (FO*N & FO*N±1 MHz) [22] C = –67 dBm
Intermodulation
C = –64 dBm, ∆f = 5,10 MHz
Spurious Emission
30 MHz–1 GHz
1 GHz–12.75 GHz except (4.8 GHz - 5.0 GHz)
4.8 GHz–5.0 GHz
Radio Transmitter (T = 25°C, VCC = 3.3V, fosc = 13.000 MHz)
Maximum RF Transmit Power
PA = 7
RF Power Control Range
RF Power Range Control Step Size
seven steps, monotonic
Frequency Deviation
PN Code Pattern 10101010
Frequency Deviation
PN Code Pattern 11110000
Zero Crossing Error
Occupied Bandwidth
100-kHz resolution bandwidth, –6 dBc
Initial Frequency Offset
In-band Spurious
Second Channel Power (±2 MHz)
> Third Channel Power (>3 MHz)
Non-Harmonically Related Spurs
30 MHz–12.75 GHz
Harmonic Spurs
Second Harmonic
Third Harmonic
Fourth and Greater Harmonics
35
Unit
GHz
dBm
dBm
µs
11
dB
3
–30
–40
–20
–25
dB
dB
dB
dB
dB
–30
–20
–39
dBm
dBm
dBm
–57
dBm
–54
dBm
–40[23] dBm
0
30
4.3
270
320
±125
dBm
dB
dB
kHz
kHz
ns
kHz
kHz
500
±75
–30
–40
dBm
dBm
–54
dBm
–28
–25
–42
dBm
dBm
dBm
Notes:
19. Subject to regulation.
20. Max. time after receive enable and the synthesizer has settled before receiver is ready.
21. Image frequency is +4 MHz from desired channel (2 MHz low IF, high side injection).
22. FO = Tuned Frequency, N = Integer.
23. Antenna matching network and antenna will attenuate the output signal at these frequencies to meet regulatory requirements.
Document 38-16007 Rev. *I
Page 27 of 30
CYWUSB6932
CYWUSB6934
12.2
Power Management Timing
Table 12-4. Power Management Timing (The values below are dependent upon oscillator network component selection)[28]
Parameter
Description
Conditions
tPDN_X13
Time from PD deassert to X13OUT
tSPI_RDY
Time from oscillator stable to start of SPI transactions
Min.
2000
tPWR_RST
Power On to RESET deasserted
tRST
Minimum RESET asserted pulse width
tPWR_PD
Power On to PD deasserted[24]
1
VCC @ 2.7V
PD deassert to clocks running
tPD
Minimum PD asserted pulse width
tSLEEP
PD assert to low power mode
IRQ[26] assert
Unit
µs
1300
µs
1
µs
1300
µs
2000
10
µs
µs
interrupt)[27]
50
ns
2000
µs
tWAKE_INT
PD deassert to
tSTABLE
PD deassert to clock stable
to within ±10 ppm
2100
µs
tSTABLE2
IRQ assert (wake interrupt) to clock stable
to within ±10 ppm
2100
µs
tPDN_X13
X13O U T
t S P I_ R D Y
S
VCC
(wake
Max.
µs
[25]
tWAKE
Typ
A
T
R
T
tPW R _R ST
PD
tPW R_PD
P
U
RESET
tRST
Figure 12-5. Power On Reset/Reset Timing
tWAKE
X13OUT
KE
EP
t PD
A
W
E
SL
PD
IR
IRQ
Q
tSLEEP
tSTABLE
tWAKE_INT
tSTABLE2
Figure 12-6. Sleep / Wake Timing
Notes:
24. The PD pin must be asserted at power up to ensure proper crystal startup.
25. When X13OUT is enabled.
26. Both the polarity and the drive method of the IRQ pin are programmable. See page 9 for more details. Figure 12-6 illustrates default values for the Configuration
register (Reg 0x05, bits 1:0).
27. A wakeup event is triggered when the PD pin is deasserted. Figure 12-6 illustrates a wakeup event configured to trigger an IRQ pin event via the Wake Enable
register (Reg 0x1C, bit 0=1).
28. Measured with CTS ATXN6077A crystal.
Document 38-16007 Rev. *I
Page 28 of 30
CYWUSB6932
CYWUSB6934
12.3
AC Test Loads and Waveforms for Digital Pins
AC Test Loads
DC Test Load
OUTPUT
OUTPUT
5 pF
30 pF
INCLUDING
JIG AND
SCOPE
R1
VCC
OUTPUT
INCLUDING
JIG AND
Typical
SCOPE
Max
R2
ALL INPUT PULSES
Parameter
R1
R2
RTH
VTH
VCC
VCC
Unit
Ω
Ω
Ω
V
V
1071
937
500
1.4
3.00
90%
90%
10%
GND
10%
Fall time: 1 V/ns
Rise time: 1 V/ns
THÉVENIN EQUIVALENT
RTH
VTH
OUTPUT
Equivalent to:
Figure 12-7. AC Test Loads and Waveforms for Digital Pins
13.0
Ordering Information
Table 13-1. Ordering Information
Part Number
Radio
CYWUSB6932-48LFXC Transmitter
CYWUSB6934-48LFXC Transceiver
14.0
Package Name Package Type
48 QFN
48 Quad Flat Package No Leads Lead-Free
48 QFN
48 Quad Flat Package No Leads Lead-Free
Operating Range
Commercial
Commercial
Package Description
0.08
6.90
7.10
C
1.00 MAX.
0.05 MAX.
X
0.80 MAX.
6.70
6.80
0.23±0.05
0.20 REF.
N
N
PIN1 ID
0.20 R.
1
1
2
2
0.80 DIA.
6.70
6.80
6.90
7.10
0.45
E-PAD
5.45
5.55
Y
0.30-0.45
0°-12°
0.50
C
TOP VIEW
5.45
5.55
SEATING
PLANE
SIDE VIEW
0.42±0.18
(4X)
BOTTOM VIEW
51-85152-*B
DIMENSIONS IN mm MIN.
MAX.
REFERENCE JEDEC MO-220
PKG. WEIGHT 0.13 gms
E-PAD SIZE PADDLE SIZE
(X, Y MAX.)
5.1 X 5.1
5.3 X 5.3
3.8 X 3.8
4.0 X 4.0
Figure 14-1. 48-pin Lead-Free QFN 7 x 7 mm LY48
The recommended dimension of the PCB pad size for the
E-PAD underneath the QFN is 209 mils × 209 mils (width x
length).
This document is subject to change, and may be found to contain errors of omission or changes in parameters. For feedback or
technical support regarding Cypress WirelessUSB products please contact Cypress at www.cypress.com. WirelessUSB, PSoC,
and enCoRe are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders.
Document 38-16007 Rev. *I
Page 29 of 30
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CYWUSB6932
CYWUSB6934
Document History Page
Document Title: CYWUSB6932/CYWUSB6934 WirelessUSB™ LS 2.4-GHz DSSS Radio SoC
Document Number: 38-16007
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
123907
01/20/03
LXA
New data sheet
*A
125470
04/28/03
XGR
Preliminary release
*B
127076
07/30/03
KKU
Updated pinouts, timing diagrams, AC Test loads, DC Characteristics, Radio
Characteristics
Removed die
*C
128886
08/04/03
KKV
Minor change: removed table of contents and fixed layout of section 10.
*D
129180
12/04/03
TGE
Updated AC and DC characteristics from char. results
Updated register entries
Changed package type from 56-pin QFN to 48-pin QFN
Updated all pinouts and timing diagrams
Updated block diagram and functional description
Updated application interfaces
Added Interrupt descriptions
*E
131851
12/15/03
TGE
Changed Static Discharge Voltage (Digital) Specification of Section 9.0
*F
241471
See ECN
ZTK
Removed Static Discharge Voltage (Digital) Specification of Section 9.0 footnote
Updated REG_DATA_RATE (0x04), 111—Not Valid
Swapped bit field descriptions of REG_CONFIG
Corrected Figure 3-1 and Figure 6-2
Minor edits throughout
*G
284810
See ECN
ZTK
Removed SOIC package option
Updated ordering information section
Added Table 4-1 Internal PA Output Power Step Table
Added tSTABLE2 Parameter to Table 12-4 and Figure 12-6
Corrected Figure 14-1 caption
Corrected Figure 6-2 to show QFN matching network
Removed Addr 0x01 and 0x02 - unused
Updated Figure 8-1
Updated Spurious Emissions parameters
*H
335758
See ECN
TGE
Corrected Figure 6-2 - swap RFIN / RFOUT
Corrected REG_CONTROL - bit 1 description
Added Table 11-1 footnote 14 - Max. value measured with Vcc = 3.3V
*I
391306
See ECN
TGE
Added receive ready parameter to Table 12-3
Document 38-16007 Rev. *I
Page 30 of 30