CY25100:Field and Factory Programmable Spread Spectrum Clock Generator for EMI Reduction

CY25100
Field and Factory Programmable Spread
Spectrum Clock Generator for EMI Reduction
Field and Factory Programmable Spread Spectrum Clock Generator for EMI Reduction
Features
Functional Description
■
Wide Operating Output (SSCLK) Frequency Range
❐ 3 MHz to 200 MHz
■
Programmable Spread Spectrum with nominal 31.5 kHz
Modulation Frequency
❐ Center Spread: ±0.25% to ±2.5%
❐ Down Spread: –0.5% to –5.0%
■
Input frequency range
❐ External Crystal: 8 to 30 MHz Fundamental Crystals
❐ External Reference: 8 to 166 MHz Clock
■
Integrated Phase-Locked Loop (PLL)
■
Field Programmable devices available
■
Programmable Crystal Load Capacitor Tuning Array
■
Low Cycle-to-cycle Jitter
■
Spread Spectrum on/off function
■
Powerdown or Output Enable function
■
Commercial and Industrial temperature ranges
■
3.3 V operation
■
8-pin TSSOP and SOIC packages
The CY25100 is a Spread Spectrum Clock Generator (SSCG) IC
used to reduce EMI found in today’s high speed digital electronic
systems.
The device uses a Cypress proprietary PLL and Spread
Spectrum Clock (SSC) technology to synthesize and modulate
the frequency of the input clock. By frequency modulating the
clock, the measured EMI at the fundamental and harmonic
frequencies are greatly reduced. This reduction in radiated
energy can significantly reduce the cost of complying with
regulatory agency (EMC) requirements and improve
time-to-market without degrading system performance.
The CY25100 uses a factory or field-programmable
configuration memory array to synthesize output frequency,
spread percentage, crystal load capacitor, reference clock output
on/off, spread spectrum on/off function, and PD#/OE options.
The spread percentage is programmed to either center spread
or down spread with various spread percentages. The range for
center spread is from ±0.25% to ±2.50%. The range for down
spread is from –0.5% to –5.0%.
The input to the CY25100 can either be a crystal or a clock
signal. The CY25100 has two clock outputs: REFCLK and
SSCLK. The non-spread spectrum REFCLK output has the
same frequency as the input of the CY25100.
For a complete list of related documentation, click here.
Logic Block Diagram
R FB
P LL
w ith
M O D U LA TIO N
C O N TR O L
3
XIN
C XIN
O U TP U T
D IVID E R S
and
MUX
PR O G R A M M A B LE
C O N FIG U R A TIO N
2
XOUT
C XOUT
6
R E FC LK
7
4
SS C LK
P D # or O E
8
S SO N #
Cypress Semiconductor Corporation
Document Number: 38-07499 Rev. *K
•
1
5
VD D
V SS
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 28, 2014
CY25100
Contents
Pinouts .............................................................................. 3
Pin Description ................................................................. 3
Programming Description ............................................... 4
Field Programmable CY25100 .................................. 4
CyberClocks Online Software ................................... 4
CY3672 Programmer and
CY3690/CY3691 Socket Adapters ..................................... 4
Factory Programmable CY25100 ................................ 4
Product Functions ............................................................ 4
Input Frequency (XIN, Pin 3 and XOUT, Pin 2) ........... 4
CXIN and CXOUT (Pin 3 and Pin 2) ........................... 4
Output Frequency (SSCLK, Pin 7) .............................. 4
Spread Percentage (SSCLK, Pin 7) ............................ 4
Reference Output (REFOUT, Pin 6) ............................ 4
Modulation Frequency ................................................. 4
Power Down or Output Enable (PD# or OE, Pin 4) ..... 4
Absolute Maximum Rating .............................................. 5
Recommended Crystal Specifications ........................... 5
Operating Conditions ....................................................... 5
Document Number: 38-07499 Rev. *K
DC Electrical Characteristics .......................................... 6
AC Electrical Characteristics .......................................... 7
Application Circuit ............................................................ 8
Switching Waveforms ...................................................... 9
Informational Graphs ..................................................... 10
Ordering Information ...................................................... 12
Possible Configurations ............................................. 12
Ordering Code Definitions ......................................... 13
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC® Solutions ...................................................... 18
Cypress Developer Community ................................. 18
Technical Support ..................................................... 18
Page 2 of 18
CY25100
Pinouts
Figure 1. CY25100 8-pin SOIC/TSSOP
1
VDD
SSON# 8
2
XOUT
SSCLK 7
3 XIN/CLKIN
REFCLK 6
4 PD#/OE
VSS 5
Pin Description
Pin
Name
Type
Description
1
VDD
Power
3.3 V power supply.
2
XOUT
Output
Crystal output. Leave this pin floating if external clock is connected to pin 3.
3
XIN/CLKIN Input
Crystal input or reference clock input.
4
PD#/OE
Input
User has the option of choosing either PD# or OE function.
Power Down pin: Active LOW. If PD# = 0, PLL and crystal oscillator circuit are powered down,
and outputs are weakly pulled low.
Output Enable pin: Active HIGH. If OE = 1, SSCLK and REFCLK are enabled.
5
VSS
Power
Power supply ground.
6
REFCLK
Output
Buffered reference output.
7
SSCLK
Output
Spread spectrum clock output.
8
SSON#
Input
Spread spectrum control: Active LOW. 0 = spread on. 1 = spread off.
Table 1. User Specified Variables
Pin Function
Input Frequency
Total Crystal
Load
Capacitance
Output
Frequency
Spread Percent
(0.5% – 5%,
0.25% granularity)
Reference
Output
Power Down or
Output Enable
Pin Name
XIN and XOUT
XIN and XOUT
SSCLK
SSCLK
REFOUT
PD#/OE
Pin#
3 and 2
3 and 2
7
7
6
4
Unit
MHz
pF
MHz
% and Center- or
Down-spread
On or Off
Select PD# or OE
USER
SPECIFIED
USER
SPECIFIED
USER
SPECIFIED
USER SPECIFIED
USER
SPECIFIED
USER
SPECIFIED
Document Number: 38-07499 Rev. *K
Page 3 of 18
CY25100
Programming Description
Field Programmable CY25100
The CY25100 is programmed at the package level, and must be
programmed prior to installation on a circuit board. Field
programmable devices are denoted by an “F” in the ordering
code, and are blank when shipped. The CY25100 is Flash
technology based, which allows it to be reprogrammed up to 100
times. This allows fast and easy design changes and product
updates, and eliminates issues with old and out of date inventory.
Samples and small prototype quantities can be programmed on
the CY3672 programmer with the CY3690 (TSSOP package) or
CY3691 (SOIC package) socket adapter.
CyberClocks Online Software
CyberClocks Online Software is a web based software
application that allows the user to custom-configure the
CY25100. All of the parameters in Table 1 on page 3 can be
entered as variables into the software. CyberClocks Online
outputs an industry-standard JEDEC file which is used for
programming the CY25100. CyberClocks Online is available at
www.cyberclocksonline.com web site.
CY3672 Programmer and CY3690/CY3691 Socket
Adapters
The Cypress CY3672 programmer and the CY3690 or CY3691
socket adapter may be used to program field programmable
versions of the CY25100. The CY3690 enables users to program
the CY25100ZXCF and CY25100ZXIF (TSSOP). CY3691
provides the ability to program the CY25100SXCF and
CY25100SXIF (SOIC). The CY3690 and CY3691 are separate
orderable items, so the existing users of the CY3672
programmer need to order only the specific socket adapter to
program the CY25100.
Factory Programmable CY25100
Factory programming by Cypress is available for high volume
orders. All requests must be submitted to the local Cypress Field
Application Engineer (FAE) or sales representative. After the
request is processed, you will receive a new part number,
samples, and data sheet with the programmed values. This part
number is used for additional sample requests and production
orders.
Product Functions
Input Frequency (XIN, Pin 3 and XOUT, Pin 2)
The input to the CY25100 can be a crystal or a clock. The input
frequency range for crystals is 8 to 30 MHz, and for clock signals
is 8 to 166 MHz.
Document Number: 38-07499 Rev. *K
CXIN and CXOUT (Pin 3 and Pin 2)
The CY25100 has internal load capacitors at Pin 3 (CXIN) and
Pin 2 (CXOUT) CXIN always equals CXOUT, and they are
programmable from 12 pF to 60 pF, in 0.5 pF increments.This
feature eliminates the need for external crystal load capacitors.
The following formula is used to calculate the value of CXIN and
CXOUT for matching the crystal load (CL):
CXIN = CXOUT = 2CL – CP
where CL is the crystal load capacitor as specified by the crystal
manufacturer and CP is the parasitic PCB capacitance on each
node of the crystal.
For example, if a crystal with CL of 16 pF is used, and CP is 2 pF,
CXIN and CXOUT are calculated as:
CXIN = CXOUT = (2 × 16) – 2 = 30 pF
If using a driven reference, set CXIN and CXOUT to the minimum
value 12 pF, connect the reference to XIN/CLKIN, and leave
XOUT unconnected.
Output Frequency (SSCLK, Pin 7)
The modulated frequency at the SSCLK output is produced by
synthesizing the input reference clock. The modulation can be
stopped by SSON# digital control input (SSON# = HIGH, no
modulation). If modulation is stopped, the clock frequency is the
nominal value of the synthesized frequency without modulation
(spread percentage = 0). The range of synthesized clock is from
3 to 200 MHz.
Spread Percentage (SSCLK, Pin 7)
The SSCLK spread can be programmed at any percentage value
from ±0.25% to ±2.5% for center spread and from –0.5% to
–5.0% for down spread.
Reference Output (REFOUT, Pin 6)
The reference clock output has the same frequency and the
same phase as the input clock. This output can be programmed
to be enabled (clock on) or disabled (High Z, clock off). If this
output is not required, it is recommended that the disabled
(High Z, Clock Off) option be selected.
Modulation Frequency
The modulation frequency is 31.5 kHz for all SSCLK frequencies
from 3 to 200 MHz.
Power Down or Output Enable (PD# or OE, Pin 4)
The part can be programmed to include either PD# or OE
function. PD# function powers down the oscillator and PLL. The
OE function disables the outputs.
Page 4 of 18
CY25100
Junction Temperature .............................. –40 C to +125 C
Absolute Maximum Rating
Data Retention at Tj = 125 C ..............................> 10 years
Supply Voltage (VDD) ...................................... –0.5 to +7.0 V
Package Power Dissipation ..................................... 350 mW
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .......................... > 2000V
Storage Temperature
(Non condensing) .................................... –55 C to +125 C
Recommended Crystal Specifications
Min
Typ
Max
Unit
fNOM
Parameter
Nominal Crystal Frequency
Description
Parallel resonance, fundamental
mode, AT cut
Comments
8
–
30
MHz
CLNOM
Nominal Load Capacitance
Internal load caps
6
–
30
pF
R1
Equivalent Series Resistance
(ESR)
Fundamental mode
–
–
25

R3/R1
Ratio of Third Overtone Mode
Ratio used because typical R1
ESR to Fundamental Mode ESR values are much less than the
maximum spec
3
–
–
–
DL
Crystal Drive Level
–
0.5
2
mW
Min
Typ
Max
Unit
3.13
3.30
3.45
V
0
–
70
°C
No external series resistor assumed
Operating Conditions
Parameter
Description
VDD
Supply Voltage
TA
Ambient Commercial Temperature
–40
–
85
°C
CLOAD
Ambient Industrial Temperature
Maximum Load Capacitance at Pin 6 and Pin 7
–
–
15
pF
fREF
External Reference Crystal (Fundamental tuned crystals only)
8
–
30
MHz
External Reference Clock
8
–
166
MHz
fSSCLK
SSCLK Output Frequency, CLOAD = 15 pF
3
–
200
MHz
fREFCLK
REFCLK Output Frequency, CLOAD = 15 pF
8
–
166
MHz
fMOD
Spread Spectrum Modulation Frequency
30.0
31.5
33.0
kHz
tPU
Power Up Time for all VDD’s to reach minimum specified voltage (power
ramp must be monotonic)
0.05
–
500
ms
Document Number: 38-07499 Rev. *K
Page 5 of 18
CY25100
DC Electrical Characteristics
Parameter
Description
Condition
Min
Typ
Max
Unit
IOH
Output High Current
VOH = VDD – 0.5 V, VDD = 3.3 V
(source)
10
12
mA
IOL
Output Low Current
VOL = 0.5 V, VDD= 3.3 V (sink)
10
12
mA
VIH
Input High Voltage
CMOS levels, 70% of VDD
0.7 × VDD
–
VDD
V
VIL
Input Low Voltage
CMOS levels, 30% of VDD
–
–
0.3 × VDD
V
IIH
Input High Current, PD#/OE and
SSON# Pins
Vin = VDD
–10
–
10
A
IIL
Input Low Current, PD#/OE and
SSON# Pins
Vin = VSS
–10
–
10
A
IOZ
Output Leakage Current
Three-state output, PD#/OE = 0,
output pulldown resistor disabled
–10
10
A
CXIN or
CXOUT[1]
Programmable Capacitance at
Pin 2 and Pin 3
Capacitance at minimum setting
–
12
–
pF
Capacitance at maximum setting
–
60
–
pF
CIN[1]
Input Capacitance at Pin 4 and
Pin 8
Input pins excluding XIN and XOUT
–
5
7
pF
IVDD
Supply Current
VDD = 3.45 V, Fin = 30 MHz,
REFCLK = 30 MHz,
SSCLK = 66 MHz,
CLOAD = 15 pF,
PD#/OE = SSON# = VDD
–
25
35
mA
IDDS
Standby Current
VDD = 3.45 V, Device powered down
with PD# = 0 V (driven reference
pulled down)
–
15
30
A
Note
1. Guaranteed by characterization, not 100% tested.
Document Number: 38-07499 Rev. *K
Page 6 of 18
CY25100
AC Electrical Characteristics
The AC Electrical Characteristics for part CY25100 is as follows. [2]
Parameter
DC
Description
Output Duty Cycle
Output Duty Cycle
SR1
Rising Edge Slew Rate
SR2
Falling Edge Slew Rate
SR3
Rising Edge Slew Rate
SR4
Falling Edge Slew Rate
tCCJ1[3]
Cycle-to-Cycle Jitter,
SSCLK (Pin 7)
tCCJ2[3]
tCCJ3[3]
Cycle-to-Cycle Jitter,
SSCLK (Pin 7)
Cycle-to-Cycle Jitter,
REFCLK (Pin 6)
tSTP
Power down Time (pin 4 = PD#)
tOE1
Output Disable Time (pin 4 = OE)
tOE2
Output Enable Time (pin 4 = OE)
tPU1
Power Up Time, Crystal is used
tPU2
Power Up Time, Reference clock
is used
Condition
SSCLK, Measured at VDD/2
REFCLK, Measured at VDD/2,
Duty Cycle of CLKIN = 50% at input
bias
SSCLK from 3 to 100 MHz; REFCLK
from 3 to 100 MHz; 20%–80% of
VDD
SSCLK from 3 to 100 MHz; REFCLK
from 3 to 100 MHz; 80%–20% of
VDD
SSCLK from 100 to 200 MHz;
REFCLK from 100 to 166 MHz;
20%–80% of VDD
SSCLK from 100 to 200 MHz;
REFCLK from 100 to 166 MHz;
80%–20% of VDD
CLKIN = SSCLK = 166 MHz, 2%
spread, REFCLK off
CLKIN = SSCLK = 66 MHz, 2%
spread, REFCLK off
CLKIN = SSCLK = 33 MHz, 2%
spread, REFCLK off
CLKIN = SSCLK = 166 MHz, 2%
spread, REFCLK on
CLKIN = SSCLK = 66 MHz, 2%
spread, REFCLK on
CLKIN = SSCLK = 33 MHz, 2%
spread, REFCLK on
CLKIN = SSCLK = 166 MHz, 2%
spread, REFCLK on
CLKIN = SSCLK = 66 MHz, 2%
spread, REFCLK on
CLKIN = SSCLK = 33 MHz, 2%
spread, REFCLK on
Time from falling edge on PD# to
stopped outputs (Asynchronous)
Time from falling edge on OE to
stopped outputs (Asynchronous)
Time from rising edge on OE to
outputs at a valid frequency
(Asynchronous)
Time from rising edge on PD# to
outputs
at
valid
frequency
(Asynchronous)
Time from rising edge on PD# to
outputs
at
valid
frequency
(Asynchronous), reference clock at
correct frequency
Min
45
40
Typ
50
50
Max
55
60
Unit
%
%
0.7
1.1
3.6
V/ns
0.7
1.1
3.6
V/ns
1.0
1.6
4.0
V/ns
1.2
1.6
4.0
V/ns
–
90
120
ps
–
100
130
ps
–
130
170
ps
–
100
130
ps
–
105
140
ps
–
200
260
ps
–
80
100
ps
–
100
130
ps
–
135
180
ps
–
150
350
ns
–
150
350
ns
–
150
350
ns
–
3.5
5
ms
–
2
3
ms
Notes
2. Guaranteed by characterization, not 100% tested.
3. Jitter is configuration dependent. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, spread percentage, temperature,
and output load.
Document Number: 38-07499 Rev. *K
Page 7 of 18
CY25100
Application Circuit
Figure 2. Application Circuit Diagram [4, 5, 6]
Power
SSON# 8
1 VDD
0.1uF
2
XOUT
SSCLK 7
CY25100
3 XIN/CLKIN
VDD
4 PD#/OE
REFCLK 6
VSS 5
Notes
4. Because the load capacitors (CXIN and CXOUT) are provided by the CY25100, no external capacitors are needed on the XIN and XOUT pins to match the crystal load
capacitor (CL). Only a single 0.1-F bypass capacitor is required on the VDD pin.
5. If an external clock is used, apply the clock to XIN (pin 3) and leave XOUT (pin 2) floating (unconnected).
6. If SSON# (pin 8) is LOW (VSS), the frequency modulation is on at SSCLK (pin 7).
Document Number: 38-07499 Rev. *K
Page 8 of 18
CY25100
Switching Waveforms
Figure 3. Duty Cycle Timing (DC = t1A/t1B)
OUTPUT
t1A
t1B
Figure 4. Output Rise/Fall Time (SSCLK and REFCLK)
VDD
OUTPUT
0V
Tr
Tf
Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3)
Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4)
Refer to AC Electrical Characteristics table for SR (Slew Rate) values.
Figure 5. Power Down and Power Up Timing
VDD
POWER
DOWN
0V
VIH
VIL
tPU
High Impedance
CLKOUT
(Asynchronous)
tSTP
Figure 6. Output Enable/Disable Timing
VDD
OUTPUT
ENABLE
0V
VIH
VIL
TOE2
High Impedance
CLKOUT
(Asynchronous)
TOE1
Document Number: 38-07499 Rev. *K
Page 9 of 18
CY25100
Informational Graphs
The Informational Graphs are as follows. [7]
161.5
169.5
169
168.5
168
167.5
167
166.5
166
165.5
165
164.5
164
163.5
163
160.5
162.5
172.5
171.5
Spread Spectrum Profile: Fnom=166MHz,
Fmod=30kHz, Spread%= -4%
170.5
169.5
168.5
167.5
166.5
Fnominal
165.5
164.5
163.5
162.5
Spread Spectrum Profile: Fnom=166MHz,
Fmod=30kHz, Spread%= +/-1%
Fnominal
159.5
0
20
68.5
40
60
80
100
120
Time (us)
140
160
180
0
200
Spread Spectrum Profile: Fnom=66MHz,
Fmod=30kHz, Spread%= -4%
68
20
67.5
67.5
67
67
66.5
66.5
Fnominal
66
40
60
80
100 120
Time (us)
140
160
180
200
Spread Spectrum Profile: Fnom=66MHz,
Fmod=30kHz, Spread%= +/-1%
Fnominal
66
65.5
65.5
65
64.5
65
64
64.5
63.5
0
20
40
60
80
100
120
Time (us)
140
160
180
0
200
20
40
60
80
100
120
Time (us)
140
160
180
200
IDD vs. SSCLK
Duty Cycle vs. REFCLK
T e m p e r atu r e =25C, V DD=3.3V , CL OAD=15p F, SS o ff,
( C L OA D =1 5 p F )
60
58
56
54
52
50
48
46
44
42
40
30
25
IDD (m A)
Duty Cycle (%)
Re fclk = 30M Hz
20
15
10
5
0
50
100
REFCLK (MHz)
150
200
0
0
50
100
150
200
SSCL K (M Hz )
Note
7. The Informational Graphs are meant to convey the typical performance levels. No performance specifications is implied or guaranteed. Refer to DC Electrical
Characteristics on page 6 and AC Electrical Characteristics on page 7 for device specifications.
Document Number: 38-07499 Rev. *K
Page 10 of 18
CY25100
Informational Graphs (continued)
The Informational Graphs are as follows. [7]
Measured Spread% vs. VDD over Tem perature
(Target Spread = 0.5%, Fout=100MHz, CLOA D =15pF)
Measured Spread% vs. VDD over
Tem perature
(Target Spread = 5.0%, Fout=100MHz, CLOA D =15pF)
0.55%
-40C
0.50%
25C
0.45%
85C
6.00%
Spread%
Spread%
0.60%
5.50%
-40C
5.00%
25C
4.50%
85C
4.00%
0.40%
2.7
3
3.3
3.6
2.7
3.9
3
3.3
SSCLK Attenuation vs. VDD over Tem perature
(Measured at 7th Harmonic w ith Fnom=100MHz and
Spread=5.0%, CLOAD=15pF)
0
-2
-40C
-4
25C
-6
85C
-8
-10
3.3
3.6
Attenuation (dB)
Attenuation (dB)
SSCLK Attenuation vs. VDD over Tem perature
(Measured at 7th Harmonic w ith Fnom=100MHz and
Spread=0.5%, CLOA D =15pF)
3
-10
-12
-14
-16
-18
-20
-40C
25C
85C
2.7
3.9
3
3.3
3.9
Max Cycle-Cycle Jitter on SSCLK vs.
Tem perature
(SSCLK=100MHz, VDD=3.3V, CLOAD=15pF, +/2%spread, REFCLK off)
SSCLK EMI Attenuation vs. Spread%
(Measured at 7th Harmonic Temp=25C, VDD=3.3V,
SSCLK=100MHz, Measured on Cypress
Characterization board w ith CLOAD=15pF)
0
200
-2
175
-4
150
Jitter (ps)
Attenuation (dB)
3.6
VDD (V)
VDD (V)
-6
-8
- 10
- 12
125
100
75
50
25
- 14
0
- 16
0.0%
3.9
VDD (V)
VDD (V)
2.7
3.6
0.5%
1.0%
1.5%
2.0%
2.5%
3.0%
Spread %
Document Number: 38-07499 Rev. *K
3.5%
4.0%
4.5%
5.0%
- 40
- 20
0
20
40
60
80
100
Tem perature (deg C)
Page 11 of 18
CY25100
Ordering Information
Ordering Code
Package Description
Product Flow
Pb-free
CY25100SXCF
8-pin SOIC
Commercial, 0 °C to 70 °C
CY25100SXCFT
8-pin SOIC – Tape and Reel
Commercial, 0 °C to 70 °C
CY25100SXIF
8-pin SOIC
Industrial, –40 °C to 85 °C
CY25100SXIFT
8-pin SOIC – Tape and Reel
Industrial, –40 °C to 85 °C
CY25100ZXCF
8-pin TSSOP
Commercial, 0 °C to 70 °C
CY25100ZXCFT
8-pin TSSOP – Tape and Reel
Commercial, 0 °C to 70 °C
CY25100ZXIF
8-pin TSSOP
Industrial, –40 °C to 85 °C
CY25100ZXIFT
8-pin TSSOP – Tape and Reel
Industrial, –40 °C to 85 °C
Programmer
CY3672-USB
Programmer, for devices with ordering codes ending in “F” and “FT”
CY3690
CY25100ZXCF/IF Adapter (TSSOP) for CY3672-USB Programmer
CY3691
CY25100SXCF/IF Adapter (SOIC) for CY3672-USB Programmer
Some product offerings are factory programmed customer specific devices with customized part numbers. The Possible
Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or Sales
Representative for more information.
Possible Configurations
Ordering Code
Package Description
Product Flow
CY25100ZIxxx[8, 9]
8-pin TSSOP
Industrial, –40 °C to 85 °C
CY25100ZIxxxT[8, 9]
8-pin TSSOP – Tape and Reel
Industrial, –40 °C to 85 °C
CY25100SXCxxx[8]
8-pin SOIC
Commercial, 0 °C to 70 °C
CY25100SXCxxxT[8]
8-pin SOIC – Tape and Reel
Commercial, 0 °C to 70 °C
CY25100SXIxxx[8]
8-pin SOIC
Industrial, –40 °C to 85 °C
CY25100SXIxxxT[8]
8-pin SOIC – Tape and Reel
Industrial, –40 °C to 85 °C
CY25100ZXCxx
8-pin TSSOP
Commercial, 0 °C to 70 °C
CY25100ZXCxxT[8]
8-pin TSSOP – Tape and Reel
Commercial, 0 °C to 70 °C
CY25100ZXIxx[8]
8-pin TSSOP
Industrial, –40 °C to 85 °C
CY25100ZXIxxT[8]
8-pin TSSOP – Tape and Reel
Industrial, –40 °C to 85 °C
Pb-free
[8]
Note
8. Ordering codes with “xxx” or “xx” are factory-programmed configurations. “xxx” or “xx” denotes the specific device configuration. “w” denotes the revision. Factory
programming is available for high-volume orders. For more details, contact your local Cypress field application engineer or Cypress Sales Representative.
9. Not recommended for new designs. New designs should use Pb-free devices.
Document Number: 38-07499 Rev. *K
Page 12 of 18
CY25100
Ordering Code Definitions
CY 25100 X
X
X
F
(xx, xxx)
T
T = Tape and Reel; blank = Tube
Custom configuration code (factory programmed device only)
Programming: F = field programmable; blank = factory programmed
Temperature Range: X = C or I
C = Commercial; I = Industrial
X = Pb-free package
Package Type: X = S or Z
S = 8-pin SOIC; Z = 8-pin TSSOP
Base part number
Company ID: CY = Cypress
Package Diagrams
Figure 7. 8-pin SOIC (150 Mils) S08.15/SZ08.15/SW815 Package Outline, 51-85066
51-85066 *F
Document Number: 38-07499 Rev. *K
Page 13 of 18
CY25100
Package Diagrams (continued)
Figure 7. 8-pin TSSOP (4.40 mm Body) Z08.173/ZZ08.173 Package Outline, 51-85093
51-85093 *E
Document Number: 38-07499 Rev. *K
Page 14 of 18
CY25100
Acronyms
Acronym
Document Conventions
Description
DC
Direct Current
EMI
Electromagnetic Interference
ESR
Equivalent Series Resistance
FAE
Field Application Engineer
JEDEC
Joint Electron Devices Engineering Council
OE
Output Enable
PCB
Printed Circuit Board
PD
Power Down
PLL
Phase Locked Loop
SOIC
Small Outline Integrated Circuit
SSC
Spread Spectrum Clock
SSCG
Spread Spectrum Clock Generator
TSSOP
Thin Shrunk Small Outline Package
Document Number: 38-07499 Rev. *K
Units of Measure
Symbol
Unit of Measure
°C
degree Celsius
kHz
kilohertz
MHz
megahertz
µA
microampere
µF
microfarad
mA
milliampere
mm
millimeter
ms
millisecond
mW
milliwatt
ns
nanosecond

ohm
%
percent
pF
picofarad
ps
picosecond
V
volt
Page 15 of 18
CY25100
Document History Page
Document Title: CY25100, Field and Factory Programmable Spread Spectrum Clock Generator for EMI Reduction
Document Number: 38-07499
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
126578
CKN
06/27/03
New data sheet.
*A
128753
IJATMP
08/29/03
Changes to reflect field programmability
*B
130342
RGL
12/02/03
Changes to Application Circuit diagram and correction to the package
description listed under the Ordering Information table for CY3690 and
CY3691.
*C
204121
RGL
See ECN
Add Industrial Temperature Range
Corrected the Ordering Information to match the DevMaster
*D
215392
RGL
See ECN
Added Lead Free devices
*E
2513909
AESA
06/10/08
Updated template. Added Note “Not recommended for new designs.”
Added part number CY25100KSXCF, CY25100KSXIF, CY25100KSXI-xxx,
CY25100KZXC-xxx, CY25100KZXI-xxx, CY25100KSXI-xxxT,
CY25100KZXC-xxxT, CY25100KZXI-xxxT, and CY25100KZXIF in ordering
information table.
Added Pb-Free header in the ordering information table.
Removed Pb-Free from Package description in the ordering information table.
Changed CY3672-PRG with CY3672-USB in the ordering information table.
Removed CY25100SCF, CY25100SIF, CY25100ZCF, CY25100ZIF, and
CY3672 in the ordering information table.
Changed Lead free to Pb-Free.
*F
2601881
KVM /
PYRS
11/06/08
Rising edge slew rate (SR3) minimum limit changed from 1.2 V/ns to 1.0 V/ns.
Removed part numbers added in rev *E.
*G
2742910
KVM
07/23/09
General text cleanup
Moved General Description to p. 1 to replace the Benefits section
Removed “FTG” from references to CY3672
Added “Type” column to Pin Description table
Revised software description section
Revised Modulation Frequency section to remove mention of optional
modulation frequencies
Added minimum values to IIH and IIL
Added to IOZ conditions: applies only for output pulldown disabled
Standardized timing parameter names to upper case
Corrected some part numbers to remove dashes and revision code
Added part numbers to the Ordering Information table: CY25100ZI-xxx,
CY25100ZI-xxxT, CY25100SXCFT, CY25100SXIFT, CY25100ZXCFT and
CY25100ZXIFT
Revised Ordering Information table footnotes
*H
2897317
KVM
03/22/10
Removed obsolete parts from Ordering Information table and moved ‘xxx’ parts
to Possible Configurations table
Updated package diagrams
*I
3366141
PURU
09/12/2011
Document Number: 38-07499 Rev. *K
Updated Logic Block Diagram.
Added Ordering Code Definitions.
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Updated in new template.
Page 16 of 18
CY25100
Document History Page (continued)
Document Title: CY25100, Field and Factory Programmable Spread Spectrum Clock Generator for EMI Reduction
Document Number: 38-07499
Rev.
ECN No.
Orig. of
Change
Submission
Date
*J
4108421
CINM
08/30/2013
Description of Change
Updated Package Diagrams:
spec 51-85066 – Changed revision from *E to *F.
spec 51-85093 – Changed revision from *C to *D.
Updated in new template.
Completing Sunset Review.
*K
4581659
TAVA
Document Number: 38-07499 Rev. *K
11/28/2014
Added related documentation hyperlink in page 1.
Updated package diagram.
Page 17 of 18
CY25100
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
cypress.com/go/memory
PSoC
cypress.com/go/psoc
Touch Sensing
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/go/touch
USB Controllers
Wireless/RF
psoc.cypress.com/solutions
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2003-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07499 Rev. *K
Revised November 28, 2014
CyberClocks is a trademark of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.
Page 18 of 18