CY25000 Programmable Spread Spectrum Clock Generator for EMI Reduction Features Benefits • Wide operating output (SSCLK) frequency range — 3–200 MHz • Programmable spread spectrum with nominal 30-kHz modulation frequency — Center spread: ±0.25% to ±2.5% — Down spread: –0.5% to –5.0% • Services most PC peripherals, networking, and consumer applications. • Provides wide range of spread percentages for maximum EMI reduction, to meet regulatory agency Electro Magnetic Compliance (EMC) requirements. Reduces development and manufacturing costs and time-to-market. • Eliminates the need for expensive and difficult to use higher order crystals. • Input frequency range — External crystal: 8–30 MHz fundamental crystals — External reference: 8–166 MHz Clock • Integrated phase-locked loop (PLL) • Programmable crystal load capacitor tuning array • Low cycle-to-cycle Jitter • Internal PLL to generate up to 200-MHz output. Able to generate custom frequencies from an external crystal or a driven source. • Enables fine-tuning of output clock frequency by adjusting CLoad of the crystal. Eliminates the need for external CLoad capacitors. • Suitable for most PC, consumer, and networking applications • 3.3V operation • Spread spectrum On/Off function • Power-down or Output Enable function • Application compatibility in standard and low-power systems. • Provides ability to enable or disable spread spectrum with an external pin. • Enables low-power state or output clocks to High-Z state. Logic Block Diagram XIN/CLKIN 1 OSC. PLL XOUT 8 CXOUT Pin Configuration with Modulation Control CXIN Programmable Configuration CY25000 8-pin SOIC Output Dividers and MUX 6 REFCLK 5 SSCLK PD#/OE 3 XIN/CLKIN 1 8 XOUT VDD 2 7 PD#/OE VSS 3 6 SSON REFCLK 4 5 SSCLK SSON 7 2 4 VDD VSS Cypress Semiconductor Corporation Document #: 38-07424 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised September 26, 2003 CY25000 Pin Descriptions Pin Name 1 XIN/CLKIN 2 VDD 3 PD#/OE 4 VSS Description Crystal input or reference clock input. 3.3V voltage supply. Power-down pin. Active LOW. If PD# = 0, SSCLK and REFCLK are three-stated. Output Enable pin: Active HIGH. If OE = 1, SSCLK and REFCLK are enabled. User has the option of choosing either PD# or OE function. GND. 5 SSCLK 6 REFCLK Spread spectrum clock output. 7 SSON Spread spectrum control. 1 = Spread on. 0 = Spread off. 8 XOUT Crystal output. Leave this pin floating if external clock is used. Buffered reference output. General Description The CY25000 is a Spread Spectrum Clock Generator (SSCG) IC used for the purpose of reducing Electro Magnetic Interference (EMI) found in today’s high-speed digital electronic systems. The device uses a Cypress-proprietary PLL and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the input clock. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies are greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory agency requirements (EMC) and improve time to market without degrading system performance. The CY25000 uses a factory-programmable configuration memory array to synthesize output frequency, spread %, crystal load capacitor, reference clock on/off and PD#/OE options. Document #: 38-07424 Rev. *B The spread % is factory programmed to either center spread or down spread with various spread percentages. The range for center spread is from ±0.25% to ±2.50%. The range for down spread is from –0.5% to –5.0%. Contact the factory for smaller or larger spread % amounts if required. The input to the CY25000 can be either a crystal or a clock signal. The input frequency range for crystals is 8–30 MHz, and for clock signals is 8–166 MHz. The CY25000 has two clock outputs, REFCLK and SSCLK. The non-spread spectrum REFCLK output has the same frequency as the input of the CY25000. The frequency modulated SSCLK output can be programmed from 3–200 MHz. The CY25000 products are available in an 8-pin SOIC (150-mil) package with a commercial operating temperature range of 0 to 70°C. Page 2 of 10 CY25000 Absolute Maximum Rating Junction Temperature ................................ –40°C to +125°C Data Retention @ Tj=125°C................................. > 10 Years Supply Voltage (VDD) ........................................–0.5 to +7.0V Package Power Dissipation...................................... 350 mW DC Input Voltage...................................... –0.5V to VDD + 0.5 Static Discharge Voltage.......................................... > 2000V (per MIL-STD-883, Method 3015) Storage Temperature (Non-Condensing) .... –55°C to +125°C Operating Conditions Parameter Description Min. Typ. Max. Unit 3.13 3.30 3.45 V 70 °C VDD Supply Voltage TA Ambient Temperature CLOAD Max. Load Capacitance @ pin 5 and pin 6 15 pF Fref External Reference Crystal (Fundamental tuned crystals only) 8 30 MHz External Reference Clock 8 166 MHz 0 FSSCLK SSCLK output frequency, CLOAD = 15 pF 3 200 MHz FREFCLK REFCLK output frequency, CLOAD = 15 pF 8 166 MHz tPU Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 500 ms DC Electrical Characteristics Parameter Description Condition Min. Typ. Max. Unit IOH Output High Current VOH = VDD – 0.5, VDD = 3.3V (source) 10 14 mA IOL Output Low Current VOL = 0.5, VDD= 3.3V (sink) 10 14 mA VIH Input High Voltage CMOS levels, 70% of VDD VIL Input Low Voltage CMOS levels, 30% of VDD IIH 0.7VDD V 0.3VDD V Input High Current, PD#/OE Vin = VDD and SSON pins 10 µA IIL Input Low Current, PD#/OE Vin = VSS and SSON pins 10 µA IOZ Output Leakage Current 10 µA CXIN/CXOUT[1, 2] Programmable Capacitance Capacitance at minimum setting at pin 1 and pin 8 Capacitance at maximum setting CIN[1] Input Capacitance at pin 3 and pin 7 Input pins excluding XIN and XOUT 5 7 pF IVDD Supply Current VDD = 3.45V, Fin = 30 MHz, REFCLK = 30 MHz, SSCLK = 66 MHz, CLOAD = 15 pF, PD#/OE = SSON = VDD 25 35 mA IDDS Stand by current VDD = 3.45V, Device powered down with PD#/OE = 0V 15 30 µA Three-state output, PD#/OE = 0 –10 12 pF 60 pF AC Electrical Characteristics[1] Parameter Min. Typ. Max. Unit Output Duty Cycle SSCLK, Measured at VDD/2 45 50 55 % Output Duty Cycle REFCLK, Measured at VDD/2 Duty Cycle of CLKIN = 50%. 40 50 60 % SR1 Rising Edge Slew Rate SSCLK from 3 to 100 MHz; REFCLK from 10 to 100 MHz. 20%–80% of VDD 0.7 1.1 1.5 V/ns SR2 Falling Edge Slew Rate SSCLK from 3 to 100 MHz; REFCLK from 10 to 100 MHz. 80%–20% of VDD 0.7 1.1 1.5 V/ns DC Description Condition Notes: 1. Guaranteed by characterization, not 100% tested. 2. Contact factory for desired crystal load programming. Document #: 38-07424 Rev. *B Page 3 of 10 CY25000 AC Electrical Characteristics[1] Min. Typ. Max. Unit SR3 Parameter Rising Edge Slew Rate Description SSCLK from 100 to 200 MHz; REFCLK from 100 to 166 MHz 20%–80% of VDD Condition 1.2 1.6 2.0 V/ns SR4 Falling Edge Slew Rate SSCLK from 100 to 200 MHz; REFCLK from 100 to 166 MHz 80%–20% of VDD 1.2 1.6 2.0 V/ns tj1 Peak Cycle-to-Cycle Jitter. SSCLK pin SSCLK = 200 MHz. Spread on 100 200 ps SSCLK = 66 MHz. Spread on 150 300 ps SSCLK = 14.3 MHz. Spread on 200 400 ps tj2 Peak Cycle-to-Cycle Jitter, REFCLK REFCLK output only 100 200 ps tSTP Power-down Time (pin3 = PD#) Time from falling edge on PD# to stopped outputs (Asynchronous) 150 300 ns TOE1 Output Disable Time (pin3 = OE) Time from falling edge on OE to stopped outputs (Asynchronous) 150 300 ns TOE2 Output Enable Time (pin3 = OE) Time from rising edge on OE to outputs at a valid frequency (Asynchronous) 150 300 ns tPU1 Power-up Time, Crystal is used Time from rising edge on PD# to outputs at valid frequency (Asynchronous) 3 5 ms tPU2 Power-up Time, Reference clock is used Time from rising edge on PD# to outputs at valid frequency (Asynchronous) 2 3 ms Table 1. Pin Function Input Frequency CXIN and CXOUT Output Frequency Spread Percent Reference Output Power-down or Output Enable Frequency Modulation Pin Name XIN and XOUT XIN and XOUT SSCLK SSCLK REFOUT PD#/OE SSCLK Pin# 1 and 8 1 and 8 5 5 6 3 5 Units MHz pF MHz % On or Off Select PD# or OE kHz PROGRAM VALUE ENTER DATA ENTER DATA ENTER DATA ENTER DATA 30 ENTER DATA ENTER DATA Programming Description The customers planning to use the CY25000 need to provide the programming information described as “ENTER DATA” in Table 1 and should contact local Cypress Sales. Additional information on the CY25000 can be obtained from the Cypress web site at www.cypress.com. CXIN = CXOUT = 2CL - CP Where CL is the crystal load capacitor as specified by the crystal manufacturer and CP is the parasitic PCB capacitance. For example, if a fundamental 16-MHz crystal with CL of 16 pF is used and CP is 2 pF, CXIN and CXOUT can be calculated as: CXIN = CXOUT = (2 x 16) – 2 = 30 pF. Product Functions If using a driven reference, set CXIN and CXOUT to the minimum value 12 pF. Input Frequency (XIN, pin 1 and XOUT, pin 8) Output Frequency, SSCLK Output (SSCLK, pin 5) The input to the CY25000 can be a crystal or a clock. The input frequency range for crystals is 8 to 30 MHz, and for clock signal is 8 to 166 MHz. The modulated frequency at the SSCLK output is produced by synthesizing the input reference clock. The modulation can be stopped by SSON digital control input (SSON = LOW, no modulation). If modulation is stopped, the clock frequency is the nominal value of the synthesized frequency without modulation (spread % = 0). The range of synthesized clock is from 3–200 MHz. CXIN and CXOUT (pin 1 and pin 8) The load capacitors at pin 1 (CXIN) and pin 8 (CXOUT) can be programmed from 12 pF to 60 pF with 0.5-pF increments. The programmed value of these on-chip crystal load capacitors are the same (XIN = XOUT = 12 to 60 pF). The required values of CXIN and CXOUT can be calculated using the following formula: Document #: 38-07424 Rev. *B Spread Percentage (SSCLK, pin 5) The SSCLK frequency can be programmed at any percentage value from ±0.25% to ±2.5% for Center Spread and from –0.5% to –5.0% Down Spread. Page 4 of 10 CY25000 Reference Output (REFOUT, pin 6) Frequency Modulation The reference clock output has the same frequency and the same phase as the input clock. This output can be programmed to be enabled (clock on) or disabled (High-Z, clock off). If this output is not needed, it is recommended that users request the disabled (High-Z, Clock Off) option. The frequency modulation is programmed at 30 kHz for all SSCLK frequencies from 3 to 200 MHz. Contact the factory if a higher modulation frequency is required. Power-down or Output Enable (PD# or OE, pin 3): Users can select either PD# or OE function which are also factory programmable. Application Circuit[3, 4, 5] Crystal Power XOUT XIN 1 VDD PD#/OE VSS 2 3 4 CY25000 VDD 0.1µF 8 7 SSON 6 REFCLK 5 SSCLK VDD Switching Waveforms Duty Cycle Timing (DC = t1A/t1B) t1A OUTPUT t1B Output Rise/Fall Time (SSCLK and REFCLK) VDD OUTPUT 0V Tr Tf Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3) Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4) Refer to AC Electrical Characteristics table for SR (Slew Rate) values. Power-down Timing and Power-up Timing POWERDOWN VDD 0V VIH VIL tPU High Impedance CLKOUT (Asynchronous) tSTP Notes: 3. Since the load capacitors (CXIN and CXOUT) are provided by the CY25000, no external capacitors are needed on the XIN and XOUT pins to match the crystal load capacitor (CL). Only a single 0.1-µF bypass capacitor is required on the VDD pin. 4. If an external clock is used, apply the clock to XIN (pin 1) and leave XOUT (pin 8) floating (unconnected). 5. If SSON (pin 7) is LOW (VSS), the frequency modulation will be stopped on SSCLK pin (pin 5). Document #: 38-07424 Rev. *B Page 5 of 10 CY25000 Switching Waveforms (continued) Output Enable/Disable Timing OUTPUT ENABLE VDD VIH VIL 0V TOE2 High Impedance CLKOUT (Asynchronous ) TOE1 Informational Graphs 172.5 161.5 169.5 169 168.5 168 167.5 167 166.5 166 165.5 165 164.5 164 163.5 163 160.5 162.5 171.5 Spread Spectrum Profile: Fnom=166MHz, Fmod=30kHz, Spread%= -4% 170.5 169.5 168.5 167.5 166.5 Fnominal 165.5 164.5 163.5 162.5 159.5 0 20 68.5 40 60 80 100 120 Time (us) 140 160 180 Fnominal 0 200 Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= -4% 68 Spread Spectrum Profile: Fnom=166MHz, Fmod=30kHz, Spread%= +/-1% 20 67.5 40 60 80 100 120 Time (us) 140 160 180 200 Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= +/-1% 67 67.5 67 66.5 66.5 Fnominal 66 Fnominal 66 65.5 65.5 65 64.5 65 64 64.5 63.5 0 20 40 60 80 100 120 Time (us) Document #: 38-07424 Rev. *B 140 160 180 200 0 20 40 60 80 100 120 Time (us) 140 160 180 200 Page 6 of 10 CY25000 Informational Graphs (continued) Duty Cycle vs. REFCLK (VDD=3.0V, Temperature=25C, CLOAD = 15pF) IDD vs. SSCLK Temperature=25C, VDD=3.3V, CLOAD=15pF 60 70 58 60 Duty Cycle (%) 56 54 50 52 40 50 30 48 20 46 10 44 0 42 0 40 0 50 100 150 50 100 150 200 SSC LK (M H z) 200 250 REFCLK=SSCLK REFCLK=30MHz REFCLK (MHz) Measured Spread% vs. VDD over Tem perature (Target Spread = 0.5%, Fout=100MHz, CLOA D =15pF) Measured Spread% vs. VDD over Tem perature (Target Spread = 5.0%, Fout=100MHz, CLOA D =15pF) 0.55% -40C 0.50% 25C 0.45% 85C 6.00% Spread% Spread% 0.60% 5.50% -40C 5.00% 25C 4.50% 85C 4.00% 0.40% 2.7 3 3.3 3.6 2.7 3.9 3 0 -2 -40C -4 25C -6 85C -8 -10 3.3 VDD (V) Document #: 38-07424 Rev. *B 3.9 SSCLK Attenduation vs. VDD over Tem perature (Measured at 7th Harmonic w ith Fnom=100MHz and Spread=5.0%, CLOAD=15pF) 3.6 3.9 Attenuation (dB) Attenuation (dB) SSCLK Attenduation vs. VDD over Tem perature (Measured at 7th Harmonic w ith Fnom=100MHz and Spread=0.5%, CLOA D =15pF) 3 3.6 VDD (V) VDD (V) 2.7 3.3 -10 -12 -14 -16 -18 -20 -40C 25C 85C 2.7 3 3.3 3.6 3.9 VDD (V) Page 7 of 10 CY25000 Informational Graphs (continued) Max Cycle-Cycle Jitter on SSCLK vs. Tem perature (SSCLK=100MHz, VDD=3.3V, CLOAD=15pF) SSCLK Attenuation vs. Spread% (Temp=25C, VDD=3.3V, SSCLK=100MHz, Measured on Cypress Characterization board w ith CLOAD=15pF) 200 0 175 -2 150 -4 125 -6 100 -8 75 -10 50 -12 25 -14 0 -16 0.0% 0.5% 1.0% 1.5% 2.0% 2.5% 3.0% 3.5% 4.0% 4.5% -60 5.0% -40 - 20 0 20 40 60 80 100 T e m p ( de g C ) S pre a d % Custom Configuration Request Procedure The CY25000 is a memory programmable device that is configured in the factory. All requests must be submitted to the local Cypress Field Application Engineer (FAE) or sales representative. A sample request form (refer to “CY25000 Sample Request Form” at www.cypress.com) must be completed. Once the request has been processed, you will receive a new part number, samples and data sheet with the programmed values. This part number will be used for additional sample requests and production orders. Ordering Information Part Number[6] Package Type Product Flow CY25XXXSC-W 8-pin Small Outline Integrated Circuit (SOIC) Commercial, 0 to 70°C CY25XXXSC-WT 8-pin Small Outline Integrated Circuit (SOIC)–Tape and Reel Commercial, 0 to 70°C Document #: 38-07424 Rev. *B Page 8 of 10 CY25000 Package Drawing and Dimensions 8 Lead (150 Mil) SOIC -8-lead S08 (150-Mil) SOIC S8 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0138[0.350] 0.0192[0.487] 0.0075[0.190] 0.0098[0.249] 51-85066-*C Note: 6. “XXX” denotes the assigned product number. “W” denotes the different programmed spread % values. The user can request different spread % values. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07424 Rev. *B Page 9 of 10 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY25000 Document History Page Document Title: CY25000 Programmable Spread Spectrum Clock Generator for EMI Reduction Document Number: 38-07424 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 115076 06/20/02 CKN New Data Sheet *A 121901 12/14/02 RBI Power-up requirements added to Operating Conditions Information *B 129855 10/01/03 RGL Removed “PRELIMINARY” Changed IOH and IOL min. from 12 mA to 10 mA and typical from 24 mA to 14 mA Document #: 38-07424 Rev. *B Page 10 of 10