AN49576 Interfacing ADMUX SRAM Processors to West Bridge® Antioch™ Author: Hingkwan Huen Associated Project: No Associated Part Family: CYWB0124AB Software Version: Antioch™ SDK Version 1.3.2 Related Application Notes: None Cypress West Bridge® Antioch™ provides High-Speed USB peripheral and mass storage control capabilities to the host processor through its host Processor-port (P-port). This application note presents a physical interconnect example of interfacing a host processor with an address data multiplexed (ADMUX) SRAM interface to Antioch, using Antioch’s Pseudo-CRAM P-port interface. Contents Introduction Introduction ....................................................................... 1 West Bridge® Antioch™ Overview..................................... 2 Antioch P-Port Interface .................................................... 2 Interface to ADMUX SRAM ............................................... 3 Host Processor External Memory Controller Configuration .......................................................................................... 3 Clocking........................................................................ 3 Register Configurations ................................................ 3 Timing Analysis and Recommendations ...................... 5 Summary ........................................................................... 9 Additional Resources ........................................................ 9 Worldwide Sales and Design Support ............................. 11 The rapid growth of the mobile and embedded device market demands new features and capabilities such as High-Speed USB connectivity and support for the latest mass storage devices. However, the system processor cannot keep in pace with the high speed evolution of new technologies and standards. Cypress West Bridge® Antioch™ (CYBW0124AB) device is the solution to this discrepancy. It is designed to enable handset designers easily add new functionalities in their designs. When Antioch is integrated into a system, its Processorport (P-port) interface is used to connect to the system bus of the host processor. The P-port on Antioch supports a conventional interface similar to a SRAM that is compatible with many commonly used embedded processors. This application note discusses how a system processor can interface to Antioch through Antioch’s P-port interface. A host processor with an ADMUX SRAM memory interface is used as an example. Note that West Bridge Astoria™ natively supports an ADMUX SRAM interface. Further information can be found in the West Bridge Astoria datasheet. www.cypress.com Document No. 001-49576 Rev. *C 1 ® Interfacing ADMUX SRAM Processors to West Bridge Antioch™ West Bridge® Antioch™ Overview The West Bridge family of controllers uses robust Simultaneous Link to Independent Multimedia (SLIM™) architecture. This provides simultaneous and independent data paths between the processor and USB, USB and mass storage, and processor and mass storage. Antioch is the first device in the West Bridge device family available to the market. Table 1. Antioch P-Port Interface Signals P-port Signal Name I/O Function CLK I Interface Clock Input CE# I Chip Enable A[7:0] I Address Bus DQ[15:0] IO Data Bus ADV# I Address Latch Enable OE# I Read Enable WE# I Write Enable INT# O Antioch Device Interrupt DRQ# O DMA Request This pin is optional if the processor GPIO resource is limited. DACK# I DMA Acknowledgement This pin is optional if the processor GPIO resource is limited. As shown in Figure 1, Antioch has three independent ports: the Processor-port (P-port), the USB-port (U-port), and the mass Storage-port (S-port). The P-port of Antioch is a conventional interface similar to a SRAM that enables synchronous and asynchronous access to endpoint buffers and configuration registers. The U-port is a High-Speed USB peripheral interface with a built in transceiver that enables independent UP and US data transfers with optimal performance. The S-port can be configured to simultaneously interface with multiple mass storage devices such as 8 or 16-bit raw SLC NAND, controlled NAND, SD/MMC/MMC+, and CE-ATA devices. Figure 1. West Bridge Antioch Block Diagram West Bridge Antioch Processor Interface P 8051 MCU High-Speed USB 2.0 XCVR Control Registers U SLIMTM Mass Storage Interface SD/MMC+/CE-ATA Comments NAND Maximum frequency is 33 MHz in synchronous mode. This pin is not needed in asynchronous mode. This pin is not available for WLCSP package. A0 is 16-bit aligned address. S For a full description of Antioch’s features, see West Bridge Antioch CYWB0124AB device datasheet. Antioch P-Port Interface The P-port interface of Antioch is similar to a SRAM interface designed for a simple connection with embedded host processors. Table 1 lists the Antioch P-port signals that need to be considered when connecting to a processor with ADMUX SRAM memory interface. www.cypress.com Antioch P-port supports both synchronous and asynchronous modes. The operating mode is selected based on the P-port interface configuration register and is default in asynchronous mode. Note that the CLK pin is not available in wafer level chip scale package (WLCSP). In that case, P-port of Antioch in WLCSP only supports asynchronous accesses. Document No. 001-49576 Rev. *C 2 ® Interfacing ADMUX SRAM Processors to West Bridge Antioch™ Interface to ADMUX SRAM An ADMUX SRAM interface is compatible with Antioch’s P-port interface, although its native mode of operation multiplexes address and data lines on the same I/O bus. When connecting Antioch’s P-port with dedicated address and data buses to a multiplexed address and data interface, note the following: In data phase of the access cycle, data bus also drives the Antioch’s address bus. This may latch incorrect address for subsequent access cycles. This is not the case for Antioch, because it enables distinct address cycle when ADV# signal is at logic low. As long as the processor waveform meets timing for address latch cycle (namely tAVS, tAVH and tVP), the value driven on Antioch’s address bus during the data phase is ignored. During a read operation, the address lines may still be driven by the processor when data is already available from Antioch. This causes bus contention when both the processor and Antioch are trying to drive on the same bus. Avoid this situation by ensuring proper register configuration of the processor’s external memory controller. The timing analysis presented in subsequent sections of this application note covers these two cases. Most processors’ external memory controller enables seamless connection to Antioch’s P-port. Figure 2 shows a connection example between a host processor with ADMUX SRAM interface and Antioch. Figure 2. Connection Example of a Host Processor with Antioch’s P-Port MEM_CLK Host Processor External Memory Controller Configuration Clocking For both asynchronous and synchronous modes, all external memory control signals are referenced to an internal reference clock (HCLK). The maximum frequency (minimum period) is defined by software, and HCLK is a fractional multiple of the TCXO frequency created by an internal PLL. The control of the circuitry is determined by feature #defines within the software. Assuming the following specifications for HCLK: Typical HCLK frequency = 48 MHz That is, HCLK period = 21 ns In the synchronous mode, the active I/O clock derived from HCLK is output on the CLK pin. This application note assumes that the frequencies of HCLK and CLK are the same. In asynchronous mode, the CLK pin is driven inactive low, although the clock signal is still used as an internal reference to program the different control signals. This application note focuses on asynchronous single access mode of operation. Register Configurations To correctly interface a sample host processor with ADMUX SRAM interface to Antioch, two main memory controller registers must be configured: Fast_CSn_CFG1 and Slow_CSn_CFG0. Table 2 shows the relevant bit fields for both registers. These registers define the interface timing for the Antioch device. CLK ADV_N ADV# WE_N WE# OE_N OE# CSx_N CE# GPIOx INT# West Bridge Antioch DQ[15:0] P-Port A_D[15:0] U-Port Host Processor External Memory Controller A[15:0] High Speed USB S-Port NAND/SD/MMC/ CE-ATA www.cypress.com Document No. 001-49576 Rev. *C 3 ® Interfacing ADMUX SRAM Processors to West Bridge Antioch™ Table 2. Memory Controller Register Definitions Register Name Bit Symbol Field Description Recommended Value Fast_CSn_CFG1 5 ah ADDR_HOLD_ENA The address is held for an extra cycle to meet hold time requirements with ADV_N. Upon reset, this bit initializes to 0. 0b1 This bit field indicates the number of cycles elapsed before an OE_N assertion. The reference is with respect to the cycle in which AVD_N is asserted. For example, a value of 2 implies 2 cycles between ADV_N deassertion and OE_N assertion. Reset value is 0x00. 0b01 Fast_CSn_CFG1 Slow_CSn_CFG0 Fast_CSn_CFG1 17:16 27:24 27:24 aor h h ADV_OE_RECOVERY WR_HOLD Write hold. This field specifies the length of the third segment of a write transfer. For example, in a single write transfer, this corresponds to the period from the time that WE_N goes high to the time that CS_N goes high. Power-on default is 0x0. 0b0001 RD_HOLD Read hold. This field applies to ANY read transfers that are not caused by the ID_fetch command. It specifies the length of the first segment of the read transfer. For example, in a single read transfer, this corresponds to the period from the time CS_N goes low to the time OE_N goes low. Power-on default is 0x0. 0b0001 Slow_CSn_CFG0 7:4 w WR_WAIT Slow _CSn_CFG0 3:0 w RD_WAIT These bits determine the number of waitstates incurred in every write access. If BURST_WR_ENA is set (1): * The first access to a page mode memory incurs WR_DELTA + (WR_WAIT + 1) cycles. * Subsequent accesses to a page mode memory incur WAIT_WR + 1 cycles. Reset value is 0x00. These bits determine the number of waitstates incurred in every read access. If PAGE_RD_ENA or BURST_RD_ENA is set (1): * The first access to a page incurs RD_DELTA + (RD_WAIT + 1) cycles. * Subsequent accesses incur WAIT_RD + 1 cycles. Reset value is 0x00 0b0010 0b0011 Initial latency write. These bits determine the number of extra (delta) cycles inserted in the first write access to a page or burst memory. Slow _CSn_CFG0 23:16 i WR_DELTA Upon reset, the delta cycles are inserted in every access to the memory. If CS0 is enabled for Burst accesses, the delta cycles are inserted only in the first access to memory. A minimum value of 1 must be programmed on this bit field. 0x0 Reset value is 0x0F. www.cypress.com Document No. 001-49576 Rev. *C 4 ® Interfacing ADMUX SRAM Processors to West Bridge Antioch™ Register Name Bit Symbol Field Description Recommended Value Initial latency read. These bits determine the number of extra (delta) cycles inserted in the first read access to a page or burst memory. Slow_CSn_CFG0 15:18 i RD_DELTA Upon reset, the delta cycles are inserted in every access to the memory. If CS0 is enabled for Page or Burst accesses, the delta cycles are inserted only in the first access to memory. 0x0 Reset value is 0x0C. Recovery. This bit field determines how many recovery cycles are inserted from the time the current chip-select is deasserted after a read access to the assertion of the next chip-select. This provides more data recovery time and avoids bus contention. A recovery cycle is an extra cycle inserted in the beginning of the data phase of the next transfer. The chip-select and read and write enable signals are delayed after the recovery cycles. The recovery cycles are inserted under the following conditions: CASE 1: Chip-select turnover Slow _CSn_CFG0 31:28 r RECOVERY 1. The following chip-select signal is different from the current one. 2. The current access to the external memory is a read. CASE 2: Read followed by a write on the same chip-select. 1. The following chip-select signal is the same as the current one. 2. The current access is a read, and the following access is a write. 0x0001 The maximum number of programmable values to this bit field is 15 for 15 cycles of recovery time. Program 0 if the device speed is fast enough (or bus clock speed is slow enough) to eliminate the need for a recovery cycle. The configuration of the bit field is per chip-select basis so you can program device dependent information to the bit field of the configuration register for each chip-select. For a bus-sized transfer, this bit field only affects the first. Reset value is 0x03. Note Recommended value is set based on timing analysis listed in Table 5 on page 8. Timing Analysis and Recommendations This section provides a timing analysis summary between the sample host processor and Antioch. Table 3 lists the interface timing specifications. Specification values are converted in terms of timing register values for easier calculation of the recommended final program values. www.cypress.com Table 4 lists the Antioch P-port interface timing specifications defined in the Antioch device datasheet. An accurate one-to-one comparison is necessary between the actual host processor interface and Antioch P-port waveforms. This application note provides an example of this analysis. Figure 3 and Figure 4 show two cases that highlight all the required timings. Document No. 001-49576 Rev. *C 5 ® Interfacing ADMUX SRAM Processors to West Bridge Antioch™ Table 5 lists the compatible timing parameters and calculations for the required register configurations. The precautions needed for connecting dedicated address and data buses to a multiplexed address and data interface are described in the timing analysis and avoided with the suggested register settings. To determine throughput and optimization of the interface with a particular processor, contact your local Cypress sales representative. Table 3. Memory Controller Interface Timing Specifications Sample Processor Specification Memory Controller Parameter Description Min (ns) Max (ns) (w+i+h+1)T+/-da - Write Cycle t(csvw) Write cycle chip-select active t(csw) Chip-select active to write active T+/-da - Chip-select active to data valid T+/-da - (w+i)T+/-da - (h)T+/-da - (1+ah)T+/-da - (w+i)T+/-da - (h)T+/-da - (1+ah)T+/-da - (w+i)T+/-da - t(cswdv) t(w) Write active t(wcs) Write inactive to chip-select inactive t(avw) Write cycle address valid t(ws) Write cycle data setup t(wh) Write data hold t(avr) Read cycle address valid Read Cycle t(r) Read active t(csvr) Read cycle chip-select active (w+i+1)T+/-da - t(csr) Chip-select active to read active (1+aor)T+/-da - t(csi) Chip-select inactive (r)T+/-da - t(oeh) Read inactive to chip-select inactive (h)T+/-da - t(rh) Read-data hold 0 - t(rs) Read-data setup 20 - Note T = HCLK Period, that is, 21 ns. Note da = 3 ns. This parameter defines the skew measured with respect to two signals. www.cypress.com Document No. 001-49576 Rev. *C 6 ® Interfacing ADMUX SRAM Processors to West Bridge Antioch™ Table 4. Antioch P-Port Interface Timing Specifications Antioch Specification Antioch Parameter Description Min (ns) Max (ns) tAVS Address Valid to ADV# High 5 - tAVH ADV# High to Address Hold 2 - tCVS CE# Low Setup to ADV# High 5 - tVP ADV# Low Pulse Width 7.5 - tEA CE# Low to Data Valid - 30 tOE OE# Low to Data Valid - 22.5 tOLZ OE# Low to Data Low-Z 3 - tOHZ OE# High to Data High-Z 0 22.5 tWP WE# Low Pulse Width 22 - tWPH WE# High Pulse Width 10 - tCW CE# Low to Write End 30 - tAW Address Valid to Write End 30 tDW Data Setup 18 tDH Data Hold 0 Figure 3. Asynchronous Single Read Timing (Antioch versus Sample Processor) www.cypress.com Document No. 001-49576 Rev. *C 7 ® Interfacing ADMUX SRAM Processors to West Bridge Antioch™ Figure 4. Asynchronous Single Write Timing (Antioch versus Sample Processor) Table 5. Antioch and Sample Processor Timing Analysis and Calculations Timing Antioch Name Description Sample Processor Parameter Recommended Configuration tEA-tOE+t(r)+tOHZ < t(csvr)+t(csi) tEA - tOE+ OE# Low pulse + tOHZ => 30-22.5+(w+i)*T+da+22.5 < (w+i+1)*T-da +r*T-da Read Cycle Time t(csvr)+t(csi) => 30<(r+1)*T-3*da => 30<(r+1)*21-9 => r = 1 tEA-tOE < (1+aor)*T-da => 30-22.5 < (1+aor)*21-3 Read Parameters tEA -tOE CE# Low to OE# Low t(csr) => aor = 0 However, aor must increase to 1 to avoid contention. t(r)-tOE+2*1 > t(rs) OE# Low pulse- tOE + 2*board_delay DQ output setup to OE# High t(rs) => (w+i)*T-da - 22.5 +2 > 20 => (w+i)*21-3-22.5+2>20 => i = 0; w = 3 tOHZ + 2*board_delay OE# High to DQ Hold tWPH + tWP Write Cycle Time t(rh) tOHZ+2*1 > 0 Condition always met. tWPH+tWP < (w+i+h+1)*T-da t(csvw) => 22+10 < (w+i+h+1)*21-3 => i=0; w=2; h=1 tCW-tAW < T-da tCW - tAW CE# Low to WE# Low t(csw) tAW WE# Low pulse width t(w) Write Parameters => 30-30 < 21-3; Condition always met. tAW < (w+i)*T-da => 30 < (w+i)*21-3 => i=0; w=2 tDW < (w+i)*T-da tDW DQ input setup t(ws) => 18 < (w+i)*21-3 => i=0; w=2 www.cypress.com Document No. 001-49576 Rev. *C 8 ® Interfacing ADMUX SRAM Processors to West Bridge Antioch™ Timing Antioch Name Sample Processor Parameter Description Recommended Configuration tDH < h*T-da tDH DQ input hold t(wh) => 0 < h*21-3 => h=1 tAVS Address valid to ADV# High T (i.e. 1 HCLK Cycle) tAVH ADV# High to Address hold t(avr) - T HCLK=21ns; tAVS=5ns; Condition always met. tAVH < (1+ah)*T-da-T Common for both Read and Write => 2 < (1+ah)*21-3-21 => ah = 1 tCVS CE# Low to ADV# HIGH T (i.e. 1 HCLK Cycle) HCLK=21ns; tCVS=5ns; Condition always met. tVP ADV# Low Pulse Width T (i.e. 1 HCLK Cycle) HCLK=21ns; tVP=7.5ns; Condition always met. Note Assume board delay of 1 ns. Note It requires t(csr) - tOLZ >= t(avr) to avoid data contention during read operation. That is, (1+aor)*T-da-3>= (1+ah)*T+da, based on calculation ah=1 and aor=0, which fails the condition. The aor value must increase by one cycle to avoid contention. Summary Additional Resources West Bridge Antioch can easily interconnect with host processors through ADMUX SRAM memory interface. The timing analysis described in this application note lists the modes of operation supported with Antioch. The Antioch feature set is a perfect solution for host processors to enable new High-Speed USB peripheral connectivity and storage control options for the latest mass storage devices. It also completely offloads the processor from the USB mass storage access, resulting in higher performance and more efficient system design. www.cypress.com West Bridge® Antioch Advance Datasheet. ® West Bridge Astoria Advance Datasheet. Document No. 001-49576 Rev. *C 9 ® Interfacing ADMUX SRAM Processors to West Bridge Antioch™ Document History Document Title: Interfacing ADMUX SRAM Processors to West Bridge® Antioch™ - AN49576 Document Number: 001-49576 Revision ECN Orig. of Change Submission Date Description of Change ** 2590750 HKH 10/16/2008 New Application Note. *A 3183676 ANOP 02/25/2011 Added a note in Introduction section. Added Additional Resources section. *B 3426442 AASI 10/31/2011 Updated to new template. Completing Sunset Review. *C 4556630 PRJI 10/30/2014 Updated to new template. Completing Sunset Review. www.cypress.com Document No. 001-49576 Rev. *C 10 ® Interfacing ADMUX SRAM Processors to West Bridge Antioch™ Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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