INTEGRATED CIRCUITS PDI1394P11A 3-port physical layer interface Preliminary specification 1999 Mar 10 Philips Semiconductors Preliminary specification 3-port physical layer interface PDI1394P11A 1.0 FEATURES 2.0 DESCRIPTION • 3 cable interface ports • Supports 100Mb/s and 200Mb/s transfers • Interfaces to any 1394 standard Link Layer Controller • 5V tolerant I/Os with Bus Hold Circuitry • Single 3.3V supply voltage • Arbitrated (short) Bus Reset (1394a feature) • Fully compatible with existing 100 Mbps Phys on the market • Prevents a TpBias voltage driven into a non-powered The Philips Semiconductors PDI1394P11A is an IEEE1394-1995 compliant Physical Layer interface. The PDI1394P11A provides the analog physical layer functions needed to implement a three port node in a cable-based IEEE 1394–1995 network. Additionally, the device manages bus initialization and arbitration cycles, as well as transmission and reception of data bits. The Link Layer Controller interface is compatible with both 3V and 5V Link Controllers. While providing a maximum transmission data rate of 200 Mb/s, the PDI1394P11A is compatible with current 100 Mb/s Physical Layer ICs. The PDI1394P11A is available in the LQFP64 package. PDI1394P11A from erroneously powering up the part 3.0 ORDERING INFORMATION PACKAGE TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 0°C to +70°C PDI1394P11A BD PD1394P11A BD SOT314-2 64-pin plastic LQFP AVDD AGND 49 PLLGND 52 AGND PLLGND 53 50 FILTER 54 51 XI AVDD 55 XO 56 57 R1 60 R0 AGND 61 PLLVDD ISO– 62 58 DGND 63 59 DGND 64 4.0 PIN CONFIGURATION RESET– 1 48 TPBIAS3 LPS 2 47 TPBIAS2 LREQ 3 46 TPBIAS1 DVDD 4 45 TPA1+ DVDD 5 44 TPA1– DVDD 6 43 TPB1+ PD 7 42 TPB1– DGND 8 41 AGND SYSCLK 9 40 TPA2+ DGND 10 39 TPA2– CTL0 11 38 TPB2+ CTL1 12 37 TPB2– D0 13 36 TPA3+ D1 14 35 TPA3– D2 15 34 TPB3+ D3 16 33 TPB3– 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DGND DGND DVDD DVDD TESTM2 TESTM1 CPS AVDD AVDD AGND C/LKON PC2 PC1 PC0 CNA AGND PDI1394P11A SV01073 1999 Mar 10 2 Philips Semiconductors Preliminary specification 3-port physical layer interface PDI1394P11A 5.0 PIN DESCRIPTION PIN NUMBER PIN SYMBOL I/O NAME AND FUNCTION 1 RESET– I* Phy reset, active LOW 2 LPS I* Link Layer Controller (LLC) power status 3 LREQ I* Link request from controller 4 DVDD I* Should be connected to the LLC VDD supply when a 5V LLC is connected to the Phy, and should be connected to the Phy DVDD when a 3V LLC is used. 5, 6, 19, 20 DVDDD I Digital circuit power 7 PD I* Device power down input 8, 10, 17, 18, 63, 64 DGND – Digital circuit ground 9 SYSCLK O* 49.152 MHz clock to link controller 11, 12 CTL[0:1] I/O* Link interface bi-directional control signals 13, 14, 15, 16 D[0:3] I/O* Link interface bi-directional data signals 22, 21 TESTM[1:2] I* Test/Mode Control pins 11 =1394–1995 mode 10 = 1394a mode 00/01 = Reserved 23 CPS I Cable power status 24, 25, 51, 55 AVDD – Analog circuit power 26, 32, 41, 49, 50, 61 AGND – Analog circuit ground 27 C/LKON I/O* Bus/Isochronous Resource Manager capable input, or LINK-ON signal output 30, 29, 28 PC[0:2] I* Power class bits 0 through 2 inputs 31 CNA O* Cable Not Active output 36, 40, 45 TPA[1:3]+ I/O Port n cable pair A, positive signal 35, 39, 44 TPA[1:3]– I/O Port n cable pair A, negative signal 34, 38, 43 TPB[1:3]+ I/O Port n cable pair B, positive signal 33, 37, 42 TPB[1:3]– I/O Port n cable pair B, negative signal 46, 47, 48 TPBIAS[1:3] O Cable termination voltage supplies 52, 53 PLLGND – PLL circuit ground 54 FILTER I/O PLL external filter capacitor 56 XI I Crystal oscillator connection 57 XO O Crystal oscillator connection 58 PLLVDD – PLL circuit power 59, 60 R[0:1] – External current setting resistor 62 ISO– I* Link interface isolation status input NOTE: * Indicates 5V tolerant structure. 1999 Mar 10 3 Philips Semiconductors Preliminary specification 3-port physical layer interface PDI1394P11A 6.0 BLOCK DIAGRAM R0 CPS BIAS VOLTAGE AND CURRENT GENERATOR RECEIVED DATA DECODER/ TIMER LPS ISO– CNA R1 TPBIAS1 TPBIAS2 TPBIAS3 SYSCLK LREQ PORT 1 LINK INTERFACE TPA1+ TPA1– CTL0 CTL1 D0 D1 TPB1+ TPB1– D2 D3 PC0 PC1 ARBITRATION AND CONTROL STATE MACHINE LOGIC PC2 TPA2+ TPA2– PORT 2 C/LKON TPB2+ TPB2– TESTM1 TPA3+ TPA3– PORT 3 TESTM2 RESET– TPB3+ TPB3– TRANSMIT DATA ENCODER CRYSTAL OSCILLATOR PLL SYSTEM & TRANSMIT CLOCK GENERATOR XI XO FILTER PD SV00228 monitor conditions on the cable to determine connection status, data speed, and bus arbitration states. 7.0 FUNCTIONAL SPECIFICATION The PDI1394P11A is an IEEE1394–1995 High Performance Serial Bus Specification compliant physical layer interface device. It provides an interface between an attached link layer controller and three 1394 cable interface ports. In addition to the interface function, the PDI1394P11A performs bus initialization and arbitration functions as well as monitoring line conditions and connection status. The PDI1394P11A receives data to be transmitted over the bus from two or four parallel data paths to the Link Controller, D[0:3]. These data paths are latched and synchronized with the 49.152 MHz clock. The parallel bit paths are combined serially, encoded and transmitted at either 98.304 Mb/s or 196.608 Mb/s, depending whether the transaction is a 100 Mb/s or 200 Mb/s transfer, respectively. The transmitted data is encoded as data-strobe information, with the data information being transmitted on the TPB cable pairs and the strobe information transmitted on the TPA cable pairs. 7.1 Clocking The PDI1394P11A utilizes a stable internal reference clock of 196.608 MHz. The reference clock is generated using an external 24.576 MHz crystal and an internal Phase Locked Loop (PLL). The PLL clock is divided down to 49.152 MHz and 98.304 MHz clock signals. The 49.152 MHz clock is used for internal logic and provided as an output to clock a link layer controller. The 196.608 MHz and 98.304 MHz clocks are used for synchronization of the transmitted strobe and data information. During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair and the strobe information is received on the TPB cable pair. The combination of the data and strobe signals is decoded to recover the receive clock signal and the serial data stream. The serial data stream is converted to two or four parallel bit streams, resynchronized to the internal 49.152 MHz clock and sent to the 7.2 Port Interfaces The PDI1394P11A provides the transceiver functions needed to implement a three port node in a cable-based 1394 network. Each cable port incorporates two differential line transceivers. In addition to transmission and reception of packet data, the line transceivers 1999 Mar 10 4 Philips Semiconductors Preliminary specification 3-port physical layer interface PDI1394P11A associated link controller. The received data is also transmitted out the other active cable ports. presence of the remotely supplied twisted-pair bias voltage, indicating the cable connection status. The cable status, bus initialization and arbitration states are monitored through the cable interface using differential comparators. The outputs of these comparators are used by internal logic to determine cable and arbitration status. The TPA channel monitors the incoming cable common-mode voltage value during arbitration to determine the speed of the next packet transmission. The TPB channel monitors the incoming cable common-mode voltage for the The PDI1394P11A provides a nominal 1.85 V for driver load termination. This bias voltage, when seen through a cable by a remote receiver, is used to sense the presence of an active connection. The value of this bias voltage has been chosen to allow inter-operability between transceiver chips operating from either 5 V nominal supplies, or 3.3 V nominal supplies. This bias voltage source should be stabilized by using an external filter capacitor. When not powered, the PDI1394P11A prevents the bias voltage from erroneously powering up the part as is seen in some other Phys. 8.0 RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER CONDITION UNIT MIN TYP MAX 3.3 3.6 V 5.5 V 0.8 V VDD DC supply voltage Source/non-source power node 2.7 VIH High level input voltage CMOS inputs 2.0 VIL Low level input voltage CMOS inputs VID–100 Differential input voltage Cable inputs, 100Mbit operation 142 260 mV VID–200 Differential input voltage Cable inputs, 200Mbit operation 132 260 mV VID–ARB Differential input voltage Cable inputs, during arbitration 171 262 mV TPB cable inputs, 100Mbit or speed signaling OFF, source power node 1.165 2.515 TPB cable inputs, 100Mbit or speed signaling OFF, non–source power node 1.165 2.015 TPB cable inputs, 200Mbit or speed signaling, source power node 0.935 2.515 TPB cable inputs, 200Mbit or speed signaling, non–source power node 0.935 2.015 VIC–100 C VIC–200SP C S Common mode voltage Common mode voltage Receive input jitter Receive input skew IOL O /IOH O IO Output current, current IOL O /IOH O V TPA, TPB cable inputs, 100Mbit operation ±1.08 ns TPA, TPB cable inputs, 200Mbit operation ±0.5 ns Between TPA and TPB cable inputs, 100Mbit operation ±0.8 ns Between TPA and TPB cable inputs, 200Mbit operation ±0.55 ns SYSCLK –16 16 Control, Data, CNA, C/LKON –12 12 Output current TPBIAS outputs fXTAL Crystal frequency Parallel resonant fundamental mode crystal Tamb Operating ambient temperature range in free air 1999 Mar 10 V –3 24.5735 0 5 24.576 mA 1.3 mA 24.5785 MHz +70 °C Philips Semiconductors Preliminary specification 3-port physical layer interface PDI1394P11A 9.0 ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). LIMITS SYMBOL PARAMETER CONDITION MIN UNIT MAX VDD DC supply voltage –0.3 4.6 V VI DC input voltage3 Inputs CPS, TPAn, TPBn, FILTER, XI –0.5 VDD+0.5 V VI,5t DC input voltage 5V tolerant digital inputs RESET–, LPS, LREQ, PD, CTL[0:1], D[0:3], TESTM[2:1], C/LKON, PC[0:2], ISO– –0.5 5.5 V VO DC output voltage3 –0.5 VDD+0.5 V IIK DC input diode current – –50 mA IOK DC output diode current – ±50 mA Tstg Storage temperature range –65 +150 °C VI < 0 VO < 0 or VO > VDD NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output clamp current ratings are observed. 10.0 CABLE DRIVER SYMBOL VOD IO(diff) ISP VOFF PARAMETER TEST CONDITION LIMITS MIN TYP MAX UNIT Differential output voltage 56 load 172 265 mV Difference current, TPA+, TPA–, TPB+, TPB– Driver enabled, speed signaling OFF –1.051 1.051 mA Common mode speed signaling current, TPB+, TPB– 200Mbit speed signaling enabled +2.532 +4.842 mA OFF state common mode voltage Drivers disabled 20 mV NOTES: 1. Limits defined as algebraic sum of TPA+ and TPA– driver currents. Limits also apply to TPB+ and TPB– algebraic sum of driver currents. 2. Limits defined as one half of the algebraic sum of currents flowing into TPB+ and TPB–. 11.0 CABLE RECEIVER SYMBOL IIC PARAMETER Common mode input current TEST CONDITION Driver disabled ZID Differential input impedance Driver disabled ZIC C Common mode input impedance Driver disabled VTH Receiver input threshold voltage VTH Cable bias detect threshold, TPBn cable inputs 1999 Mar 10 Driver disabled 6 LIMITS MIN –20 TYP MAX 20 15 UNIT µA kΩ 6 20 pF kΩ 24 pF –60 60 mV 0.6 1.0 V Philips Semiconductors Preliminary specification 3-port physical layer interface PDI1394P11A 12.0 OTHER DEVICE I/O SYMBOL PARAMETER TEST CONDITION VDD = 3.3 V IDD Supply Su ly current LIMITS MIN TYP One port transmitting One port receiving One port not connected MAX 60 mA VDD = 3.6 V VDD = 3.6 V VP Power-down mode 1.5 UNIT 2 175 mA 5 mA 7.5 V Cable Power Threshold Voltage RL = 400 kΩ to CPS pin 4.7 VOH High-level output voltage IOH = Max., VDD = Min. VDD – 0.55 VOL Low-level output voltage IOL = Min., VDD = Max. 0.5 V Input current, LREQ, LPS, PD, TESTM[1:2] VI = 5.5 V or 0 V, ISO– = 0 ±1.0 µA IOZ OFF-state output current, CTLn, Dn, C/LKON I/Os, PC[0:2] inputs VO = 5.5 V or 0 V, ISO– = 0 ±5.0 µA IPU Pullup current, current RESET RESET– input II IPD Pulldown current, current RESET– RESET input Power-up reset time, RESET– input VTH + VTH– VTH–SP V VI = 1.5 V –20 –40 –80 µA VI = 0 V –22 –45 –90 µA 100 260 450 µA VI = VDD PD = high C = 0.1 µf 2 ms Positive arbitration comparator threshold voltage 89 168 mV Negative arbitration comparator threshold voltage –168 –89 mV Speed signal input threshold voltage 49 131 mV VIT+ Positive going input threshold voltage, LREQ, CTLn, Dn inputs VDD/2 + 0.12 VDD/2 + 0.66 V VIT– Negative going input threshold voltage, LREQ, CTLn, Dn inputs VDD/2 – 0.66 VDD/2 – 0.12 V VO TPBIASn output voltage 2.015 V Ib Absolute value of bus holding current LREQ, PD, CTLn, Dn inputs, LPS 1.665 ISO– = high, VI = 0.5 VDD 1.85 µA 190 13.0 THERMAL CHARACTERISTICS LIMITS SYMBOL PARAMETER RΘjA Junction-to-free-air thermal resistance RΘjC Junction-to-case thermal resistance 1999 Mar 10 TEST CONDITION Board mounted, no air flow 7 MIN TYP MAX UNIT 92.5 °C/W 10.4 °C/W Philips Semiconductors Preliminary specification 3-port physical layer interface PDI1394P11A 14.0 AC SWITCHING CHARACTERISTICS LIMITS SYMBOL PARAMETER MEASURED TEST CONDITION MIN TYP MAX UNIT Transmit jitter TPA, TPB ±0.25 ns Transmit skew Between TPA and TPB ±0.15 ns tr Transmit rise time 10% to 90% RL= 56Ω, CL= 10 pF 2.2 ns tf Transmit fall time 90% to 10% RL= 56Ω, CL= 10 pF 2.2 ns tsu Dn, CTLn, LREQ input setup time to SYSCLK 50% to 50% See Figure 1 5 ns tH Dn, CTLn, LREQ input hold time from SYSCLK 50% to 50% See Figure 1 2 ns tD Delay time, SYSCLK to Dn, CTLn 50% to 50% See Figure 2 2 13 ns 15.0 SWITCHING WAVEFORMS SYSCLK 50% tSU Dn, CTLn, LREQ 50% SYSCLK tH tD 50% Dn, CTLn SV00238 50% SV00239 Figure 1. Dn, CTLn, LREQ input setup and hold times 1999 Mar 10 50% Figure 2. Dn, CTLn, output delay relative to SYSCLK 8 Philips Semiconductors Preliminary specification 3-port physical layer interface PDI1394P11A 16.0 INTERNAL REGISTER CONFIGURATION The accessible internal registers of this device are listed in the following tables: 0 1 RHB IBR ADDRESS 2 0000 3 4 5 Physical ID 0001 6 7 R CPS GC 0010 SPD Reserved 0011 AStat1 BSTAT1 Ch1 Con1 Reserved 0100 AStat2 BSTAT2 Ch2 Con2 Reserved 0101 AStat3 BSTAT3 Ch3 Con3 Reserved 0110 Loopint 0111 CPSint CPS NP IR Reserved Reserved PC2 1000 PC1 C PC0 C Reserved 1001 Reserved ISBR The keys are listed as follows: SIZE TYPE Physical ID 6 Rd The address of the local node determined during the Self-ID. R 1 Rd Indicates that the local node is the root. CPS 1 Rd Cable power Status (CPS input). RHB 1 Rd/Wr Root hold-OFF bit. Instructs the local node to try to become the root during the next bus reset. IBR 1 Rd/Wr Initiate Bus Reset. Instructs the PDI1394P11A to initiate Bus Reset at the next opportunity. GC 6 Rd/Wr Gap count. Used to optimize the gap times based on the size of the network. See 1394 standard for details. SPD 2 Rd Indicates the top signaling speed of the local ports. For the PDI1394P11A this field is 01b indicating S200 speed capability. NP 4 Rd The number of ports on this device, set to 0011. AStat(n) 2 Rd The line state of TPA of port n: 11 = Z 01 = 1 10 = 0 00 = invalid data state. Power up reset initializes to this line state. Also this line state is output during transmit and receive operations. The line state outputs are generally valid during arbitration and idle conditions on the bus. BStat(n) 2 Rd The line state of TPB of port n. The encoding is the same as AStat(n). Ch(n) 1 Rd If = 1, then port n is a child, otherwise it is a parent. Con(n) 2 Rd If = 1, then port n is connected, otherwise it is disconnected. Loopint 1 Rd/Wr Indicates that the PDI1394P11A times out in tree ID, waiting for child signal from two or more ports. The Loopint can be cleared by writing a ‘‘0’’ to this bit, but if the loop configuration has not been corrected, it will promptly return to a ‘‘1’’. CPSint 1 Rd/Wr Indicates that the cable power has dropped too low for guaranteed reliable operation. It can be cleared by writing a ‘‘0’’ to the bit, but it will immediately return if CPS is still LOW. CPS 1 Rd/Wr Cable Power Status is also included in this register to expedite handling the CPSint. IR 1 Rd/Wr Indicates that the last bus reset was initiated in the PDI1394P11A. This bit is also included in the self ID packet. C 1 Rd If set, this node is a contender for the role of bus or Isochronous Resource Manager. PC2 1 Rd The least significant power class bit PC1 1 Rd The middle power class bit PC0 1 Rd The most significant power class bit ISBR 1 Rd/Wr Initiate Short Bus Reset. Instructs the PDI1394P11A to initiate an arbitrated short bus reset. See Section 17.1. FIELD 1999 Mar 10 DESCRIPTION 9 Philips Semiconductors Preliminary specification 3-port physical layer interface PDI1394P11A 17.0 APPLICATION INFORMATION 33 34 TPB3+ TPB3– 35 36 38 37 39 TPB2+ TPB2– TPA3+ TPA3– 40 TESTM2 21 DVDD 20 DVDD 19 DGND DGND 18 D0 D1 D2 D3 13 14 16 15 CTL1 12 11 DGND TPA2– DGND 64 41 22 DGND CTL0 63 42 TESTM1 10 62 AGND ISO– TPA2+ R1 61 43 23 SYSCLK 60 44 24 CPS 9 PLLVDD R0 45 25 AVDD DGND 58 46 AVDD PDI1394P11A 8 XO TPB1– AGND XI 57 47 26 7 ISO– 27 AGND DVDD PD 12pF C/LKON 6 56 TPA1– TPB1+ AVDD DVDD FILTER 55 TPA1+ 54 59 28 5 6.3K PC2 DVDD VDD PLLGND 4 53 TPBIAS1 52 LREQ 12pF 30 PLLGND PC0 PC1 3 AVDD TPBIAS2 51 LPS VDD 0.1µF 32 RESET– VDD AGND CNA 2 AGND AGND TP CABLES 1 50 49 TPBIAS3 48 TPBIAS TP CABLES CNA OUT 31 POWER-CLASS PROGRAMMING 29 10K CONTENDER PROGRAMMING VDD 400K CABLE POWER VDD 17 0.1µF POWER DOWN LINK LAYER CONTROLLER INTERFACE VDD VDD LINK LAYER CONTROLLER INTERFACE SV01074 Figure 3. External Component Connections CPS PDI1394P11 TPBIAS 56Ω VP 400K 1µF CABLE POWER PAIR VG 56Ω TPAn+ CABLE PAIR A TPAn– CABLE PORT TPBn+ CABLE PAIR B TPBn– 56Ω 5KΩ 56Ω 250pF SV00236 Figure 4. Twisted pair cable interface connections 1999 Mar 10 10 Philips Semiconductors Preliminary specification 3-port physical layer interface PDI1394P11A The external resistor (R) needed to set the CPS trip voltage (Vcable) to a desired voltage can be calculated using the following equation: 17.1 Arbitrated (short) Bus Reset A 1394-1995 software initiated bus reset assumes that the state of the bus is unknown when reset occurs and requires that the reset be long enough to permit the longest transaction to finish and still complete reset (167µs min. to 250µs max.). The total duration of bus initialization is longer than the nominal isochronous cycle time (125µs) and may disrupt two isochronous periods. This compels device designers to add additional buffer depth to preserve the smooth flow of isochronous data from the perspective of their application. If a node that initiates a reset arbitrates for control of the bus prior to asserting reset, arbitration time can be shortened significantly (1.3µs min. to 80µs max.). This 1394a concept is known as Arbitrated (short) Bus Reset, and is incorporated in the PDI1394P11A. R (V cable 1.85V) 10mA The external and internal circuitry associated with the CPS pin is illustrated in Figure 5. Vcable R COMPARATOR CPS The TESTM2 (pin 21) pins is used to enable Arbitrated (short) Bus Reset mode. In 1394-1995 mode, this pin is tied high. In this mode, an arbitrated bus reset cannot be initiated from this node and will be treated as a “long” bus reset if initiated by another node. In accordance with the 1394-1995 spec, all bus resets on the entire bus will be “long”. Icomp 10µA Vcomp 1.85V Phy To enable Arbitrated (short) Bus Reset mode, set TESTM2 low. With the part in this mode, writing a 1 to the ISBR (Initiate Short Bus Reset) bit (bit 7) of Phy register 9 initiates an arbitrated bus reset. This mode also allows the Phy to recognize arbitrated bus resets initiated by other nodes. Non-arbitrated bus resets can still be initiated from this node and are recognized and processed correctly when initiated by another node. SV00921 Figure 5. Some typical threshold voltage values and their associated resistor values are shown in Table 1. 17.2 Setting the CPS Trip Point The Cable Power Status (CPS) pin (pin 23) is used to monitor the cable power. When cable power voltage has dropped too low for reliable operation, internal circuitry trips, which clears the CPS bits in the Phy registers (bit 7 of register 0, and bit 2 of register 6). This action causes a cable power status interrupt which sets the CPSint bit in the Phy registers (bit 1 of register 6). This bit can be cleared by a hardware reset or by writing a 0 to the CPSint bit. However, if the CPS input is still low, another cable-power status interrupt immediately occurs. The cable voltage at which these events occur is adjustable on the PDI1394P11A. 1999 Mar 10 Table 1. Typical threshold voltage values Vcable ((V)) 11 R ((kΩ)) Vcable DETECTOR TOLERANCE % WITH: R of 5% R of 2% 5 315 6.8 4.4 6 415 7.3 4.8 7 515 7.8 5.2 8 615 8.3 5.6 9 715 8.8 6.0 Philips Semiconductors Preliminary specification 3-port physical layer interface PDI1394P11A The PHY’s outputs can be 3-Stated and single capacitor isolation can be used with the Link; both situations will allow the Link inputs to float. With bushold circuitry enabled, these pins are provided with dc paths to ground, and power by means of the bushold transistors; this arrangement keeps the inputs in known logical states. 17.3 Bushold and Link/PHY single capacitor galvanic isolation 17.3.1 Bushold The PDI1394P11A uses an internal bushold circuit on each of the indicated pins to keep these CMOS inputs from “floating” while being driven by a 3-Stated device or input coupling capacitor. Unterminated high impedance inputs react to ambient electrical noise which cause internal oscillation and excess power supply current draw. The following pins have bushold circuitry enabled when the ISO– pin is in the logic “1” state: Pin No. 2 3 7 11 12 13 14 15 16 Name LPS LREQ PD CTL0 CTL1 D0 D1 D2 D3 INTERNAL CIRCUITS INPUT PIN Function Link power status line Link request line Power down pin Phy/Link Interface bi-directional control line 0 Phy/Link Interface bi-directional control line 1 Phy/Link Interface bi-directional data line 0 Phy/Link Interface bi-directional data line 1 Phy/Link Interface bi-directional data line 2 Phy/Link Interface bi-directional data line 3 SV00911 Figure 6. Bushold circuit 17.3.2 Single capacitor isolation The circuit example (Figure 7) shows the connections required to implement basic single capacitor Link/PHY isolation. Philips bushold circuitry is designed to provide a high resistance pull-up or pull-down on the input pin. This high resistance is easily overcome by the driving device when its state is switched. Figure 6 shows a typical bushold circuit applied to a CMOS input stage. Two weak MOS transistors are connected to the input. An inverter is also connected to the input pin and supplies gate drive to both transistors. When the input is LOW, the inverter output drives the lower MOS transistor and turns it on. This re-enforces the LOW on the input pin. If the logic device which normally drives the input pin were to be 3-Stated, the input pin would remain “pulled-down” by the weak MOS transistor. If the driving logic device drives the input pin HIGH, the inverter will turn the upper MOS transistor on, re-enforcing the HIGH on the input pin. If the driving logic device is then 3-Stated, the upper MOS transistor will weakly hold the input pin HIGH. The RESET, C/LKON, PD, and LPS pins need special consideration to implement an isolation scheme. Details can be found in the Philips Isolation Application Note AN2452. NOTE: The isolation enablement pins on both devices are in their “1” states, activating the bushold circuits on each part. The bushold circuits provide local dc ground references to each side of the isolating/coupling capacitors. Also note that ground isolation/signal-coupling must be provided in the form of a parallel combination of resistance and capacitance as indicated in IEEE 1394–1995. APPLICATION +3.3V ISO_N PHY D0 LINK PHY D1 PDI1394Lxx PHY D2 PHY D3 PHYCTL0 PHYCTL1 LREQ SCLK ISOLATED +3.3V Cc Cc Cc Cc Cc 62 13 Cc 14 15 16 Cc 11 12 3 Cc 9 ISO– D0 PHY D1 PDI1394P11A D2 D3 PHYCTL0 PHYCTL1 LREQ SYSCLK 1MEG Ω APPLICATION GROUND Cr Cc = 0.001µF; Cr = 0.1µF Figure 7. Single capacitor Link/PHY isolation 1999 Mar 10 12 ISOLATED PHY GROUND SV01048 Philips Semiconductors Preliminary specification 3-port physical layer interface PDI1394P11A 18.0 EXTERNAL COMPONENTS AND CONNECTIONS 18.1 Logic Reset input (RESET–, pin 1) 18.9 Cable Power Status input (CPS, pin 23) Forcing this pin low causes a Bus Reset condition on the active cable ports, and resets the internal logic to the Reset Start state. SYSCLK remains active. For power up (and after power down is asserted) a 2 ms delay is required to assure proper PLL operation. An internal pull-up resistor is connected to VDD, so only an external delay capacitor is required. This input is a standard logic buffer and may also be driven by an open drain logic output buffer. The RESET pin also has a n-channel pull-down transistor activated by the Power Down pin. For a reset during normal operation, a 10 ms low pulse on this pin will accomplish a full PHY reset. This pulse as well as the 2 ms power up pulse could be microprocessor controlled in which case the external delay capacitor would not be needed. For more details on using single capacitor isolation with this pin please refer to the Philips Isolation Application Note AN2452. This is normally connected to the cable power through an external resistor. The circuit drives an internal comparator which is used to detect the presence of cable power. This information is maintained in an internal register and is available to the link layer controller through a register read. See section 17.2 for information on setting the CPS trip point. 18.10 Bus or Isochronous Resource Manager Capable input or Link-On output (C/LKON, pin 27) On hardware reset, this pin is used to set the default value of the contender status indicated during self-ID. The bit value programming is done by tying the pin through a 10 kW resistor to VDD (high, bus manager capable) or to GND (low, not bus manager capable). Using either a pull-up or pull-down resistor allows the link-on output to override the input value when necessary. After hardware reset, this pin is used as an output to signal the reception of a Link-On packet. A 6.114 MHz signal is supplied until the LPS input is active at which point the C/LKON output goes low. 18.2 Link Power Status input (LPS, pin 2) In a non-isolated implementation a 10kΩ resistor is connected to the VDD supplying the link layer controller to monitor the link’s power status. In an isolated implementation a square wave with a minimum frequency of 500 kHz can be applied to the LPS pin to indicate the pin is powered. If the link is not powered on, the Control I/O’s (pins 11,12), Data I/O’s (pins 13 – 16) and SYSCLK output (pin 9) are disabled, and the PDI1394P11A will perform only the basic repeater functions required for network initialization and operation. This pin is equipped with Bus Hold circuitry. 18.11 Power Class bits 0 through 2 inputs (PC[0:2], pins [30,29,28]) Used as inputs to set the bit values of the three Power Class bits in the self-ID packet (bits 21, 22 and 23). These bits can be programmed by tying the pins high to VDD or low to GND. 18.12 Cable Not Active output (CNA, pin 31) 18.3 Link Request input (LREQ, pin 3) LREQ is a signal from the link layer controller used to request the PDI1394P11A to perform some service. This pin is equipped with Bus Hold circuitry and supports an optional isolation barrier. This pin outputs the cable connection status. If all ports are disconnected this pin outputs a high. If any port has a cable connected then this pin outputs a low. 18.4 Power Down input (PD, pin 7) 18.13 Twisted Pair I/O’s (TPA[1:3]+, pins [45, 40, 36], TPA[1:3]–, pins [44,39,35], TPB[1:3]+, pins [43,38,34], TPB[1:3]–, pins [42, 37, 33]) This input powers down all device functions with the exception of the CNA circuit to conserve power in portable or battery powered applications. It must be held high for at least 3.5ms to assure a successful reset after power down. This pin is equipped with Bus Hold circuitry and supports an optional isolation barrier. These pins send and receive differential data over the twisted pair cables. Two series connected external 56 Ω cable termination resistors are required at each twisted pair. Each unused TPB pin must be tied through a 5kΩ resistor to ground. The TPA pins can be left floating. 18.5 System Clock output (SYSCLK, pin 9) Provides a 49.152 MHz clock signal, synchronized with the data transfers, to the link layer controller. This pin supports an optional isolation barrier. 18.14 Twisted Pair Bias outputs (TPBIAS[1:3], pins [46, 47, 48]) 18.6 Control I/Os (CTL[0:1], pins[11,12]) These outputs provide the 1.86 V nominal bias voltage needed for proper operation of the twisted pair cable drivers, and for signaling to the remote nodes that there is a valid cable connection. Three TPBIAS outputs are provided for separate connection to each of the three TPA twisted pairs to provide electrical isolation. A 1µF capacitor to ground must be connected to each TPBIAS pin whether it is used or not. These are bi-directional signals used in the communication between the PDI1394P11A and the link layer controller that control passage of information between the two devices. These pins are equipped with Bus Hold circuitry and support an optional isolation barrier. 18.7 Data I/Os (D[0:3], pins [13,14,15,16]) These are bi-directional information signals used in the communication between the PDI1394P11A and the link layer controller. These pins are equipped with Bus Hold circuitry and support an optional isolation barrier. 18.15 PLL Filter (FILTER, pin 54) This pin is connected to an external filter capacitor used in a lag-lead filter for a PLL frequency multiplier running off of the crystal oscillator. 18.8 Test Mode control and ISBR mode inputs (TESTM[1:2], pins[22,21]) 18.16 Oscillator crystal (Xl, pin 56 & XO, pin 57) These pins connect to a 24.576 MHz parallel resonant fundamental mode crystal. The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used, the suggested values of 12 pF are appropriate for one specified for 15 pF loads. These two logic signals are used in manufacturing to enable production line testing of the PDI1394P11A. For normal use these should be tied to VDD. To enable ISBR (Arbitrated (short) bus reset) mode, set TESTM1 high and TESTM2 low. See section 17.1 for more information on ISBR mode. 1999 Mar 10 13 Philips Semiconductors Preliminary specification 3-port physical layer interface PDI1394P11A 18.17 Current setting resistor (R[0:1], pins [59,60]) An internal reference voltage is applied across the resistor connected between these two pins to set the internal operating and the cable driver output currents. A low TCR (<150ppm/°C temperature coefficient) with a value of 6.34 kΩ ±1% should be used to meet the 1394 standard output voltage limits. CTL [0:1] NAME DESCRIPTION OF ACTIVITY 00 Idle The link releases the bus (transmission has been completed). 01 Hold The link is holding the bus while data is being prepared for transmission or sending another packet without arbitrating. 10 Transmit An outgoing packet is being sent from the link to the phy. 11 NA None 18.18 Isolation Barrier disable (ISO–, pin 62) When ISO– is high, busholder circuits are enabled on the LREQ, PD, and LPS input pins and on the CTL, and Data bidirectional pins. This mode also allows isolation using a single 1nF capacitor per signal line. Details for this kind of isolation can be found in the Philips Isolation Application Note AN2452. When ISO– is low, busholder circuits are disabled and isolation can be realized by using the scheme explained in Annex J of the 1394–1995 spec. 19.2 Request When the link layer controller wishes to request the bus, or access a register that is located in the PDI1394P11A, a serial stream of information is sent across the LREQ line. The length of the stream will vary depending on whether the transfer is a bus request, a read command, or a write command. Regardless of the type of transfer, a start bit of 1 is required at the beginning of the stream, and a stop bit of 0 is required at the end of the stream. Bit 0 is the most significant, and is transmitted first. The LREQ line will be required to idle low (logic level 0). 18.19 Supply filters (AVDD, pins [24, 25, 51, 55], DVDD, pins [5,6,19,20], and PLLVDD, pin 58) A combination of decoupling capacitors is suggested for each supply group, such as paralleled 10 µF and 0.1 µF. The high frequency 0.1 µF capacitors should be mounted as close as possible to the PDI1394P11A device supply leads. These supply lines are separated on the IC to provide noise isolation. They should be tied together at a low impedance point on the circuit board. Individual filter networks are desirable. 19.2.1 Link Layer Controller Bus Request For a Bus Request, the length of the LREQ data stream is 7 bits as follows: Details of a phy-link Interface supporting an optional isolation barrier are provided in Annex J of the 1394 standard. BIT(S) NAME DESCRIPTION 0 Start Bit Indicates the beginning of the transfer (always 1) 1–3 Request Type Indicates the type of bus request (see the table below for the encoding of this field) 4–5 Request Speed This should be 00 for PDI1394P11A’s 100 Mbit/s speed and 01 for 200 Mbit/s speed. 6 Stop Bit Indicates the end of the transfer (always 0) 19.0 PRINCIPLES OF OPERATION The PDI1394P11A is designed to operate with a link layer controller. These devices use an interface such as described in Annex J of the 1394 standard. The following describes the operation of the phy-link interface. 19.1 Data Transfer and Clock rates The PDI1394P11A supports 100/200 Mbit/s data transfer, and has four bi-directional data lines D[0:3] crossing the interface. In 100 Mbit/s operation only D[0:1] pins are used, in 200 Mbit/s operations all D[0:3] pins are used for data transfer. The unused D[n] pins are driven low. In addition there are two bi-directional control lines CTL[0:1], the 50 MHz SYSCLK line from the phy to the link, and the link request line LREQ from the link to the phy. The PDI1394P11A has control of all the bi-directional pins. The link is allowed to drive these pins only after it has been given permission by the phy. The dedicated LREQ request pin is used by the link for any activity which it wishes to initiate. 19.2.2 Link Layer Controller Requests Read Register Access For a Read Register Request, the length of the LREQ data stream is 9 bits as follows: When the phy has control of the bus the CTL[0:1] lines are encoded as follows: BIT(S) NAME DESCRIPTION 0 Start Bit Indicates the beginning of the transfer (always 1) 1–3 Request Type Always a 100 indicating that this is a read register request 4–7 Address The address of the phy register to be read 8 Stop Bit Indicates the end of the transfer (always 0) 19.2.3 Link Layer Controller Requests Write Register Access For a Write Register Request, the length of the LREQ data stream is 17 bits. The details of bits are as shown below: CTL [0:1] NAME DESCRIPTION OF ACTIVITY 00 Idle No activity is occurring (this is the default mode). 01 Status Status information is being sent from the phy to the link. BIT(S) NAME DESCRIPTION 0 Start Bit An incoming packet is being sent from the phy to the link. Indicates the beginning of the transfer (always 1) 1–3 Request Type The link has been given control of the bus to send an outgoing packet. Always a 101 indicating that this is a write register request 4–7 Address The address of the phy register to be written to 8–15 Data The data that is to be written to the specified register address 16 Stop Bit Indicates the end of the transfer (always 0) 10 11 Receive Grant When the link has control of the bus (phy permission) the CTL[0:1] lines are encoded as follows: 1999 Mar 10 14 Philips Semiconductors Preliminary specification 3-port physical layer interface PDI1394P11A 19.2.4 Other Requests and LREQ The three bit Request Type field has the following possible values: BIT(S) NAME DESCRIPTION 000 ImmReq Immediate request: Upon detection of an idle, take control of the bus immediately (no arbitration) 001 IsoReq Isochronous request: Arbitrate for the bus, no gaps 010 PriReq Priority request: Arbitrate after a subaction gap, ignore fair protocol 011 FairReq Fair request: Arbitrate after a subaction gap, follow fair protocol 100 RdReg Return the specified register contents through a status transfer 101 WrReg Write to the specified register 110, 111 Reserved Reserved 19.3 Operation of LREQ LR0 LR1 LR2 LR3 LR(n–2) LR(n–1) SV00232 Figure 8. LREQ Input Sequence (each cell represents one SYSCLK sample time) removed. The only side effect would be the loss of the intended acknowledgment packet (this will be handled by the higher-layer protocol). For fair or priority access, the link requests control of the bus at least one clock after the phy-link interface becomes idle. If the link senses that the CTL pins are in a receive state (CTL[0:1] = 10), then it will know that its request has been lost. This is true anytime during or after the link sends the bus request transfer. Additionally, the phy will ignore any fair or priority requests if it asserts the receive state while the link is requesting the bus. The link will then reissue the request one clock after the next interface idle. 19.4 Read/Write Requests When the link requests to read the specified register contents, the phy will send the contents of the register to the link through a status transfer. If an incoming packet is received while the phy is transferring status information to the link, the phy will continue to attempt to transfer the contents of the register until it is successful. The cycle master uses a normal priority request to send a cycle start message. After receiving a cycle start, the link can issue an isochronous bus request. When arbitration is won, the link proceeds with the isochronous transfer of data. The isochronous request will be cleared by the phy once the link sends another type of request or when the isochronous transfer has been completed. For write requests, the phy will load the data field into the appropriately addresses register as soon as the transfer has been completed. The link will be allowed to request read or write operations at any time. The ImmReq request is issued when the link needs to send an acknowledgment after reception of a packet address to it. This request must be issued during packet reception. This is done to minimize the delays that a phy would have to wait between the end of a packet and the transmittal of an acknowledgment. As soon as the packet ends, the phy immediately grants access of the bus to the link. the link will send an acknowledgment to the sender unless the header CRC of the packet turns out to be bad. In this case, the link will release the bus immediately; it will not be allowed to send another type of packet on this grant. To guarantee this, the link will be forced to wait 160 ns after the end of the packet is received. The phy then gains control of the bus and the ack with the CRC error is sent. Then the bus is released and allowed to proceed with another request. 19.5 Status A status transfer is initiated by the phy when it has status information to transfer to the link. The phy will wait until the interface is idle before starting the transfer. The transfer is initiated by asserting the following on the control pins: CTL[0:1] = 01 along with the first two bits of status information on the D[0:1] pins. The phy maintains CTL[0:1] = 01 for the duration of status transfer. The phy may prematurely end a status transfer by asserting something other than CTL[0:1] = 01 on the control pins. This could be caused by an incoming packet from another node. The phy will continue to attempt to complete the transfer until the information has been successfully transmitted. There must be at least one idle cycle in between consecutive status transfers. The phy normally sends just the first four bits of status to the link. These bits are status flags which are needed by the link state machines. The phy sends an entire status packet to the link after a request transfer which contains a read request, or when the phy has pertinent information to send to the link or transaction layers. The only defined condition when the phy automatically sends a register to the link is after self-ID, when it sends the physical-ID register which contains the new node address. Although highly improbable, it is conceivable that the two separate nodes will believe that an incoming packet is intended for them. The nodes then issue a ImmReq request before checking the CRC of the packet. Since both phys will seize control of the bus at the same time, a temporary, localized collision of the bus will occur somewhere between the competing nodes. This collision would be interpreted by the other nodes on the network as being a ‘ZZ’ line state, not a bus reset. As soon as the two nodes check the CRC, the mistaken node will drop its request and the false line state will be 1999 Mar 10 The definition of the bits in the status transfer are shown below. 15 Philips Semiconductors Preliminary specification 3-port physical layer interface PDI1394P11A 20.0 STATUS REQUEST, LENGTH OF STREAM: 16 BITS BIT(S) NAME DESCRIPTION 0 Arbitration reset gap Indicates that the phy has detected that the bus has been idle for an arbitration reset gap time (this time is defined in the P1394 standard). This bit is used by the link in its busy/retry state machine. 1 Subaction gap Indicates that the phy has detected that the bus has been idle for a subaction gap time (this time is defined in the P1394 standard). This bit is used by the link to detect the completion of an isochronous cycle. 2 Bus Reset Indicates that the phy has entered the bus reset state. 3 State Time out or CPS Indicates that the phy stayed in a particular state for too long a period, which is usually the effect of a loop in the cable topology, or that the cable power has dropped below the threshold for reliable operation. 4–7 Address These bits hold the address of the phy register whose contents will be transferred to the link. 8–15 Data The data that is to be sent to the link. 21.0 STATUS TRANSFER TIMING PHY CTL [0:1] 00 01 01 01 00 00 PHY D [0:1] 00 S[0,1] S[2,3] S[14,15] 00 00 SV00233 Figure 9. Status Transfer Timing 1999 Mar 10 16 Philips Semiconductors Preliminary specification 3-port physical layer interface PDI1394P11A instead of ‘Idle’ when the first packet of data has been completely transmitted. ‘Hold’, in this case, informs the phy that the link needs to send another packet without releasing control of the bus. The phy will then wait a set amount of time before asserting ‘transmit’. The link can then proceed with the transmittal of the second packet. After all data has been transmitted and the link has asserted ‘Idle’ on the CTL pins, the phy will assert its own ‘Idle’ state on the CTL lines. When sending multiple packets in this fashion, it is required that all data be transmitted at the same speed. This is required because the transmission speed is set during arbitration and since the arbitration step will be skipped, there will be no way of informing the network of a change in speed. 22.0 TRANSMIT When the link wants to transmit information, it will first request access to the bus through the LREQ pin. Once the phy receives this request, it will arbitrate to gain control of the bus. When the phy wins ownership of the serial bus, it will grant the bus to the link by asserting the ‘transmit’ state on the CTL pins for at least one SYSCLK cycle, followed by idle for one clock cycle. The link will take control of the bus by asserting either ‘hold’ or ‘transmit’ on the CTL lines. ‘hold’ is used by the link to keep control of the bus if it needs some time to prepare the data for transmission. The phy will keep control of the bus for the link by asserting a ‘data-prefix’ state on the bus. It is not necessary for the link to use ‘hold’ if it is ready to transmit as soon as bus ownership is granted. The PDI1394P11A includes a digital camera/single port Phy interoperability enhancement. When a node is root (and consequently cycle master) and is sending Isochronous data, it does not need to arbitrate for the bus (by default it would win any such arbitration). This fact was overlooked by some early 100 Mbps single port Phy manufacturers whose chips are too slow to handle the absence of the arbitration time. This causes their Phys to see a header CRC error and the packet to be discarded. The PDI1394P11A compensates for this by extending the Data_Prefix time before sending the packet. This makes the PDI1394P11A fully compatible with all existing 100 Mbps Phys on the market. When the link is prepared to send data, it will assert ‘transmit’ on the CTL lines as well as sending the first four bits of the packet on the D[0:3] lines (assuming 200 Mb/s). The ‘transmit’ state is held on the CTL pins until the last bits of data have been sent. The link will then assert ‘Idle’ on the CTL lines for one clock cycle after which it releases control of the interface. However, there will be times when the link will need to send another packet without releasing the bus. For example, the link may want to send consecutive isochronous packets or it may want to attach a response to an acknowledgment. To do this, the link will assert ‘hold’ 22.1 TRANSMIT TIMING WAVEFORMS PHY CTL [0:1] 00 11 00 ZZ ZZ ZZ ZZ ZZ ZZ ZZ ZZ 00 0000 0000 0000 ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ ZZZZ 0000 ZZ ZZ ZZ 01 01 10 10 10 10 00 00 ZZ ZZZZ ZZZZ ZZZZ 0000 0000 P0 P1 P2 Pn 0000 0000 ZZZZ ZZ ZZ ZZ ZZ 00 00 11 00 ZZ ZZ ZZ ZZ ZZZZ ZZZZ ZZZZ ZZZZ 0000 0000 0000 0000 ZZZZ ZZZZ ZZZZ ZZZZ LINK CTL [0:1] 10 10 01 00 ZZ ZZ ZZ ZZ 01 01 10 10 LINK CTL [0:1] Pn–1 Pn 0000 0000 ZZZZ ZZZZ ZZZZ ZZZZ 0000 0000 P0 P1 PHY D [0:3] LINK CTL [0:1] LINK D [0:3] PHY CTL [0:1] PHY D [0:3] NOTE: ZZ = High Impedance State P0 ⇒ Pn = Packet Data SV00235 NOTE: ZZ = High Impedance State P0 => Pn = Packet data Figure 10. Transmit Timing Waveforms 1999 Mar 10 17 Philips Semiconductors Preliminary specification 3-port physical layer interface PDI1394P11A 23.0 RECEIVE When data is received by the phy from the serial bus, it will transfer the data to the link for further processing. The phy will assert ‘Receive’ on the CTL lines and ‘1’ on each D pin. The phy indicates the start of the packet by placing the speed code on the data bus. The phy will then proceed with the transmittal of the packet to the link on the D lines while still keeping the ‘Receive’ status on the CTL pins. Once the packet has been completely transferred, the phy will assert ‘Idle’ on the CTL pins which will complete the receive operation. NOTE: The speed is a phy-link protocol and not included in the CRC. 23.1 RECEIVE TIMING WAVEFORMS PHY CTL [0:1] PHY D [0:3] 00 10 10 10 10 10 10 00 00 0000 1111 1111 SPD P0 P1 Pn 0000 0000 NOTE: SPD = Speed Code P0 ⇒ Pn = Packet Data SV00234 NOTE: SPD = Speed Code P0 Pn = packet data Figure 11. Receive Timing Waveforms The speed code for the receiver is as follows: D [0:3] DATA RATE (Mbit/s) 00XX 100 0100 200 NOTE: X transmitted as 0, ignored on receive. 24.0 POWER CLASS BITS IN SELF–ID PACKET The settings of the PC[0:2] pins appear in the pwr field of the self–ID packet. Bit 21 is transmitted first, followed by bit 22 and then bit 23. pwr[21:23] DESCRIPTION 000 Node does not need power and does not repeat power. 001 Node is self powered, and provides a minimum of 15 W to the bus. 010 Node is self powered, and provides a minimum of 30 W to the bus. 011 Node is self powered, and provides a minimum of 45 W to the bus. 100 Node may be powered from the bus, and is using up to 1 W. 101 Node may be powered from the bus, and is using up to 1 W. An additional 2 W is needed to enable the LLC and higher layers. 110 Node may be powered from the bus, and is using up to 1 W. An additional 5 W is needed to enable the LLC and higher layers. 111 Node may be powered from the bus, and is using up to 1 W. An additional 9 W is needed to enable the LLC and higher layers. 1999 Mar 10 18 Philips Semiconductors Preliminary specification 3-port physical layer interface PDI1394P11A LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm 1999 Mar 10 19 SOT314-2 Philips Semiconductors Preliminary specification 3-port physical layer interface PDI1394P11A Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 03-99 Document order number: 1999 Mar 10 20 9397 750 05499