VIA Technologies, Inc. Preliminary VT6304 VT6304 1394.A 4 PORT PHYSICAL LAYER CHIP DATA SHEET (Preliminary) DATE : June 1, 1999 VIA TECHNOLOGIES, INC. 1 VIA Technologies, Inc. Preliminary VT6304 PRELIMINARY RELEASE Please contact Via Technologies for the latest documentation. Copyright Notice: Copyright © 1998, Via Technologies Incorporated. Printed in Taiwan. ALL RIGHTS RESERVED. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of Via Technologies Incorporated. The VT6101/VT6102 may only be used to identify products of Via Technologies. All trademarks are the properties of their respective owners. Disclaimer Notice: No license is granted, implied or otherwise, under any patent or patent rights of Via Technologies. Via Technologies makes no warranties, implied or otherwise, in regard to this document and to the products described in this document. The information provided by this document is believed to be accurate and reliable to the publication date of this document. However, Via Technologies assumes no responsibility for any errors in this document. Furthermore, Via Technologies assumes no responsibility for the use or misuse of the information in this document and for any patent infringements that may arise from the use of this document. The information and product specifications within this document are subject to change at any time, without notice and without obligation to notify any person of such change. Offices: 5020 Brandin Court Fremont, CA 94538 USA 8th Floor, No. 533 Chung-Cheng Rd., Hsin-Tien Taipei, Taiwan ROC Tel: Fax: Tel: Fax: (510) 683-3300 (510) 683-3301 Onlines Services: BBS : 886-2-2186408 FTP : FTP.VIA.COM.TW HTTP: WWW.VIA.COM.TW 2 (886-2) 218-5452 (886-2) 218-5453 VIA Technologies, Inc. Preliminary VT6304 VT6304 IEEE 1394A FOUR PORT CABLE TRANSCEIVER/ARBITER FEATURES n n n n n n n n n n n n n n n n n n n n Supports Provisions of IEEE 1394-1995 Standard for High Performance Serial Bus and the P1394a Supplement 2.0. Full P1394a Supplement Support includes: n Arbitrated short reset, n Connection Debounce, n Multispeed Concatenation, n Ack Accelerated Arbitration, n Fly-By Concatenation, n Programmable Port Disable, Suspend, Resume, n PHY IDs Do Not Increment Past 63 Provides Four 1394a Fully Compliant Cable Ports at 100/200/400 Megabits per Second (Mbit/s) Single 3.3 V power supply Logic Performs Bus Initialization and Arbitration Functions Encode and Decode Functions Included for Data-Strobe Bit-Level Encoding Incoming Data Resynchronized to Local Clock. Data Interface to Link-Layer Controller Provided Through 2/4/8 Parallel Lines at 49.152 MHz 24.576 MHZ Crystal Oscillator and PLL Provide TX/RX Data at 100/200/400 Mbps and Link-Layer Controller Clock at 49.152 MHZ. Cable Power Presence Monitoring. Programable Node Power Class Information for System Power Management Embedded Bus Holder Isolation to Link Layer Controller Interface Optional On-chip Resistors to Reduce Component Counts for Electrical Isolation to Link Layer Controller Interface Fully Compliant P1394a 2.0 PHY Map Separate TPBIAS for Each Port Fully Interoperable with IEEE Std1394-1995 Devices Cable Ports Monitor Line Conditions for Active Connection to Remote Node Low Power Design for Battery-Powered Applications includes: User Controlled Power-Down via PD, Automatic Device Power-Down during All Ports Suspended and Link Interface Disabled, Link Interface Power-Down via Inactive LPS, Automatic Inactive Ports Powered-Down, and Automatic Inactive Logic Power-Down Self Power Up Reset and Pinless PLL to Reduce Component Counts on System Low Cost 100-Pin PQFP package 3 VIA Technologies, Inc. Preliminary VT6304 CPS Received Data Decoder/ Retimer LPS ISO\ SYS CLK Bias Voltage and Current Generator LREQ CTL0 Link Interfac e I/O TPBIAS1 TPBIAS2 TPBIAS3 TPBIAS4 TPA1+ TPA1- CTL1 D0 D1 D2 D3 D4 D5 D6 D7 Cable Port 1 Arbitration and Control State Machine Logic PC0 PC1 PC2 TPB1+ TPB1- Cable Port 2 C/LKON Cable Port 3 TESTM1 TESTM2 Cable Port 4 RESET\ Transmit Data Encoder n Figure 1: Functional Block of VT6304 4 Crystal Oscillator, PLL System, and Clock Generator TPA2+ TPA2TPB2+ TPB2TPA3+ TPA3TPB3+ TPB3TPA4+ TPA4TPB4+ TPB4- XI XO VIA Technologies, Inc. Preliminary VT6304 LREQ GNDD 2 NC NC NC NC NC VDDD 2 CTL 1 D6 D7 CTL 0 NC NC NC NC NC PD ISO_ VDDD 4 SCLK GNDD 4 D0 D1 D2 VDDD 3 D3 D4 D5 GNDD 3 Pin Diagram 80 79 78 77 76 75 74 73 72 7170 69 68 6766 65 64 63 62 6160 59 58 57 5655 54 53 52 51 GNDDC2 XCPS VDDARX0 GNDARX0 XTPB0M XTPB0P XTPA0M XTPA0P XTPBIAS0 VDDATX0 GNDATX0 GNDATX1 VDDATX1 VDDARX1 GNDARX1 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VT6304 01/07/99 updated 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1718 19 20 21 22 2324 25 26 27 28 29 30 NC NC NC NC NC GNDATX2 XTPB1M XTPB1P XTPA1M XTPA1P XTPBIAS1 VDDATX2 VDDARX2 XTPB2M XTPB2P XTPA2M XTPA2P XTPBIAS2 GNDATX3 XTPB3M XTPB3P XTPA3M XTPA3P XTPBIAS3 GNDARX2 NC NC NC NC NC GNDD5 LINKON LPS CMC VDDDC2 5 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 CNA RESET_ ONCT TSI GNDD1 VDDD1 PC0 PC1 PC2 TSO VDDDC1 GNDDC1 XO XI XREXT GNDAREXT GNDARX3 VDDARX3 VDDATX3 GNDATX4 VIA Technologies, Inc. Preliminary VT6304 PIN DESCRIPTIONS No. Name Link-PHY Interface 82 LINKON Type Description O Link on. Indicates the reception of a link-on packet or port event occurs by asserting a 6.114 MHZ signal. Link power status. LPS is connected to either the VDD supplying the LINK or to a pulsed output that is active when the LINK is powered for the purpose of monitoring the LINK power status. Link request. LREQ is an input from the LINK that requests the PHY to perform some service. Link interface isolation control input. This terminal controls the operation of output differentiation logic on the CTL[0-1] and D[0-7] signals. If an optional isolation barrier is implemented between the VT6304 and LLC the ISO_ pin should be tied low to enable the differentiation logic. If no isolation barrier is implemented, the ISO_ should be tied high to disable differentiation logics. Control I/O. the CTLn terminals are bidirectional communications control signals between the PHY and LINK. Data I/O. The D terminals are bidirectional and pass data between the PHY and LINK. 83 LPS I 57 LREQ I 74 ISO_ I 60, 58 CTL[0-1] I/O 70, 69, 68, 66, 65, 64, 62, 61 72 D[0-7] I/O SCLK O Analog Interface 93, 10, XTPA[0-3]P 17, 22 92, 9 , XTPA[0-3]M 16, 22 91, 8, 15, XTPB[0-3]P 21 90, 7, 14, XTPB[0-3]M 20 94, 11, XTPBIAS[018, 23 3] Misc. 87 XCPS System clock. SCLK provides a 49.152 MHZ clock signal, which is synchronized with the data transfers to the LINK. I/O Twisted-pair cable A differential positive signal pins. I/O Twisted-pair cable A differential negative signal pins. I/O Twisted-pair cable B differential positive signal pins. I/O Twisted-pair cable B differential negative signal pins. I/O Twisted-pair bias voltage supply. Provide 1.85V (typical) nominal bias for proper operation of the twisted-pair cable drivers and receivers, and for signaling to the remote nodes that the cable connections is active. Hi-impedance during chip reset or power down. Can be disabled via remote packets or software defined in P1394a Draft 2.0. Each of these pin must be decoupled with a 1-uF capacitor to ground. I CPS : Cable power status. CPS is normally connected to the cable power through a 11 Kohm/1 KOhm volatge divider. This circuit drivers an internal comparator that detects the presencce of cable power. 6 VIA Technologies, Inc. 50 CNA O 84 CMC I 44, 43, 42 PC[0-2] I 47 TSI I 41 TSO I 48 ONCT I 75 PD I 49 RESET_ I/NC 38, 37 XI, XO Crystal 36, 35 XREXT, GNDARE XT Power Supply & Ground 88, 99, 13, VDDARX 33 89, 100, 25, 24 GNDARX I/O supply supply Preliminary VT6304 CNA is asserted high when none of the PHY ports are connected to another active port. This circuit remains active during the powerdown mode. Programable Contender/Bus Manager Capable. It specifies in the Self-ID packet that the node is capable of being a bus manager. Power Class. These pins are used to set the three POWER_CLASS bits in the Self-ID packet. They are used to describe the power consumption and source characteristics of the node. PC0, 1, 2 are reflected in the Self-ID packet bits 21, 22, 23, respectively. Single Self ID packet. If port 4 is unused, i.e, the resistors and capacitors for port 4 are not implemented, there is no need to send the 2nd self ID packet, and the system can get benefit by tying this pin to digital VDD to reduce self ID packet exchange time. Test pin. Tied to VT6304 digital VDD ring for normal operations. On Chip Termination. If the capacitive isolation barrier is implemented between the VT6304 and LLC, tie this pin to VDD will utilize on chip resistors to replace on board 5K Ohms resistors pair for LREQ, CTL[0:1] and D[0:7] at PHY side. The resistors for LPS input at PHY side are also replaced if this pin is tied to VDD. This pin has effects on on-chip terminations only if ISO_ is tied to ground. Power Down. A logic High on this pin turns off all internal cicuitry except the connection detect circuits, which outputs the CNA signal. Reset (active low). The reset pin is connected to an internal 10K ohm resistor and an external 0.1 uF capacitor is used for internal reset generation at power-on. The pin can be left unconnected to save the external capacitors, and then the reset time after power-on ranges from 0.5 ms to 2 ms. This pin can also be driven by an open-drain type driver. Crystal Oscillator, 3.3V. These pins connect to a 24.576 MHz parallel resonant fundamental mode crystal. The optimum values for the external shnut capacitors are dependent on the specifications of the cystal used. The resulting frequency variation is +/- 100 ppm. Current setting resistor terminals. A resistor of 6.2 KOhm +/0.5% is required for internal operating currents generation. Analog receiver power. A combination of high-frequency decoupling capacitors near these pins are suggested. These pins are seperated from digital power for noise prevention. Analog receiver ground. These pins are tied together to the lowimpedance circuit board ground. 7 VIA Technologies, Inc. 95, 98, 12, 32 VDDATX supply 96, 97, 6, 19, 31 GNDATX supply 40, 85 VDDDC supply 39, 86 GNDDC supply 45, 59, 67, 73 VDDD supply 46, 56, 63, 71, 81 GNDD supply Preliminary VT6304 Analog transmitter power. A combination of high-frequency decoupling capacitors near these pins are suggested. These pins are seperated from digital power for noise prevention. Analog transmitter ground. These pins are tied together to the low-impedance circuit board ground. Digital core power. These pin are tied to low-impdance point on the circuit board. Digital core ground. These pins are tied together to the lowimpedance circuit board ground. Digital IO power. These pin are tied to low-impdance point on the circuit board. Digital IO ground. These pins are tied together to the lowimpedance circuit board ground. 8 VIA Technologies, Inc. Preliminary VT6304 FUNCTIONAL DESCRIPTIONS 1. GENERAL DESCRIPTION The VT6304 provides three-port physical layer function in a cable-based IEEE 1394-1995 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. Data bits to be transmitted through the cable ports are received from the Link on 2/4/8 data lines (D[0:7]), and are latched internally in the VT6304 in synchronization with the 49.152-MHZ system clock. These bits are combined serially, encoded, and transmitted at 98.304 , 196.608 or 393.216 Mbits/S as the outbound data-strobe information stream. During transmission, the encoded data transmitted differential on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the TPA cable pair(s). During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded Strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two or four parallel transmitted (repeated) out of the other active (connected) cable ports. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The output of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage for the presence of the remotely supplied twisted-pair bias voltage. The presence or absence of this common-mode voltage is used as an indication of cable connection status. The cable connection status signal is internally debounced in the VT6304 on a cable disconnect-to-connect. The debounced cable connection status signal initiates a bus reset. On a cable disconnect-to-connect a debounce delay is incorporated. There is no delay on a cable disconnect. 2. NETWORK INTERFACE 9 VIA Technologies, Inc. Preliminary VT6304 VT6304 REGISTERS Definitions and usage for each of the registers listed below are provided on this and the following pages: 3. PHY REGISTER MAP FOR THE CABLE ENVIRONMENT address 0000b 0001b 0010b 0011b 0100b 0101b 0 RHB 1 2 3 Physical_ID 5 6 R 7 PS Gap_count IBR Extended(7) Max_speed Link_acti Contender ve Resume_i ISBR Loop nt 0110b 0111b 1000b 4 Page_select 1111b reserved reserved Jitter Pwr_fail Total_ports Delay Pwr_class Timeout Port_even Enab_acc Enab_mul t el ti Reserved reserve Register0(page_select) Port_select Register7(page_select) 3.1. PHY REGISTER FIELDS FOR THE CABLE ENVIRONMENT size type default description Physical_ID 6 r - R PS RHB 1 1 1 r r rw 0 IBR 1 rw 0 Gap_count 6 rw 3F Extended Total_ports Max_speed 3 5 3 r r r 7 3 010 The address of this node determined during self-identification. A value of 63 indicates a malconfigured bus; the link shall not transmit any packets. When set to one, indicate that this node is the root. Cable Power status. Root hold-off bit. When set to one, instructs the PHY to attempt to become the root during the next tree identify process. Initiate bus reset. When set to one, instructs the PHY to initiate a bus reset immediately (without arbitration). This bit causes assertion of the reset state for 166 us and is self-clearing. Used to configure the arbitration timer setting in order to optimize gap times according to the topology of the bus. IEEE 1394-1995 4.3.6 constant value of seven the number of ports implemented by this PHY Indicates the maximum speed this PHY supports; 000 - 98.304 Mbit/s 001 - 98.304 and 196.608 Mbit/s 010 - ... and 393.216 Mbit/s 011 - ... and 786.43 Mbit/s 100 - nd 1,572.864 Mbit/s 101 - nd 3,145.728 Mbit/s all other values are reserved for future definition 10 VIA Technologies, Inc. Delay Link_active 4 1 R rw Contender 1 rw Pwr_class 3 rw Preliminary VT6304 0 1 Worse case repeater delay, expressed as 144+(delay*20)ns. Link enabled. Default value of one subsequent to a power reset. Otherwise cleared or set by software to control the value of the L bit transmitted in the self-ID packet. The transmitted L bit shall be the logical AND of this bit and the LPS signal. Pin Contender. Cleared or set by software to control the value of the C bit C/LKO transmitted in the self-ID packet. N Pin Power class. Controls the value of the pwr field transmitted in the self-ID PC0- packet. PC2 000 - Node does not need power and does not repeat power 001 - Node is self-powered and provides a minimum of 15 W to the bus 010 - Node is self-powered and provides a minimum of 30 W to bus. 011 - Node is self-powered and provides a minimum of 45 W to bus 100 - Node may be powered from the bus and is using up to 1 W. 101 - Node is powered from the bus and is using up to 1 W. additional 2 W is needed to enable the link and higher layers. 110 - Node is powered form the bus and is using up to 1 W. additional 5 W is needed to enable the link and higher layers. 111 - Node is powered from the bus and is using up to 1 W. additional 9 W is needed to enable the link and higher layers. Jitter 3 R 0 Resume_int 1 Rw 0 ISBR 1 rw 0 Loop Pwr_fail 1 1 rw rw 0 0 Timeout Port_event 1 1 rw rw 0 0 Enab_accel 1 rw 0 Enab_multi 1 rw 0 Page_select 3 rw 000 Port_select 4 rw 0000 the the An An An The difference between the fastest and slowest repeater data delay, expressed as (jitter+1)*20ns Resume interrupt enable. When set to one, the PHY shall set port_event to one if resume operations commence for any port. Initiate short (arbitrated) bus reset. A write of one to this bit instructs the PHY to arbitrate and issue a short bus reset. This bit is self-clearing. Loop detect. A write of one to this bit clears it to zero. Cable power failure detect. Set to one when the PS bit changes from one to zero. A write of one to this bit clears it to zero. Arbitration state machine timeout. A write of one to this bit clears it to zero. Port event detect. The PHY sets this bit to one if any of connected, Bias, Disabled or Fault change for a port whose Int_enable bit is one. The PHY also sets this bit to one if resume operations commence for any port and Resume_int is one. A write of one to this bit clears it to zero. Enable arbitration acceleration. When set to one, the PHY shall use the enhancements specification in P1394A. Enable multi-speed packet concatenation. When set to one, the Link shall signal the speed of all packets to the PHY. Selects which of eight possible PHY register pages are accessible through the window at PHY register address 1000b through 1111b, inclusive. If the page selected by Page_select presents per port information, this field selects which port’s registers are accessible through the window at PHY 11 VIA Technologies, Inc. Preliminary VT6304 register addressed 1000b through 1111b, inclusive. 3.2. PHY REGISTER PAGE0: PORT STATUS PAGE The port Status page is used to access configuration and status information for each of the PHY’s port. The port is selected by writing zero to Page_select and the desired port number to Port_select in the PHY register at address 0111. 0 1 2 AStat Negotiated_speed 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b 3 BStat Int_enable 4 Child Fault 5 connected 6 Bias 7 Disabled 3.3. PHY REGISTER PORT STATUS PAGE FIELDS Astat Size 2 Type default r - Bstat Child 2 1 r r - Conncted 1 r 0 Bias 1 r - Disabled 1 rw 0 Negotiated_sp eed 3 r - Description TPA line State for the port 00 = invalid 01 =1 10 =0 11 =z (same encoding as Astat) If equal to one, the port is a child, else a parent. The meaning of this bit is undefined from the time a bus reset is detected until the PHY transitions to state T1:Child Handshake during the tree identify process(see 4.4.2.2 in IEEE Std 1394-1995) If equal to one, the port is connected, else disconnected. The value reported by this bit is filtered by hysteresis logic to reduce multiple status changes caused by contact scrape when a connector is inserted or removed. If equal to one, bias voltage is detected( possible connection). The value reported by this bit is filtered by hysteresis logic to reduce multiple status changes caused by contact scrape when a connector is inserted or removed. When set to one, the port shall be disabled. The value of this bit subsequent to a power reset is implementation-dependent, but should be a strappable option. Indicated the maximum speed negotiated between this PHY port and its immediately connected port; the encoding is 000 – 98.304Mbit/s 001 - and 196.608 Mbit/s 12 VIA Technologies, Inc. Int_Enable 1 rw 0 Fault 1 Rw 0 Preliminary VT6304 010 - and 393.216 Mbit/s Enable port event interrupts. When set to one, the PHY shall set Port_event to one if any of Connected, Bias, Disabled or Fault (for this port) change state. Set to one if an error is detected during a suspend or resume operation. A write of one to this bit clears it to zero. 3.4. PHY REGISTER PAGE 1: VENDOR IDENTIFICATION PAGE The Vendor Identification page is used to identify the PHY’s vendor and compliance level. The page is selected by writing one to Page_select in the PHY register at address 0111. 0 1 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b 2 3 4 Compliance_level Reserved Vendor_ID 5 6 7 Product_ID 3.5. PHY REGISTER VENDOR IDENTIFICATION PAGE FIELDS Compliance_le vel Size 8 Vendor_ID 24 Product_ID 24 Type Description R Standard to which the PHY implementation complies: 0 = not specified 1 = IEEE P1394a All other values reserved for future standardization. The default is “1”. R The company ID or Organizationally Unique Identifier (OUI) of the manufacturer of the PHY. The most significant byte of Vendor_ID appears at PHY register location 1010 and the least significant at 1100. The default value is “00 40 63”. R The meaning of this number is determined by the company or organization that has been granted Vendor_ID. The most significant byte of Product_ID appears at PHY register location 1101 and the least significant at 1111. The default value is “30 60 00”. 3.6. PHY REGISTER PAGE 7: VENDOR-DEPENDENT PAGE The vendor-dependent page provides registers set aside for use by the PHY’s vendor. The page is selected by writing seven to Page_select in the PHY register at address 0111. Don’t access the registers “used for test”. address 0 1 2 3 4 5 6 7 1000b used for test 13 VIA Technologies, Inc. 1001b 1010b 1011b 1100b 1101b 1110b 1111b Preliminary VT6304 used for test used for test used for test used for test used for test Link_Speed Reserved used for test 3.7. PHY REGISTER VENDOR DEPENDENT PAGE FIELDS Link_Speed Size 2 Type Description RW Link speed. This field indicates the top speed capability of the attached LLC. Encoding is as follows : Vendor_ID 24 R Product_ID 24 R This field has the effect on the self-ID packets as well as the PHY speed capability which is exchanged between peer PHY during self-ID state. This field is set to 10b (S400) by hardware reset and is unchanged by bus-reset. The company ID or Organizationally Unique Identifier (OUI) of the manufacturer of the PHY. The most significant byte of Vendor_ID appears at PHY register location 1010 and the least significant at 1100. The default value is “00 e0 4c”. The meaning of this number is determined by the company or organization that has been granted Vendor_ID. The most significant byte of Product_ID appears at PHY register location 1101 and the least significant at 1111. The default value is “88 01 00”. 14 VIA Technologies, Inc. 4 4.1 4.2 Preliminary VT6304 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Supply Voltage (OVDD) -0.3 V to +3.6 V Supply Voltage (OVDD_AUX) -0.3 V to +3.6 V DC Output Voltage (VOUT) -0.3 V to VDD+0.3V Storage Temperature Range (TSTG) -40°C to 125°C Ambient Temperature (TA) 0 to 70°C Lead Temp. (TL) (Soldering, 10 sec) 250°C ESD Rating (RZAP = 1.5k, CZAP = 120 pF) 2.0 KV Input Latchup Current +/- 25mA Package Power Dissipation 3.0Watt@250C RECOMMENDED OPERATING CONDITIONS Supply voltage VDD 3.3 Volts ± 5% Supply voltage VDD 3.3 Volts ± 5% Supply Current (IDD) D0 State Supply Current (IDD_AUX) D0 State Supply Current (IDD_AUX) D3cold and PME Enable State Supply Current (IDD_AUX) D3cold and PME Disable State Supply Current (IDD) Low Power Mode Supply Current (IDD_AUX) Low Power Mode 15 VIA Technologies, Inc. Preliminary VT6304 5.3 DC Electrical characteristics 4.3.1 Link PHY Interface DC Specification Unless otherwise noted, all test conditions ate as follows: Table 1. DC Characteristics Functional Operating Range (VREF = 5V±5%, VCC = 3.3V±0.3V, TCASE = 0 to +85 Symbol Parameter Min Max Unit VIL1 Input Low Voltage 0.9 V VIH1 Input High Voltage 2.4 V VIL2 Input Low Voltage 1.1 V VIH2 Input High Voltage 2.2 V VIL3 Input Low Voltage 1.1 V VIH3 Input High Voltage 2.2 V VIL4 Input Low Voltage 0.9 V VIH4 Input High Voltage 2.1 V VOL1 Output Low Voltage 0.1Vcc V VOH1 Output High Voltage 0.9Vcc V VOL2 Output Low Voltage 0.1Vcc V VOH2 Output High Voltage 0.9Vcc V IOL1 Output Low Current 9.0 18.7 mA IOH1 Output High Current 8.2 16.2 mA IOL2 Output Low Current 8.5 17.8 mA IOH2 Output High Current 7.7 15.4 mA ILI1 Input Leakage Current 50 A ILI2 Hi-Z State Data Line Leakage 50 A CIN Input Capacitance 12 pF COUT Output Capacitance 12 pF CI/O I/O Capacitance 12 pF NOTES: 1. Refer to table 2 for the signals associated with this specification. Table 2. DC Characteristic Signal Association (Sheet 1 of 2) Symbol Associated Signals VIL1 / VIH1 **** Input Type 1 (1394) **** CNA, CTL[0:1], D[0:7], LINKON, LREQ, SCLK VIL2 / VIH2 **** Input Type 2 **** CMC, ISO_, ONCT, PC[0:2], TSI, TSO VIL3 / VIH3 **** Input Type 3 **** LPS, PD VIL4 / VIH4 **** Input Type 4 **** RESET_ VOL1 / VOH1 **** Output Type 1 **** CNA, CTL[0:1], D[0:7], LINKON, LREQ, SCLK VOL2 / VOH2 **** Output Type 2 **** CMC, ISO_, ONCT, PC[0:2], TSI, TSO IOL1 / IOH1 **** Output Type 1 **** CNA, CTL[0:1], D[0:7], LINKON, LREQ, SCLK IOL2 / IOH2 **** Output Type 2 **** CMC, ISO_, ONCT, PC[0:2], TSI, TSO Table 3. DC Current Characteristic 16 ) Notes 1 1 1 1 1 1 1 1 1 1 1 1 1, @ VOL1 1, @ VOH1 1, @ VOL2 1, @ VOH2 (0V < VIN < 3.3 V) FC = 1MHz FC = 1MHz FC = 1MHz VIA Technologies, Inc. Preliminary VT6304 Functional Operating Range (VREF = 5V±5%, VCC = 3.3V±0.3V, TCASE = 0 to +85 ) Symbol Parameter Typ Max Unit Notes ICC(3v) VCC Supply Current 110 155 mA ICC(SUS) ON Suspend Well Supply Current – Full On 3 5 mA ICC(SUS) Suspend Well Supply Current – Power On 30 150 A POS/STR Suspend or Suspend to RAM ICC(SUS) Suspend Well Supply Current – Suspend to Disk or 9 150 A STD/Soff Soft Off 4.3.3 Analog Signals DC Specification Unless otherwise noted, all test conditions ate as follows: 1. TA = 0 to +700C 2. VCC = 3.3V +/- 10% 3. 24.576 Mhz +/- 0.01% 4. REXT = 6.2 K +/- 1%, no load SYMBOL PARAMETER CONDITION MIN TYP MAX UNIT 1.5 Volt VIL Input Low Voltage OSCIN VIH Input High Voltage OSCIN IIL Input Low Current VIN=GND. OSCIN -150 µA IIH Input High Current VIN=VCC. OSCIN 150 µA VOL Output Low Voltage IOL= -4 mA TPO± 0.4 Volt 1 Volt 3.5 Volt IOL= -20 mA, PLED[3:0]# VOH Output High Voltage CIN Input Capacitance ICC VCC Supply Current IOH= 4 mA TPO± VCC-1.0 Volt IOH= 4 µA PLED[3:2]# VCC-1.0 Volt IOH= 6 µA PLED[1:0]# 2.4 Volt 5 pF Transmitting, 100Mbps, 4 portss 170 mA Transmitting, 200Mbps, 4 ports 220 mA 17 VIA Technologies, Inc. Preliminary VT6304 Transmitting, 400 Mbps, 4 ports 280 mA Powerdown Mode 0.1 mA 18 VIA Technologies, Inc. Preliminary VT6304 Package Diminsion Unit Millimeter/Inch 2.72/.107 3.40MAX 0.88/.035 0.25/.01MIN 0.15MAX 1.6/.063 0.15+0.102 / 0.15-0.051 0~7 o Unit Millimeter/Inch 23.2/.913 20.0/0.787 80 51 81 50 14.0/.551 17.2/.677 31 100 1 30 0.2+0.030 / 0.008+0.001 0.5/.020 19 VIA Technologies, Inc. Preliminary VT6304 [This page left to blank] 20 VIA Technologies, Inc. Preliminary VT6101/VT6102 21