INTEGRATED CIRCUITS 74ALVCH16601 18-bit universal bus transceiver (3-State) Product specification Supersedes data of 1998 Aug 31 IC24 Data Handbook 1998 Sep 24 Philips Semiconductors Product specification 18-bit universal bus transceiver (3-State) FEATURES 74ALVCH16601 DESCRIPTION • Complies with JEDEC standard no. 8-1A • CMOS low power consumption • Direct interface with TTL levels • MULTIBYTETM flow-through standard pin-out architecture • Low inductance multiple VCC and ground pins for minimum noise The 74ALVCH16601 is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is High. When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level. If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the Low-to-High transition of CPAB. When OEAB is Low, the outputs are active. When OEAB is High, the outputs are in the high-impedance state. The clocks can be controlled with the clock-enable inputs (CEBA/CEAB). and ground bounce • Current drive ± 24 mA at 3.0 V • All inputs have bus hold circuitry • Output drive capability 50Ω transmission lines @ 85°C Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. To ensure the high impedance state during power up or power down, OEBA and OEAB should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf = 2.5 ns PARAMETER SYMBOL tPHL/tPLH Propagation delay An, Bn to Bn, An CI/O Input/Output capacitance CI Input capacitance CPD CONDITIONS VCC = 2.5V, CL = 30pF VCC = 3.3V, CL = 50pF Power dissipation capacitance per latch VI = GND to VCC1 TYPICAL UNIT 3.1 2.8 ns 8.0 pF 4.0 pF Outputs enabled 21 Outputs disabled 3 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC2 × fo) = sum of outputs. ORDERING INFORMATION PACKAGES 56-Pin Plastic TSSOP Type II 1998 Sep 24 TEMPERATURE RANGE OUTSIDE NORTH AMERICA DWG NUMBER –40°C to +85°C 74ALVCH16601 DGG SOT364-1 2 853-2122 20076 Philips Semiconductors Product specification 18-bit universal bus transceiver (3-State) PIN CONFIGURATION PIN DESCRIPTION PIN NUMBER SYMBOL 1 OEAB Output enable A-to-B 2 LEAB Latch enable A-to-B 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26 A0 to A17 Data inputs/outputs B4 4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V) 7, 22, 35, 50 VCC Positive supply voltage 27 OEBA Output enable B-to-A 28 LEBA Latch enable B-to-A OEAB 1 56 CEAB LEAB 2 55 CPAB A0 3 54 B0 GND 4 53 GND A1 5 52 B1 A2 6 51 B2 VCC 7 50 VCC A3 8 49 B3 A4 9 48 A5 10 47 B5 GND 11 46 GND A6 12 45 B6 13 44 B7 A8 14 43 B8 29 CEBA Clock enable B-to-A 30 CPBA Clock input B-to-A 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 B0 to B17 Data inputs/outputs 55 CPAB Clock input A-to-B 56 CEAB Clock enable A-to-B A9 15 42 B9 A10 16 41 B10 A11 17 40 B11 GND 18 39 GND A12 19 38 B12 A13 20 37 B13 A14 21 36 B14 VCC 22 35 VCC A15 23 34 B15 A16 24 33 B16 GND 25 32 GND A17 26 31 B17 OEBA 27 30 CPBA LEBA 28 29 CEBA LOGIC SYMBOL 55 56 3 5 A0 A1 B0 B1 54 52 6 8 9 10 A2 A3 A4 A5 B2 B3 B4 B5 51 49 48 47 12 13 14 15 A6 A7 A8 A9 B6 B7 B8 B9 45 44 43 42 16 17 19 20 A10 A11 A12 A13 B10 B11 B12 B13 41 40 38 37 21 23 24 26 A14 A15 A16 A17 B14 B15 B16 B17 36 34 33 31 OEAB OEBA LEAB CPAB CEAB LEBA 27 28 CPBA CEBA 30 29 SW00130 1998 Sep 24 NAME AND FUNCTION A7 SW00129 1 2 74ALVCH16601 3 Philips Semiconductors Product specification 18-bit universal bus transceiver (3-State) 74ALVCH16601 LOGIC DIAGRAM (one section) OEAB CEAB LEAB CPAB CPBA LEBA CEBA OEBA CE C1 CP 1D A1 B1 CE C1 CP 1D 18 IDENTICAL CHANNELS SW00132 FUNCTION TABLE INPUTS XX H L h l X ↑ NC Z CEXX OEXX X X X = = = = = = = = = DATA OUTPUTS STATUS LEXX CPXX H X X X Z Disabled L L H H X X H L H L Transparent H L L X X NC L L L L L L ↑ ↑ h l H L L L L L L L L H X X NC AB for A-to-B direction, BA for B-to-A direction HIGH voltage level LOW voltage level HIGH state must be present one setup time before the LOW-to-HIGH transition of CPXX LOW state must be present one setup time before the LOW-to-HIGH transition of CPXX Don’t care LOW-to-HIGH level transition No change High impedance “off ” state 1998 Sep 24 4 Hold Clock + display Hold Philips Semiconductors Product specification 18-bit universal bus transceiver (3-State) LOGIC SYMBOL (IEEE/IEC) OEAB CEAB CPAB LEAB 1 56 BUSHOLD CIRCUIT EN1 VCC G2 55 2 74ALVCH16601 2C3 C3 G2 OEBA CEBA CPBA LEBA 27 EN4 29 G5 30 28 Data Input To internal circuit 5C6 C6 G5 A0 3 3D 4 1 54 B0 6D A1 5 52 B1 A2 6 51 B2 A3 8 49 B3 A4 9 48 B4 A5 10 47 B5 A6 12 45 B6 A7 13 44 B7 A8 14 43 B8 A9 15 42 B9 A10 16 41 B10 A11 17 40 B11 A12 19 38 B12 A13 20 37 B13 A14 21 36 B14 A15 23 34 B15 A16 24 33 B16 A17 26 31 B17 SW00050 SW00133 1998 Sep 24 5 Philips Semiconductors Product specification 18-bit universal bus transceiver (3-State) 74ALVCH16601 RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC PARAMETER CONDITIONS UNIT MIN MAX DC supply voltage 2.5V range (for max. speed performance @ 30 pF output load) 2.3 2.7 DC supply voltage 3.3V range (for max. speed performance @ 50 pF output load) 3.0 3.6 V VI DC Input voltage range 0 VCC V VO DC output voltage range 0 VCC V –40 +85 °C 0 0 20 10 ns/V Tamb Operating free-air temperature range tr, tf Input rise and fall times VCC = 2.3 to 3.0V VCC = 3.0 to 3.6V ABSOLUTE MAXIMUM RATINGS In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK PARAMETER CONDITIONS DC supply voltage DC input diode current VI 0 DC output diode current VO VCC or VO 0 DC output voltage Note 1 IO DC output source or sink current VO = 0 to VCC DC VCC or GND current Storage temperature range For temperature range: –40 to +125 °C above +55°C derate linearly with 8 mW/K NOTE: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Sep 24 –50 mA –0.5 to VCC +0.5 VO PTOT V For data inputs1 IOK Power dissipation per package –plastic thin-medium-shrink (TSSOP) –0.5 to +4.6 –0.5 to +4.6 DC in input ut voltage Tstg UNIT For control pins1 VI IGND, ICC RATING 6 V 50 mA –0.5 to VCC +0.5 V 50 mA 100 mA –65 to +150 °C 600 mW Philips Semiconductors Product specification 18-bit universal bus transceiver (3-State) 74ALVCH16601 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER VIH HIGH level Input voltage VIL LOW level Input voltage VOH O HIGH level output voltage TEST CONDITIONS Temp = -40°C to +85°C MIN TYP1 VCC = 2.3 to 2.7V 1.7 1.2 VCC = 2.7 to 3.6V 2.0 1.5 UNIT MAX V VCC = 2.3 to 2.7V 1.2 0.7 VCC = 2.7 to 3.6V 1.5 0.8 V 3 to 3 6V; VI = VIH or VIL; IO = –100µA 100µA VCC = 2 2.3 3.6V; 02 VCC0.2 VCC VCC = 2.3V; VI = VIH or VIL; IO = –6mA VCC0.3 VCC0.08 VCC = 2.3V; VI = VIH or VIL; IO = –12mA VCC0.6 VCC0.26 VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC0.5 VCC0.14 VCC = 3.0V; VI = VIH or VIL; IO = –12mA VCC0.6 VCC0.09 VCC = 3.0V; VI = VIH or VIL; IO = –24mA VCC1.0 VCC0.28 V VCC = 2 2.3 3 to 3 3.6V; 6V; VI = VIH or VIL; IO = 100µA GND 0 20 0.20 V VCC = 2.3V; VI = VIH or VIL; IO = 6mA 0.07 0.40 V VCC = 2.3V; VI = VIH or VIL; IO = 12mA 0.15 0.70 VCC = 2.7V; VI = VIH or VIL; IO = 12mA 0.14 0.40 VCC = 3.0V; VI = VIH or VIL; IO = 24mA 0.27 0.55 Input leakage g current VCC = 2 2.3 3 to 3 3.6V; 6V; VI = VCC or GND 0.1 5 µA µ IOZ 3-State output OFF-state current VCC = 2.7 to 3.6V; VI = VIH or VIL; VO = VCC or GND 0.1 10 µA ICC Quiescent supply current VCC = 2.3 to 3.6V; VI = VCC or GND; IO = 0 0.2 40 µA ∆ICC Additional quiescent supply current VCC = 2.3V to 3.6V; VI = VCC – 0.6V; IO = 0 150 750 µA IBHL Bus hold LOW sustaining current IBHH Bus hold HIGH sustaining current IBHLO Bus hold LOW overdrive current VCC = 3.6V2 500 µA IBHHO Bus hold HIGH overdrive current VCC = 3.6V2 –500 µA VOL II LOW level output voltage VCC = 2.3V; VI = 0.7V2 45 – 0.8V2 75 150 VCC = 2.3V; VI = 1.7V2 –45 2.0V2 –75 VCC = 3.0V; VI = VCC = 3.0V; VI = NOTES: 1. All typical values are at Tamb = 25°C. 2. Valid for data inputs of bus hold parts. 1998 Sep 24 7 –175 V µA µA Philips Semiconductors Product specification 18-bit universal bus transceiver (3-State) 74ALVCH16601 AC CHARACTERISTICS FOR VCC = 2.3V TO 2.7V RANGE GND = 0V; tr = tf ≤ 2.0ns; CL = 30pF LIMITS SYMBOL PARAMETER Propagation delay An, Bn to Bn, An tPHL/tPLH Propagation delay LEAB, LEBA to Bn, An VCC = 2.5V ± 0.2V WAVEFORM 1, 2 Propagation delay CPAB, CPBA to Bn, An UNIT MIN TYP1 MAX 1.0 3.1 5.2 1.0 3.6 6.2 1.0 3.4 5.9 ns tPZH/tPZL 3-State output enable time OEBA, OEAB to An,Bn 3 1.1 3.1 5.3 ns tPHZ/tPLZ 3-State output enable time OEBA, OEAB to An,Bn 3 1.4 2.8 4.9 ns 3.3 1.6 – Pulse width HIGH or LOW CPAB, CPBA 3.3 2.0 – Set-up time An, Bn to CPAB, CPBA 2.3 –0.2 – 1.3 0.1 – Set-up time CEAB, CEBA to CPAB, CPBA 2.0 –0.4 – Hold time An, Bn to CPAB, CPBA 1.2 0.3 – 1.3 0.2 – Hold time CEAB, CEBA to CPAB, CPBA 1.1 0.4 – Maximum clock frequency 150 390 – tW tSU th fMAX Pulse width HIGH LEAB or LEBA 2 Set-up time An, Bn to LEAB, LEBA 4 Hold time An, Bn to LEAB, LEBA 4 NOTE: 1. All typical values are at VCC = 2.5V and Tamb = 25°C. 1998 Sep 24 8 ns ns ns MHz Philips Semiconductors Product specification 18-bit universal bus transceiver (3-State) 74ALVCH16601 AC CHARACTERISTICS FOR VCC = 3.0V TO 3.6V RANGE AND VCC = 2.7V GND = 0V; tr = tf = 2.5ns; CL = 50pF LIMITS SYMBOL PARAMETER WAVEFORM Propagation delay An, Bn to Bn, An tPHL/tPLH Propagation delay LEAB, LEBA to Bn, An 1, 2 Propagation delay CPAB, CPBA to Bn, An VCC = 3.3V ±0.3V MIN TYP1 MAX 1.0 2.8 1.0 VCC = 2.7V MIN UNIT TYP MAX 4.2 3.1 4.7 3.1 4.9 3.4 5.4 1.3 3.1 5.0 3.5 5.8 ns tPZH/tPZL 3-State output enable time OEBA to An 3 1.1 2.8 5.2 3.3 6.1 ns tPHZ/tPLZ 3-State output disable time OEBA to An 3 1.2 3.2 4.4 3.3 4.8 ns 3.3 0.9 3.3 0.7 LE pulse width HIGH or LOW CPAB, CPBA 3.3 0.9 3.3 1.2 Set-up time An, Bn to CPAB, CPBA 2.1 –0.2 2.4 0.0 1.1 0.3 1.2 –0.2 Set-up time CEAB, CEBA to CPAB, CPBA 1.7 –0.2 2.0 –0.7 Hold time An, Bn to CPAB, CPBA 1.0 –0.1 1.1 0.3 1.4 0.1 1.6 0.1 Hold time CEAB, CEBA to CPAB, CPBA 1.1 0.4 1.2 0.6 Maximum clock frequency 150 340 150 333 tW tSU th fMAX LE pulse width LEAB, LEBA to CPAB, CPBA Set-up time An, Bn to LEAB, LEBA Hold time An, Bn to LEAB, LEBA 2 ns 4 4 NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 1998 Sep 24 9 ns ns MHz Philips Semiconductors Product specification 18-bit universal bus transceiver (3-State) ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ AC WAVEFORMS VCC = 2.3 TO 2.7 V RANGE 1. VM = 0.5 V 2. VX = VOL + 0.15V 3. VY = VOH – 0.15V 4. VI = VCC 5. VOL and VOH are the typical output voltage drop that occur with the output load. VCC = 3.0 TO 3.6 V RANGE AND VCC = 2.7 V 1. VM = 1.5 V 2. VX = VOL + 0.3V 3. VY = VOH – 0.3V 4. VI = 2.7 V 5. VOL and VOH are the typical output voltage drop that occur with the output load. VI An, Bn INPUT VM GND th th tSU tSU VI CPXX, LEXX INPUT VM GND NOTE: The unshaded areas indicate when the input is permitted to change for predictable output performance. SW00128 VI An, Bn INPUT 74ALVCH16601 Waveform 4. Data set-up and hold times for the An and Bn inputs to the LEAB, LEBA, CPAB and CPBA inputs VM GND tPHL TEST CIRCUIT tPLH VOH S1 VCC Bn, An OUTPUT 2VCC Open GND VM VOL RL=500 Ω SW00063 VIN Waveform 1. Input (An, Bn) to output (Bn, An) propagation delays PULSE GENERATOR LEXX INPUT CPXX INPUT D.U.T. RT 1/fmax VI VOUT VM RL=500 Ω CL Test Circuit for 3-State Outputs SWITCH POSITION GND tW tPHL VOH tPLH An, Bn OUTPUT VM VOL TEST SWITCH VCC VIN tPLH/tPHL Open tPLZ/tPZL 2VCC 2.7V 2.7 – 3.6V VCC 2.7V tPHZ/tPZH GND SW00134 DEFINITIONS RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. Waveform 2. Latch enable input (LEAB, LEBA) and clock pulse input (CPAB, CPBA) to output propagation delays and their pulse width VI SW00047 OEXX INPUT Load circuitry for switching times VM GND tPLZ tPZL VCC OUTPUT LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ tPZH VOH VY OUTPUT HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled SW00127 Waveform 3. 3-State enable and disable times 1998 Sep 24 10 Philips Semiconductors Product specification 18-bit universal bus transceiver (3-State) TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm 1998 Sep 24 11 74ALVCH16601 SOT364-1 Philips Semiconductors Product specification 18-bit universal bus transceiver (3-State) 74ALVCH16601 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 06-98 Document order number: 1998 Sep 24 12 9397–750–04798