PHILIPS 74LVC543APW

INTEGRATED CIRCUITS
74LVC543A
Octal D-type registered transceiver
(3-State)
Product specification
Supersedes data of 1997 Jun 30
IC24 Data Handbook
1998 Jul 31
Philips Semiconductors
Product specification
Octal D-type registered transceiver (3-State)
FEATURES
74LVC543A
DESCRIPTION
• 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
• Supply voltage range of 1.2V to 3.6V
• Complies with JEDEC standard no. 8–1A
• CMOS low power consumption
• Direct interface with TTL levels
• 8-bit octal transceiver with D-type latch
• Back-to-back registers for storage
• Separate controls for data flow in each direction
• 3-State non-inverting outputs for bus oriented applications
• High impedance when VCC = 0V
The 74LVC543A is a high–performance, low–power, low–voltage,
Si–gate CMOS device and superior to most advanced CMOS
compatible TTL families.
The 74LVC543A is an octal registered transceiver containing two
sets of D–type latches for temporary storage of the data flow in
either direction. Separate latch enable (LEAB, LEBA) and output
enable (OEAB, OEBA) inputs are provided for each register to permit
independent control of inputting and outputting in either direction of
the data flow.
The 74LVC543A contains eight D–type latches, with separate inputs
and controls for each set. For data flow from A to B, for example, the
A–to–B enable (EAB) input must be LOW in order to enter data from
A0–A7 or take data from B0–B7, as indicated in the function table.
With EAB LOW, a LOW signal on the A–to–B latch enable (LEAB)
input makes the A–to–B latches transparent; a subsequent LOW–to
HIGH transition of the LEAB signal puts the A data into the latches
where it is stored and the B outputs no longer change with the A
inputs. With EAB and OEAB both low, the 3–state B output buffers
are active and display the data present at the outputs of the A
latches
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; Tr = Tf ≤ 2.5ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
CL = 50 pF
VCC = 3.3V
3.3
ns
tPHL/tPLH
Propagation delay
An to Bn
CI
input capacitance
5.0
pF
CI/O
input/output capacitance
10.0
pF
CPD
power dissipation capacitance per latch
27
pF
VCC = 3.3V
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD x VCC2 x fi +Σ (CL x VCC2 x fo ) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
Σ (CL x VCC2 x fo ) = sum of the outputs
2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES
TEMPERATURE
RANGE
OUTSIDE NORTH
AMERICA
NORTH AMERICA
PKG DWG. #
24-Pin Plastic Small Outline (SO)
–40°C to +85°C
74LVC543A D
74LVC543A D
SOT137-1
24-Pin Plastic Shrink Small Outline (SSOP) Type II
–40°C to +85°C
74LVC543A DB
74LVC543A DB
SOT340-1
24-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I
–40°C to +85°C
74LVC543A PW
7LVC543APW DH
SOT355-1
1998 Jul 31
2
853-1992 19813
Philips Semiconductors
Product specification
Octal D-type registered transceiver (3-State)
PIN CONFIGURATION
74LVC543A
LOGIC SYMBOL
LEBA
1
24 VCC
OEBA
2
23 EAB
A0
3
22 B0
3
A0
B0
22
A1
4
21 B1
4
A1
B1
21
5
A2
B2
20
6
A3
B3
19
7
A4
B4
18
8
A5
B5
17
5
A2
20 B2
A3
6
19 B3
A4
7
18 B4
A5
8
17 B5
9
A6
B6
16
A6
9
16 B6
10
A7
B7
15
A7 10
15 B7
EBA 11
14 LEAB
2 OEBA
GND 12
13 OEAB
13 OEAB
11 EBA
SW00212
23 EAB
14 LEAB
PIN DESCRIPTION
1 LEBA
PIN NUMBER
SYMBOL
FUNCTION
1
LEBA
’B’ to ’A’ latch enable input
(active LOW)
2
OEBA
’B’ to ’A’ output enable
input (active LOW)
3,4,5,6, 7, 8, 9 10
A0 to A7
’A’ data inputs/outputs
11
EBA
’B’ to ’A’ enable input
(active LOW)
SW00213
LOGIC SYMBOL (IEEE/IEC)
2
12
GND
23
1
ground (0V)
13
11
1EN3
G1
1C5
2EN4
22, 21, 20, 19,
18, 17, 16, 15
B0 to B7
’B’ data inputs/outputs
14
13
OEAB
’A’ to ’B’ output enable
input (active LOW)
3
14
LEAB
’A’ to ’B’ latch enable input
(active LOW)
4
21
5
20
6
19
7
18
8
17
9
16
10
15
23
24
EAB
VCC
’A’ to ’B’ enable input
(active LOW)
positive supply voltage
G2
2C6
∇3
5D
6D
4∇
22
SW00214
1998 Jul 31
3
Philips Semiconductors
Product specification
Octal D-type registered transceiver (3-State)
74LVC543A
LOGIC DIAGRAM
OEBA
EBA
LEBA
OEAB
EAB
LEAB
LE
D
Bn
An
LE
D
8 IDENTICAL
CHANNELS
TO 7 OTHER CHANNELS
SW00215
FUNCTION TABLE
INPUTS
OPERATING MODES
NOTES:
XX =
H
=
L
=
h
=
l
=
X
=
↑
=
NC =
Z
=
OUTPUTS
OEXX
EXX
LEXX
DATA
Disabled
H
X
X
X
Z
Disabled
X
H
X
X
Z
Disabled + Latch
L
L
↑
↑
L
L
h
l
Z
Z
Latch + Display
L
L
L
L
↑
↑
h
l
H
L
Transparent
L
L
L
L
L
L
H
L
H
L
Hold
(do nothing)
L
L
H
X
NC
AB for A-to-B direction, BA for B-to-A direction
High voltage level
Low voltage level
High state must be present one setup time before the Low-to-High transition of LEAB, LEBA, EAB, EBA
Low state must be present one setup time before the Low-to-High transition of LEAB, LEBA, EAB, EBA
Don’t care
Low-to-High level transition
No change
High impedance OFF state
1998 Jul 31
4
Philips Semiconductors
Product specification
Octal D-type registered transceiver (3-State)
74LVC543A
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN
MAX
VCC
DC supply voltage (for max. speed performance)
2.7
3.6
V
VCC
DC supply voltage (for low-voltage applications)
1.2
3.6
V
DC Input voltage range
0
5.5
V
DC Output voltage range; output HIGH or LOW
state
0
VCC
V
VI
VI/O
DC input voltage range; output 3-State
Tamb
Operating ambient temperature range in free-air
tr, tf
Input rise and fall times
VCC = 1.2 to 2.7V
VCC = 2.7 to 3.6V
0
5.5
V
–40
+85
°C
0
0
20
10
ns/V
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
PARAMETER
SYMBOL
VCC
CONDITIONS
UNIT
–0.5 to +6.5
V
IIK
DC input diode current
VI 0
–50
mA
VI
DC input voltage
Note 2
–0.5 to +6.5
V
IOK
DC output diode current
VO VCC or VO 0
50
mA
DC output voltage; output HIGH or LOW state
Note 2
–0.5 to VCC +0.5
V
DC input voltage; output 3-State
Note 2
–0.5 to 6.5
V
DC output source or sink current
VO = 0 to VCC
50
mA
100
mA
–65 to +150
°C
500
500
mW
VI/O
IO
IGND, ICC
Tstg
PTOT
DC supply voltage
RATING
DC VCC or GND current
Storage temperature range
Power dissipation per package
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jul 31
5
Philips Semiconductors
Product specification
Octal D-type registered transceiver (3-State)
74LVC543A
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
MIN
VIH
HIGH level Input voltage
VIL
LOW level Input voltage
VOH
O
VCC = 1.2V
VCC
VCC = 2.7 to 3.6V
2.0
TYP1
V
VCC = 1.2V
GND
V
VCC = 2.7 to 3.6V
HIGH level output voltage
0.8
VCC = 2.7V; VI = VIH or VIL; IO = –12mA
VCC0.5
VCC = 3.0V; VI = VIH or VIL; IO = –100µA
VCC0.2
VCC = 3.0V; VI = VIH or VIL; IO = –18mA
VCC0.6
VCC = 3.0V; VI = VIH or VIL; IO = –24mA
VCC0.8
VCC
VCC = 2.7V; VI = VIH or VIL; IO = 12mA
VOL
LOW level output voltage
VCC = 3.0V; VI = VIH or VIL; IO = 100µA
GND
0.20
V
0.55
0.1
5
µA
0.1
15
µA
VCC = 3.6V; VI = VIH or VIL; VO = 5.5V or GND
0.1
10
µA
Power off leakage supply
VCC = 0.0V; VI or VO = 5.5V
0.1
10
µA
Quiescent supply current
VCC = 3.6V; VI = VCC or GND; IO = 0
0.1
10
µA
Additional quiescent supply current
per input pin
VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0
5
500
µA
Input leakage current
VCC = 3.6V; VI = 5.5V or GND
IIHZ/IILZ
Input current for common I/O pins
VCC = 3.6V; VI = 5.5V or GND
IOZ
3-State output OFF-state current
Ioff
ICC
∆ICC
V
0.40
VCC = 3.0V; VI = VIH or VIL; IO = 24mA
II
UNIT
MAX
Not for I/O pins
NOTE:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
AC CHARACTERISTICS
GND = 0V; tr = tf =2.5ns; CL = 50pF
LIMITS
SYMBOL
PARAMETER
VCC = 3.3V ±0.3V
WAVEFORM
VCC = 2.7V
VCC = 1.2V
MIN
TYP1
MAX
MIN
MAX
TYP
UNIT
tPHL
tPLH
Propagation delay
An to Bn, Bn to An
1, 5
1.5
3.3
7
1.5
8
13.0
ns
tPHL
tPLH
Propagation delay
LEBA to An, LEAB to Bn,
2, 5
1.5
4.1
8.5
1.5
9.5
16.0
ns
tPZH
tPZL
3-State output enable time
OEBA to An, OEAB to Bn,
3, 5
1.5
4.2
7.7
1.5
9.2
15.0
ns
tPHZ
tPLZ
3-State output disable time
OEBA to An, OEAB to Bn,
3, 5
1.5
3.4
7.0
1.5
7.5
8.0
ns
tPZH
tPZL
3-State output enable time
EBA to An, EAB to Bn,
3, 5
1.5
4.4
8.0
1.5
9.3
15.0
ns
tPHZ
tPLZ
3-State output disable time
EBA to An, EAB to Bn,
3, 5
1.5
3.6
7.0
1.5
7.5
8.0
ns
tW
LEXX pulse width LOW
2
3.0
0.9
–
3.0
–
4.0
ns
tsu
Set-up time
An/Bn to LEXX, An/Bn to EXX
4
1.5
–0.5
–
1.5
–
–1.5
ns
th
Hold time
An/Bn to LEXX, An/Bn to EXX
4
1.5
0.6
–
1.5
–
2.0
ns
NOTE:
1. These typical values are at VCC = 3.3V and Tamb = 25°C.
1998 Jul 31
6
Philips Semiconductors
Product specification
Octal D-type registered transceiver (3-State)
74LVC543A
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V.
VOL and VOH are the typical output voltage drop that occur with the output load.
VX = VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V
VY = VOH –0.3V at VCC w 2.7V; VY = VOH – 0.1 VCC at VCC t 2.7V
VI
VI
INPUT
An, Bn
INPUT
VM
GND
GND
ÉÉÉ ÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉ ÉÉÉÉÉÉÉ
ÉÉÉ
VM
th
tPHL
VOH
tPLH
th
tSU
tSU
VI
OUTPUT
LEXX, EXX
INPUT
VM
VM
GND
VOL
SY00041
Waveform 1.
delays.
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
Input (An, Bn) to output (Bn, An) propagation
SW00211
Waveform 4. Data setup and hold times for the (An, Bn) input
to the LEXX and EXX inputs.
VI
VM
LEXX INPUT
VM
VM
TEST CIRCUIT
GND
tw
tPHL
An, Bn
OUTPUT
VM
2<VCC
Open
GND
VM
RL=500 Ω
VOL
VOUT
VIN
PULSE
GENERATOR
SA00408
Waveform 2. Latch enable input (LEXX) pulse width and the
latch enable input to output (An, Bn) propagation delays.
D.U.T.
RT
VI
OEXX, EXX
INPUT
S1
VCC
tPLH
VOH
RL=500 Ω
CL
Test Circuit for 3-State Outputs
SWITCH POSITION
VM
GND
tPLZ
tPZL
VCC
OUTPUT
LOW-to-OFF
OFF-to-LOW
SWITCH
VCC
VIN
Open
tPLZ/tPZL
2<VCC
t 2.7V
2.7 – 3.6V
VCC
2.7V
tPHZ/tPZH
GND
DEFINITIONS
RL = Load resistor
CL = Load capacitance includes jig and probe capacitance
RT = Termination resistance should be equal to ZOUT
of pulse generators.
VM
VX
VOL
tPHZ
TEST
tPLH/tPHL
tPZH
SW00047
VOH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
Waveform 5.
VY
VM
GND
outputs
enabled
outputs
disabled
outputs
enabled
SW00210
Waveform 3.
1998 Jul 31
3-State enable and disable times
7
Load circuitry for switching times.
Philips Semiconductors
Product specification
Octal D-type registered transceiver (3-State)
SO16: plastic small outline package; 16 leads; body width 3.9 mm
1998 Jul 31
8
74LVC543A
SOT109-1
Philips Semiconductors
Product specification
Octal D-type registered transceiver (3-State)
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
1998 Jul 31
9
74LVC543A
SOT338-1
Philips Semiconductors
Product specification
Octal D-type registered transceiver (3-State)
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
1998 Jul 31
10
74LVC543A
SOT403-1
Philips Semiconductors
Product specification
Octal D-type registered transceiver (3-State)
NOTES
1998 Jul 31
11
74LVC543A
Philips Semiconductors
Product specification
Octal D-type registered transceiver (3-State)
74LVC543A
DEFINITIONS
Data Sheet Identification
Product Status
Definition
Objective Specification
Formative or in Design
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
Preliminary Specification
Preproduction Product
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Product Specification
Full Production
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code
Document order number:
Date of release: 05-96
9397-750-04511