PHILIPS PHP13N40E

Philips Semiconductors
Product specification
PowerMOS transistors
Avalanche energy rated
FEATURES
PHP13N40E, PHB13N40E, PHW13N40E
SYMBOL
• Repetitive Avalanche Rated
• Fast switching
• Stable off-state characteristics
• High thermal cycling performance
• Low thermal resistance
QUICK REFERENCE DATA
d
VDSS = 400 V
ID = 13.7 A
g
RDS(ON) ≤ 0.35 Ω
s
GENERAL DESCRIPTION
N-channel, enhancement mode field-effect power transistor, intended for use in off-line switched mode power supplies,
T.V. and computer monitor power supplies, d.c. to d.c. converters, motor control circuits and general purpose switching
applications.
The PHP13N40E is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHW13N40E is supplied in the SOT429 (TO247) conventional leaded package.
The PHB13N40E is supplied in the SOT404 surface mounting package.
PINNING
PIN
SOT78 (TO220AB)
DESCRIPTION
1
gate
2
drain1
3
source
SOT404
SOT429 (TO247)
tab
tab
2
tab
drain
1 23
1
1
3
2
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDSS
VDGR
VGS
ID
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Tj = 25 ˚C to 150˚C
Tj = 25 ˚C to 150˚C; RGS = 20 kΩ
IDM
PD
Tj, Tstg
Pulsed drain current
Total dissipation
Operating junction and
storage temperature range
- 55
400
400
± 30
13.7
8.7
55
156
150
V
V
V
A
A
A
W
˚C
Tmb = 25 ˚C; VGS = 10 V
Tmb = 100 ˚C; VGS = 10 V
Tmb = 25 ˚C
Tmb = 25 ˚C
1 It is not possible to make connection to pin 2 of the SOT404 package.
December 1998
1
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistors
Avalanche energy rated
PHP13N40E, PHB13N40E, PHW13N40E
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
EAS
EAR
IAS, IAR
CONDITIONS
MIN.
MAX.
UNIT
-
705
mJ
-
18
mJ
-
13.7
A
Non-repetitive avalanche
energy
Unclamped inductive load, IAS = 13.6 A;
tp = 0.2 ms; Tj prior to avalanche = 25˚C;
VDD ≤ 50 V; RGS = 50 Ω; VGS = 10 V
Repetitive avalanche energy2 IAR = 13.7 A; tp = 2.5 µs; Tj prior to
avalanche = 25˚C; RGS = 50 Ω; VGS = 10 V
Repetitive and non-repetitive
avalanche current
THERMAL RESISTANCES
SYMBOL PARAMETER
Rth j-mb
Rth j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
MIN.
SOT78 package, in free air
SOT429 package, in free air
SOT404 package, pcb mounted, minimum
footprint
TYP. MAX. UNIT
-
-
0.8
K/W
-
60
45
50
-
K/W
K/W
K/W
ELECTRICAL CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
V(BR)DSS
VGS = 0 V; ID = 0.25 mA
400
-
-
V
VDS = VGS; ID = 0.25 mA
-
0.1
-
%/K
2.0
4
-
0.26
3.0
7.5
1
50
10
0.35
4.0
25
500
200
Ω
V
S
µA
µA
nA
Drain-source breakdown
voltage
∆V(BR)DSS / Drain-source breakdown
∆Tj
voltage temperature
coefficient
Drain-source on resistance
RDS(ON)
VGS(TO)
Gate threshold voltage
gfs
Forward transconductance
Drain-source leakage current
IDSS
TYP. MAX. UNIT
IGSS
VGS = 10 V; ID = 6.5 A
VDS = VGS; ID = 0.25 mA
VDS = 30 V; ID = 6.5 A
VDS = 400 V; VGS = 0 V
VDS = 320 V; VGS = 0 V; Tj = 125 ˚C
Gate-source leakage current VGS = ±30 V; VDS = 0 V
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 13 A; VDD = 320 V; VGS = 10 V
-
79
7.2
43
100
12
55
nC
nC
nC
td(on)
tr
td(off)
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 200 V; RD = 15 Ω;
RG = 5.6 Ω
-
16
40
100
42
-
ns
ns
ns
ns
Ld
Ld
Internal drain inductance
Internal drain inductance
-
3.5
4.5
-
nH
nH
Ls
Internal source inductance
Measured from tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
Measured from source lead to source
bond pad
-
7.5
-
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
1283
218
120
-
pF
pF
pF
2 pulse width and repetition rate limited by Tj max.
December 1998
2
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistors
Avalanche energy rated
PHP13N40E, PHB13N40E, PHW13N40E
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
IS
Tmb = 25˚C
-
-
13.7
A
Tmb = 25˚C
-
-
55
A
VSD
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
IS = 13 A; VGS = 0 V
-
-
1.2
V
trr
Qrr
Reverse recovery time
Reverse recovery charge
IS = 13 A; VGS = 0 V; dI/dt = 100 A/µs
-
420
5.4
-
ns
µC
ISM
December 1998
MIN.
3
TYP. MAX. UNIT
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistors
Avalanche energy rated
120
PHP13N40E, PHB13N40E, PHW13N40E
Normalised Power Derating
PD%
Transient Thermal Impedance, Zth j-a (K/W) PHP13N40E
110
1
100
90
D = 0.5
80
0.2
70
0.1
60
50
0.1
0.05
PD
0.02
40
0.01
D = tp/T
tp
Single pulse
30
20
10
0
0
20
40
60
80
100
Tmb / C
120
140
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
120
t
T
0.001
1E-06
1E-05
1E-04
1E-03 1E-02 1E-01
pulse width, tp (s)
1E+00 1E+01
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Normalised Current Derating
ID%
Drain Current, ID (A)
110
8
100
90
PHP13N40E
VGS = 10 V
Tj = 25 C
5V
7
80
6
70
5
60
50
4
40
3
30
2
20
10
1
4.8 V
4.6 V
4.4 V
4.2 V
4V
0
0
0
20
40
60
80
Tmb / C
100
120
0
140
1
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V
2
3
4
Drain-Source Voltage, VDS (V)
5
Fig.5. Typical output characteristics.
ID = f(VDS); parameter VGS
Drain-Source On Resistance, RDS(on) (Ohms)
100
Peak Pulsed Drain Current, IDM (A)
1.4
PHP13N40E
RDS(on) = VDS/ ID
tp = 10 us
10
1
4V
4.2V
4.4V
Tj = 25 C
4.6V
1.2
d.c.
1
100 us
0.8
1 ms
0.6
10 ms
4.8V
5V
0.4
100 ms
VGS = 10 V
0.2
PHP13N40E
0.1
0
10
100
Drain-Source Voltage, VDS (V)
1000
0
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
December 1998
1
2
3
4
5
Drain Current, ID (A)
6
7
8
Fig.6. Typical on-state resistance.
RDS(ON) = f(ID); parameter VGS
4
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistors
Avalanche energy rated
PHP13N40E, PHB13N40E, PHW13N40E
VGS(TO) / V
PHP13N40E
Drain current, ID (A)
20
max.
4
VDS > ID X RDS(ON)
18
16
14
typ.
3
12
10
min.
8
2
150 C
6
Tj = 25 C
4
1
2
0
0
1
2
3
4
5
6
7
0
-60
Gate-source voltage, VGS (V)
1E-01
PHP13N40E
Transconductance, gfs (S)
-20
0
20
40
60
Tj / C
80
100
120
140
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS
Fig.7. Typical transfer characteristics.
ID = f(VGS); parameter Tj
12
-40
SUB-THRESHOLD CONDUCTION
ID / A
Tj = 25 C
VDS > ID X RDS(ON)
10
1E-02
150 C
8
2%
1E-03
typ
98 %
6
1E-04
4
2
1E-05
0
0
5
10
15
1E-06
20
0
Drain current, ID (A)
Fig.8. Typical transconductance.
gfs = f(ID); parameter Tj
1
2
VGS / V
3
4
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Normalised RDS(ON) = f(Tj)
a
10000
2
Capacitances, Ciss, Coss, Crss (pF)
PHP13N40E
Ciss
1000
1
Coss
100
Crss
10
0
-60
-40
-20
0
20
40 60
Tj / C
80
0.1
100 120 140
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 6.5 A; VGS = 10 V
December 1998
1
10
Drain-source voltage, VDS (V)
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
5
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistors
Avalanche energy rated
PHP13N40E, PHB13N40E, PHW13N40E
Source-Drain Diode Current, IF (A)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PHP13N40E
20
PHP13N40E
Gate-source voltage, VGS (V)
18
ID = 13A
Tj = 25 C
16
14
200V
12
100 V
10
VDD=320V
150 C
8
Tj = 25 C
6
4
2
0
0
20
40
60
80
Gate charge, QG (nC)
100
0
120
100
td(off)
VDD = 200V
RD = 15 Ohms
0.6
0.8
1
1.2
Fig.16. Source-Drain diode characteristic.
IF = f(VSDS); parameter Tj
PHP13N40E
Switching times, td(on), tr, td(off), tf (ns)
400
0.4
Drain-Source Voltage, VSDS (V)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); parameter VDS
450
0.2
Non-repetitive Avalanche current, IAS (A)
PHP13N40E
350
Tj prior to avalanche = 25 C
300
250
10
200
tf
150
VDS
100
125 C
tp
tr
ID
td(on)
50
1
1E-06
0
0
10
20
30
Gate resistance, RG (Ohms)
40
50
1E-04
1E-03
1E-02
Avalanche time, tp (s)
Fig.14. Typical switching times; td(on), tr, td(off), tf = f(RG)
1.15
1E-05
Fig.17. Maximum permissible non-repetitive
avalanche current (IAS) versus avalanche time (tp);
unclamped inductive load
Normalised Drain-source breakdown voltage
V(BR)DSS @ Tj
V(BR)DSS @ 25 C
100
1.1
Maximum Repetitive Avalanche Current, IAR (A)
Tj prior to avalanche = 25 C
1.05
10
125 C
1
1
0.95
0.9
0.85
-100
PHP13N40E
0.1
1E-06
-50
0
50
Tj, Junction temperature (C)
100
150
1E-04
1E-03
1E-02
Avalanche time, tp (s)
Fig.15. Normalised drain-source breakdown voltage;
V(BR)DSS/V(BR)DSS 25 ˚C = f(Tj)
December 1998
1E-05
Fig.18. Maximum permissible repetitive avalanche
current (IAR) versus avalanche time (tp)
6
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistors
Avalanche energy rated
PHP13N40E, PHB13N40E, PHW13N40E
MECHANICAL DATA
Dimensions in mm
4,5
max
Net Mass: 2 g
10,3
max
1,3
3,7
2,8
5,9
min
15,8
max
3,0 max
not tinned
3,0
13,5
min
1,3
max 1 2 3
(2x)
0,9 max (3x)
2,54 2,54
0,6
2,4
Fig.19. SOT78 (TO220AB); pin 2 connected to mounting base.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for SOT78 (TO220) envelopes.
3. Epoxy meets UL94 V0 at 1/8".
December 1998
7
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistors
Avalanche energy rated
PHP13N40E, PHB13N40E, PHW13N40E
MECHANICAL DATA
Dimensions in mm
4.5 max
1.4 max
10.3 max
Net Mass: 1.4 g
11 max
15.4
2.5
0.85 max
(x2)
0.5
2.54 (x2)
Fig.20. SOT404 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
11.5
9.0
17.5
2.0
3.8
5.08
Fig.21. SOT404 : soldering pattern for surface mounting.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Epoxy meets UL94 V0 at 1/8".
December 1998
8
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistors
Avalanche energy rated
PHP13N40E, PHB13N40E, PHW13N40E
MECHANICAL DATA
Dimensions in mm
5.3 max
16 max
1.8
Net Mass: 5 g
5.3
o 3.5
max
7.3
3.5
21
max
15.5
max
seating
plane
2.5
15.5
min
4.0
max
1
2
3
0.9 max
2.2 max
1.1
3.2 max
5.45
0.4 M
5.45
Fig.22. SOT429; pin 2 connected to mounting base.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for SOT429 envelope.
3. Epoxy meets UL94 V0 at 1/8".
December 1998
9
Rev 1.000
Philips Semiconductors
Product specification
PowerMOS transistors
Avalanche energy rated
PHP13N40E, PHB13N40E, PHW13N40E
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1998
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
December 1998
10
Rev 1.000