Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated IRFP460 FEATURES SYMBOL • Repetitive Avalanche Rated • Fast switching • Stable off-state characteristics • High thermal cycling performance • Low thermal resistance QUICK REFERENCE DATA d VDSS = 500 V ID = 20 A g RDS(ON) ≤ 0.27 Ω s GENERAL DESCRIPTION PINNING N-channel, enhancement mode field-effect power transistor, intended for use in off-line switched mode power supplies, T.V. and computer monitor power supplies, d.c. to d.c. converters, motor control circuits and general purpose switching applications. PIN SOT429 (TO247) DESCRIPTION 1 gate 2 drain 3 source tab drain 1 The IRFP460 is supplied in the SOT429 (TO247) conventional leaded package. 2 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDSS VDGR VGS ID Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Tj = 25 ˚C to 150˚C Tj = 25 ˚C to 150˚C; RGS = 20 kΩ IDM PD Tj, Tstg Pulsed drain current Total dissipation Operating junction and storage temperature range - 55 500 500 ± 30 20 12.4 80 250 150 V V V A A A W ˚C MIN. MAX. UNIT - 1300 mJ - 32 mJ - 20 A Tmb = 25 ˚C; VGS = 10 V Tmb = 100 ˚C; VGS = 10 V Tmb = 25 ˚C Tmb = 25 ˚C AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS EAR IAS, IAR CONDITIONS Non-repetitive avalanche energy Unclamped inductive load, IAS = 20 A; tp = 0.2 ms; Tj prior to avalanche = 25˚C; VDD ≤ 50 V; RGS = 50 Ω; VGS = 10 V Repetitive avalanche energy1 IAR = 20 A; tp = 2.5 µs; Tj prior to avalanche = 25˚C; RGS = 50 Ω; VGS = 10 V Repetitive and non-repetitive avalanche current 1 pulse width and repetition rate limited by Tj max. September 1999 1 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated IRFP460 THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. SOT429 package, in free air TYP. MAX. UNIT - - 0.5 K/W - 45 - K/W ELECTRICAL CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. Drain-source breakdown voltage ∆V(BR)DSS / Drain-source breakdown ∆Tj voltage temperature coefficient RDS(ON) Drain-source on resistance VGS(TO) Gate threshold voltage gfs Forward transconductance IDSS Drain-source leakage current VGS = 0 V; ID = 0.25 mA 500 - - V VDS = VGS; ID = 0.25 mA - 0.1 - %/K 2.0 13 - 0.2 3.0 18 2 100 10 0.27 4.0 50 1000 200 Ω V S µA µA nA V(BR)DSS TYP. MAX. UNIT IGSS VGS = 10 V; ID = 10 A VDS = VGS; ID = 0.25 mA VDS = 30 V; ID = 10 A VDS = 500 V; VGS = 0 V VDS = 400 V; VGS = 0 V; Tj = 125 ˚C Gate-source leakage current VGS = ±30 V; VDS = 0 V Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 20 A; VDD = 400 V; VGS = 10 V - 147 12 78 190 18 100 nC nC nC td(on) tr td(off) tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 250 V; RD = 12 Ω; RG = 3.9 Ω - 23 72 150 75 - ns ns ns ns Ld Ld Ls Internal drain inductance Internal drain inductance Internal source inductance Measured from tab to centre of die Measured from drain lead to centre of die Measured from source lead to source bond pad - 3.5 4.5 7.5 - nH nH nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 3000 480 270 - pF pF pF SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS IS Tmb = 25˚C - - 20 A Tmb = 25˚C - - 80 A VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage IS = 20 A; VGS = 0 V - - 1.5 V trr Qrr Reverse recovery time Reverse recovery charge IS = 20 A; VGS = 0 V; dI/dt = 100 A/µs - 900 15 - ns µC ISM September 1999 MIN. 2 TYP. MAX. UNIT Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated 120 IRFP460 Normalised Power Derating PD% 110 D = 0.5 0.2 80 0.1 70 0.1 0.05 60 50 P D 0.02 30 D = tp/T tp 0.01 40 single pulse 20 10 T 0.001 1E-06 0 0 20 40 60 80 100 Tmb / C 120 1E-05 1E-04 140 1E-03 1E-02 1E-01 1E+00 1E+01 Pulse width, tp (s) Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) 120 PHW20N50E Zth j-mb (K/W) 1 100 90 Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Normalised Current Derating ID% Drain Current, ID (A) 110 20 100 90 PHW20N50E Tj = 25 C 18 VGS = 10 V 8V 16 80 14 70 60 50 12 5V 10 4.8 V 8 40 4.6 V 6 30 20 10 4 4.4 V 4.2 V 2 4V 0 0 0 20 40 60 80 Tmb / C 100 120 0 140 1 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V 2 3 4 Drain-Source Voltage, VDS (V) 5 Fig.5. Typical output characteristics. ID = f(VDS); parameter VGS Drain-Source On Resistance, RDS(on) (Ohms) PHW20N50E 100 Peak Pulsed Drain Current, IDM (A) 0.5 PHW20N50E tp = 10 us 10 RDS(on) = VDS/ ID d.c. 1 4V 4.2V 4.6 V 4.8V 4.4 V 0.45 100us 0.4 1 ms 0.35 10 ms 100 ms Tj = 25 C 5V 0.3 VGS = 6 V 10V 0.25 0.1 0.2 10 100 Drain-Source Voltage, VDS (V) 1000 0 Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp September 1999 2 4 6 8 10 12 Drain Current, ID (A) 14 16 18 20 Fig.6. Typical on-state resistance. RDS(ON) = f(ID); parameter VGS 3 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated IRFP460 VGS(TO) / V Drain current, ID (A) PHW20N50E 30 max. 4 VDS > ID X RDS(ON) 25 typ. 3 20 15 min. 150 C 2 Tj = 25 C 10 5 1 0 0 1 2 3 4 5 6 7 8 0 -60 Gate-source voltage, VGS (V) 1E-01 PHW20N50E Transconductance, gfs (S) -20 0 20 40 60 Tj / C 80 100 120 140 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS Fig.7. Typical transfer characteristics. ID = f(VGS); parameter Tj 20 -40 SUB-THRESHOLD CONDUCTION ID / A VDS > ID X RDS(ON) 18 Tj = 25 C 16 1E-02 150 C 14 2% 1E-03 12 typ 98 % 10 8 1E-04 6 4 1E-05 2 0 0 5 10 15 20 25 30 1E-06 0 Drain current, ID (A) Fig.8. Typical transconductance. gfs = f(ID); parameter Tj 1 2 VGS / V 3 4 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Normalised RDS(ON) = f(Tj) a Capacitances, Ciss, Coss, Crss (pF) PHW20N50E 10000 2 Ciss 1000 1 Coss Crss 100 0 -60 -40 -20 0 20 40 60 Tj / C 80 0.1 100 120 140 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 10 A; VGS = 10 V September 1999 1 10 Drain-Source Voltage, VDS (V) 100 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 4 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated IRFP460 Source-Drain Diode Current, IF (A) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VGS = 0 V 45 ID = 20A Tj = 25 C PHW20N50E 50 PHW20N50E Gate-source voltage, VGS (V) 40 300V 35 30 200V 25 VDD = 400 V 150 C Tj = 25 C 20 15 10 5 0 0 25 50 75 100 125 Gate charge, QG (nC) 150 175 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 200 Drain-Source Voltage, VSDS (V) Fig.16. Source-Drain diode characteristic. IF = f(VSDS); parameter Tj Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS Switching times, td(on), tr, td(off), tf (ns) PHW20N50E 600 100 Non-repetitive Avalanche current, IAS (A) td(off) 500 Tj prior to avalanche = 25 C 400 300 10 tr, tf 200 125 C VDS tp td(on) 100 ID 0 0 5 10 15 20 25 1 1E-06 30 PHW20N50E 1E-05 Gate resistance, RG (Ohms) Fig.14. Typical switching times; td(on), tr, td(off), tf = f(RG) 1.15 1E-04 1E-03 1E-02 Avalanche time, tp (s) Fig.17. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tp); unclamped inductive load Normalised Drain-source breakdown voltage V(BR)DSS @ Tj Maximum Repetitive Avalanche Current, IAR (A) V(BR)DSS @ 25 C 100 1.1 1.05 Tj prior to avalanche = 25 C 10 125 C 1 1 0.95 0.9 0.85 -100 PHW20N50E 0.1 1E-06 -50 0 50 Tj, Junction temperature (C) 100 150 1E-04 1E-03 1E-02 Avalanche time, tp (s) Fig.15. Normalised drain-source breakdown voltage; V(BR)DSS/V(BR)DSS 25 ˚C = f(Tj) September 1999 1E-05 Fig.18. Maximum permissible repetitive avalanche current (IAR) versus avalanche time (tp) 5 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated IRFP460 MECHANICAL DATA Plastic single-ended through-hole package; heatsink mounted; 1 mounting hole; 3-lead TO-247 SOT429 α E P A A1 β q S R D Y L1(1) Q b2 L 1 2 3 c w M b b1 e e 0 10 20 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b b1 b2 c D E mm 5.3 4.7 1.9 1.7 1.2 0.9 2.2 1.8 3.2 2.8 0.9 0.6 21 20 16 15 e L 5.45 16 15 (1) L1 4.0 3.6 P Q 3.7 3.3 2.6 2.4 q R S 5.3 3.5 3.3 7.5 7.1 w Y α β 0.4 15.7 15.3 6° 4° 17° 13° Note 1. Tinning of terminals are uncontrolled within zone L1. OUTLINE VERSION SOT429 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 98-04-07 99-08-04 TO-247 Fig.19. SOT429; pin 2 connected to mounting base Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT429 envelope. 3. Epoxy meets UL94 V0 at 1/8". September 1999 6 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated IRFP460 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. September 1999 7 Rev 1.000