0 QPRO XQ4000XL Series QML High-Reliability FPGAs R DS029 (v1.3) June 25, 2000 0 2 XQ4000X Series Features • • • • • • • Certified to MIL-PRF-38535 Appendix A QML (Qualified Manufacturer Listing) Ceramic and plastic packages Also available under the following standard microcircuit drawings (SMD) - XQ4013XL 5962-98513 - XQ4036XL 5962-98510 - XQ4062XL 5962-98511 - XQ4085XL 5962-99575 For more information contact the Defense Supply Center Columbus (DSCC) http://www.dscc.dla.mis/v/va/smd/smdsrch.html Available in -3 speed System featured Field-Programmable Gate Arrays - SelectRAM™ memory: on-chip ultra-fast RAM with · synchronous write option · dual-port RAM option - Abundant flip-flops - Flexible function generators - Dedicated high-speed carry logic - Wide edge decoders on each edge - Hierarchy of interconnect lines - Internal 3-state bus capability - Eight global low-skew clock or signal distribution networks • • • • • • • • • • • • • Development system runs on most common computer platforms - Interfaces to popular design environments - Fully automatic mapping, placement and routing - Interactive design editor for design optimization Highest capacity—over 180,000 usable gates Additional routing over XQ4000E - Almost twice the routing capacity for high-density designs Buffered Interconnect for maximum speed New latch capability in configurable logic blocks Improved VersaRing™ I/O interconnect for better Fixed pinout flexibility - Virtually unlimited number of clock signals Optional multiplexer or 2-input function generator on device outputs 5V tolerant I/Os 0.35 µm SRAM process Introduction The QPRO™ XQ4000XL Series high-performance, high-capacity Field Programmable Gate Arrays (FPGAs) provide the benefits of custom CMOS VLSI, while avoiding the initial cost, long development cycle, and inherent risk of a conventional masked gate array. The result of thirteen years of FPGA design experience and feedback from thousands of customers, these FPGAs combine architectural versatility, on-chip Select-RAM memory with edge-triggered and dual-port modes, increased speed, abundant routing resources, and new, sophisticated soft-ware to achieve fully automated implementation of complex, high-density, high-performance designs. System performance beyond 50 MHz Flexible array architecture Low power segmented routing architecture Systems-oriented features - IEEE 1149.1-compatible boundary scan logic support • Product Specification - Individually programmable output slew rate - Programmable input pull-up or pull-down resistors - 12 mA sink current per XQ4000XL output Configured by loading binary file - Unlimited reprogrammability Readback capability - Program verification - Internal node observability Refer to the complete Commercial XC4000XL Series Field Programmable Gate Arrays Data Sheet for more information on device architecture and timing, and the latest Xilinx databook for package pinouts other than the CB228 (included in this data sheet). (Pinouts for XQ4000XL device are identical to XC4000XL.) © 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS029 (v1.3) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 1 R QPRO XQ4000XL Series QML High-Reliability FPGAs Table 1: XQ4000XL Series High Reliability Field Progammable Gate Arrays Device Logic Cells Max Logic Gates (No RAM)(1) Max. RAM Bits (No Logic) Typical Gate Range (Logic and RAM)(1) CLB Matrix Total CLBs Number of Flip-Flops Max. User I/O XQ4013XL 2432 13,000 18,432 10,000-30,000 24x24 576 1,536 192 PG223, CB228, PQ240, BG256 XQ4036XL 3078 36,000 41,472 22,000-65,000 36x36 1,296 3,168 288 PG411, CB228, HQ240, BG352 XQ4062XL 5472 62,000 73,728 40,000-130,000 48x48 2,304 5,376 384 PG475, CB228, HQ240, BG432 XQ4085XL 7448 85,000 100,352 55,000-180,000 56x56 3,136 7,168 448 PG475, CB228, HQ240, BG432 Packages Notes: 1. Maximum values of typical gate range includes 20% to 30% of CLBs used as RAM. 2 www.xilinx.com 1-800-255-7778 DS029 (v1.3) June 25, 2000 Product Specification R QPRO XQ4000XL Series QML High-Reliability FPGAs XQ4000XL Switching Characteristics Definition of Terms In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or devicefamilies. Values are subject to change. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final. Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction temperature conditions. All specifications subject to change without notice. Additional Specifications Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters included are common to popular designs and typical appli- cations. For design considerations requiring more detailed timing information, see the appropriate family AC supplements available on the Xilinx web site at: http://www.xilinx.com/partinfo/databook.htm. Absolute Maximum Ratings(1) Symbol Description Units VCC Supply voltage relative to GND –0.5 to 4.0 V VIN GND(2) –0.5 to 5.5 V –0.5 to 5.5 V 50 ms –65 to +150 °C Input voltage relative to output(2) VTS Voltage applied to High-Z VCCt Longest supply voltage rise time from 1V to 3V TSTG Storage temperature (ambient) TSOL Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 °C Junction temperature Ceramic package +150 °C Plastic package +125 °C TJ Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 2. Maximum DC overshoot or undershoot above VCC or below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to –2.0 V or overshoot to VCC + 2.0V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. Recommended Operating Conditions(1) Symbol VCC Description Min Max Units Supply voltage relative to GND, TJ = –55°C to +125°C Plastic 3.0 3.6 V Supply voltage relative to GND, TC = –55°C to +125°C Ceramic 3.0 3.6 V 50% of VCC 5.5 V voltage(2) VIH High-level input VIL Low-level input voltage 0 30% of VCC V TIN Input signal transition time - 250 ns Notes: 1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per °C. 2. Input and output measurement threshold is ~50% of VCC. DS029 (v1.3) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 3 R QPRO XQ4000XL Series QML High-Reliability FPGAs XQ4000XL DC Characteristics Over Recommended Operating Conditions Symbol VOH Description Min Max Units 2.4 - V 90% VCC - - V 0.4 V V 2.5 10% VCC - V - 5 mA –10 +10 µA BGA, PQ, HQ, packages - 10 pF PGA packages - 16 pF High-level output voltage at IOH = –4 mA, VCC min (LVTTL) High-level output voltage at IOH = –500 µA, (LVCMOS) VOL VDR ICCO IL (LVTTL)(1) Low-level output voltage at IOL = 12 mA, VCC min Low-level output voltage at IOL = 1500 µA, (LVCMOS) - Data retention supply voltage (below which configuration data may be lost) Quiescent FPGA supply current(2) Input or output leakage current CIN Input capacitance (sample tested) IRPU Pad pull-up (when selected) at VIN = 0V (sample tested) 0.02 0.25 mA IRPD Pad pull-down (when selected) at VIN = 3.6V (sample tested) Horizontal longline pull-up (when selected) at logic Low 0.02 0.15 mA 0.3 2.0 mA IRLL Notes: 1. With up to 64 pins simultaneously sinking 12 mA. 2. With no output current loads, no active input or Longline pull-up resistors, all I/O pins in a High-Z state and floating. Power-On Power Supply Requirements Xilinx FPGAs require a minimum rated power supply current capacity to insure proper initialization, and the power supply ramp-up time does affect the current required. A fast ramp-up time requires more current than a slow ramp-up time. The slowest ramp-up time is 50 ms. Current capacity is not specified for a ramp-up time faster than 2 ms. The cur- rent capacity varies linealy with ramp-up time, e.g., an XQ4036XL with a ramp-up time of 25 ms would require a capacity predicted by the point on the straight line drawn from 1A at 120 µs to 500 mA at 50 ms at the 25 ms time mark. This point is approximately 750 mA . Ramp-up Time Product Description Fast (120 µs) Slow (50 ms) XQ4013 - 36XL Minimum required current supply 1A 500 mA XC4062XL Minimum required current supply 2A 500 mA Minimum required current supply 2A(1) 500 mA XC4085XL(1) Notes: 1. The XC4085XL fast ramp-up time is 5 ms. 2. Devices are guaranteed to initialize properly with the minimum current listed above. A larger capacity power supply may result in a larger initialization current. 3. This specification applies to Commercial and Industrial grade products only. 4. Ramp-up Time is measured from 0VDC to 3.6VDC. Peak current required lasts less than 3 ms, and occurs near the internal power on reset threshold voltage. After initialization and before configuration, ICC max is less than 10 mA. 4 www.xilinx.com 1-800-255-7778 DS029 (v1.3) June 25, 2000 Product Specification R QPRO XQ4000XL Series QML High-Reliability FPGAs XQ4000XL AC Switching Characteristic Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature) Global Buffer Switching Characteristics Symbol TGLS Description Delay from pad through Global Low Skew buffer, to any clock K -3 -1 Device All Min Max Max Units XQ4013XL 0.6 3.6 - ns XQ4036XL 1.1 4.8 - ns XQ4062XL 1.4 6.3 - ns XQ4085XL 1.6 - 5.7 ns Global Early BUFGEs 1, 2, 5, and 6 to IOB Clock Characteristics Symbol TGE Description Delay from pad through Global Early buffer, to any IOB clock. Values are for BUFGEs 1, 2, 5 and 6. -3 -1 Device All Min Max Max Units XQ4013XL 0.4 2.4 - ns XQ4036XL 0.3 3.1 - ns XQ4062XL 0.3 4.9 - ns XQ4085XL 0.4 - 4.7 ns Global Early BUFGEs 3, 4, 7, and 8 to IOB Clock Characteristics Symbol TGE Description Delay from pad through Global Early buffer, to any IOB clock. Values are for BUFGEs 3, 4, 7 and 8. DS029 (v1.3) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 -3 -1 Device All Min Max Max Units XQ4013XL 0.7 2.4 - ns XQ4036XL 0.9 4.7 - ns XQ4062XL 1.2 5.9 - ns XQ4085XL 1.3 - 5.5 ns 5 R QPRO XQ4000XL Series QML High-Reliability FPGAs XQ4000XL CLB Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000XL devices and expressed in nanoseconds unless otherwise noted. CLB Switching Characteristics -3 Symbol Description -1 Min Max Min Max Units Combinatorial Delays TILO F/G inputs to X/Y outputs - 1.6 - 1.3 ns TIHO F/G inputs via H’ to X/Y outputs - 2.7 - 2.2 ns TITO F/G inputs via transparent latch to Q outputs - 2.9 - 2.2 ns THH0O C inputs via SR/H0 via H to X/Y outputs - 2.5 - 2.0 ns THH1O C inputs via H1 via H to X/Y outputs - 2.4 - 1.9 ns THH2O C inputs via DIN/H2 via H to X/Y outputs - 2.5 - 2.0 ns TCBYP C inputs via EC, DIN/H2 to YQ, XQ output (bypass) - 1.5 - 1.1 ns CLB Fast Carry Logic TOPCY Operand inputs (F1, F2, G1, G4) to C OUT - 2.7 - 2.0 ns TASCY Add/subtract input (F3) to COUT - 3.3 - 2.5 ns TINCY Initialization inputs (F1, F3) to COUT - 2.0 - 1.5 ns TSUM CIN through function generators to X/Y outputs - 2.8 - 2.4 ns TBYP CIN to COUT, bypass function generators - 0.26 - 0.20 ns TNET Carry net delay, C OUT to C IN - 0.32 - 0.25 ns Sequential Delays TCKO Clock K to flip-flop outputs Q - 2.1 - 1.6 ns TCKLO Clock K to latch outputs Q - 2.1 - 1.6 ns Setup Time Before Clock K 6 TICK F/G inputs 1.1 - 0.9 - ns TIHCK F/G inputs via H 2.2 - 1.7 - ns THH0CK C inputs via H0 through H 2.0 - 1.6 - ns THH1CK C inputs via H1 through H 1.9 - 1.4 - ns THH2CK C inputs via H2 through H 2.0 - 1.6 - ns TDICK C inputs via DIN 0.9 - 0.7 - ns TECCK C inputs via EC 1.0 - 0.8 - ns TRCK C inputs via S/R, going Low (inactive) 0.6 - 0.5 - ns TCCK CIN input via F/G 2.3 - 1.9 - ns TCHCK CIN input via F/G and H 3.4 - 2.7 - ns www.xilinx.com 1-800-255-7778 DS029 (v1.3) June 25, 2000 Product Specification R QPRO XQ4000XL Series QML High-Reliability FPGAs CLB Switching Characteristics (Continued) -3 Symbol Description -1 Min Max Min Max Units Hold Time After Clock K TCKI F/G inputs 0 - 0 - ns TCKIH F/G inputs via H 0 - 0 - ns TCKHH0 C inputs via SR/H0 through H 0 - 0 - ns TCKHH1 C inputs via H1 through H 0 - 0 - ns TCKHH2 C inputs via DIN/H2 through H 0 - 0 - ns TCKDI C inputs via DIN/H2 0 - 0 - ns TCKEC C inputs via EC 0 - 0 - ns TCKR C inputs via SR, going Low (inactive) 0 - 0 - ns Clock TCH Clock High time 3.0 - 2.5 - ns TCL Clock Low time 3.0 - 2.5 - ns 3.0 - 2.5 - ns - 3.7 - 2.8 ns - 19.8 - 15.0 ns Set/Reset Direct TRPW Width (High) Delay from C inputs via S/R, going High to Q TRIO Global Set/Reset TMRW Minimum GSR pulse width TMRQ Delay from GSR input to any Q FTOG Toggle frequency (MHz) (for export control) DS029 (v1.3) June 25, 2000 Product Specification See page 17 for TRRI values per device. www.xilinx.com 1-800-255-7778 - 166 - 200 MHz 7 R QPRO XQ4000XL Series QML High-Reliability FPGAs XQ4000XL RAM Synchronous (Edge-Triggered) Write Operation Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XQ4000XL devices and are expressed in nanoseconds unless otherwise noted. Single-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics -3 Symbol Single Port RAM -1 Size Min Max Min Max Units 16x2 9.0 - 7.7 - ns 32x1 9.0 - 7.7 - ns 16x2 4.5 - 3.9 - ns 32x1 4.5 - 3.9 - ns 16x2 2.2 - 1.7 - ns 32x1 2.2 - 1.7 - ns 16x2 0 - 0 - ns 32x1 0 - 0 - ns 16x2 2.0 - 1.7 - ns 32x1 2.5 - 2.1 - ns 16x2 0 - 0 - ns 32x1 0 - 0 - ns 16x2 2.0 - 1.6 - ns 32x1 1.8 - 1.5 - ns 16x2 0 - 0 - ns 32x1 0 - 0 - ns 16x2 - 6.8 - 5.8 ns 32x1 - 8.1 - 6.9 ns 16x2 4.5 - 2.6 - ns 32x1 6.5 - 3.8 - ns 16x2 - 1.6 - 1.3 ns 32x1 - 2.7 - 2.2 ns 16x2 1.1 - 0.9 - ns 32x1 2.2 - 1.7 - ns Write Operation TWCS Address write cycle time (clock K period) TWCTS TWPS Clock K pulse width (active edge) TWPTS TASS Address setup time before clock K TASTS TAHS Address hold time after clock K TAHTS TDSS DIN setup time before clock K TDSTS TDHS DIN hold time after clock K TDHTS TWSS WE setup time before clock K TWSTS TWHS WE hold time after clock K TWHTS TWOS Data valid after clock K TWOTS Read Operation TRC Address read cycle time TRCT TILO Data valid after address change (no Write Enable) TIHO TICK Address setup time before clock K TIHCK 8 www.xilinx.com 1-800-255-7778 DS029 (v1.3) June 25, 2000 Product Specification R QPRO XQ4000XL Series QML High-Reliability FPGAs Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics -3 Symbol Dual Port RAM Size(1) Min -1 Max Min Max Units Write Operation TWCDS Address write cycle time (clock K period) 16x1 9.0 TWPDS Clock K pulse width (active edge) 16x1 4.5 - 3.9 - ns TASDS Address setup time before clock K 16x1 2.5 - 1.7 - ns TAHDS Address hold time after clock K 16x1 0 - 0 - ns TDSDS DIN setup time before clock K 16x1 2.5 - 2.0 - ns TDHDS DIN hold time after clock K 16x1 0 - 0 - ns TWSDS WE setup time before clock K 16x1 1.8 - 1.6 - ns TWHDS WE hold time after clock K 16x1 0 - 0 - ns TWODS Data valid after clock K 16x1 - 7.8 - 6.7 ns DS029 (v1.3) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 7.7 ns 9 R QPRO XQ4000XL Series QML High-Reliability FPGAs XQ4000XL CLB Single-Port RAM Synchronous (Edge-Triggered) Write Timing TWPS WCLK (K) TWSS TWHS TDSS TDHS TASS TAHS WE DATA IN ADDRESS TILO TILO TWOS DATA OUT OLD NEW DS029_01_011300 XQ4000XL CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing TWPDS WCLK (K) TWHS TWSS WE TDSDS TDHDS TASDS TAHDS DATA IN ADDRESS TILO DATA OUT TILO TWODS OLD NEW DS029_02_011300 10 www.xilinx.com 1-800-255-7778 DS029 (v1.3) June 25, 2000 Product Specification R QPRO XQ4000XL Series QML High-Reliability FPGAs XQ4000XL Pin-to-Pin Output Parameter Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted. Output Flip-Flop, Clock to Out(1,2,3) Symbol TICKOF TSLOW Description Global low skew clock to output using OFF(4) For output SLOW option add -3 -1 Device All Min Max Max Units XQ4013XL 1.5 8.6 - ns XQ4036XL 2.0 9.8 - ns XQ4062XL 2.3 11.3 - ns XQ4085XL 2.5 - 9.5 ns All Devices 3.0 3.0 3.0 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for FAST mode configurations. 3. Output timing is measured at ~50% V CC threshold with 50 pF external capacitive load. 4. OFF = Output Flip-Flop Output Flip-Flop, Clock to Out, BUFGEs 1, 2, 5, and 6 -3 -1 Device All Min Max Max Units Global early clock to output using OFF XQ4013XL 1.3 7.4 - ns Values are for BUFGEs 1, 2, 5, and 6. XQ4036XL 1.2 8.1 - ns XQ4062XL 1.2 9.9 - ns XQ4085XL 1.3 - 8.5 ns Symbol TICKEOF Description Notes: 1. Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for FAST mode configurations. 2. Output timing is measured at ~50% V CC threshold with 50 pF external capacitive load. DS029 (v1.3) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 11 R QPRO XQ4000XL Series QML High-Reliability FPGAs Output Flip-Flop, Clock to Out, BUFGEs 3, 4, 7, and 8 -3 -1 Device All Min Max Max Units Global early clock to output using OFF XQ4013XL 1.8 8.8 - ns Values are for BUFGEs 3, 4, 7, and 8. XQ4036XL 1.8 9.7 - ns XQ4062XL 2.0 10.9 - ns XQ4085XL 2.2 - 9.3 ns Symbol TICKEOF Description Notes: 1. Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for FAST mode configurations. 2. Output timing is measured at ~50% V CC threshold with 50 pF external capacitive load. Capacitive Load Factor Figure 1 is usable over the specified operating conditions of voltage and temperature and is independent of the output slew rate control. 3 2 Delta Delay (ns) Figure 1 shows the relationship between I/O output delay and load capacitance. It allows a user to adjust the specified output delay if the load capacitance is different than 50 pF. For example, if the actual load capacitance is 120 pF, add 2.5 ns to the specified delay. If the load capacitance is 20 pF, subtract 0.8 ns from the specified output delay. 1 0 -1 -2 0 20 40 60 80 100 120 140 Capacitance (pF) DS029_03_011300 Figure 1: Delay Factor at Various Capacitive Loads 12 www.xilinx.com 1-800-255-7778 DS029 (v1.3) June 25, 2000 Product Specification R QPRO XQ4000XL Series QML High-Reliability FPGAs XQ4000XL Pin-to-Pin Input Parameter Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted. Global Low Skew Clock, Input Setup and Hold Times(1,2) Symbol Description -3 -1 Device(1) Min Min Units XQ4013XL 1.2 / 3.2 - ns XQ4036XL 1.2 / 5.5 - ns XQ4062XL 1.2 / 7.0 - ns XQ4085XL - 0.9 / 7.1 ns XQ4013XL 6.1 / 0.0 - ns XQ4036XL 6.4 / 1.0 - ns XQ4062XL 6.7 / 1.2 - ns XQ4085XL - 9.8 / 1.2 ns XQ4013XL 6.4 / 0.0 - ns XQ4036XL 6.6 / 0.0 - ns XQ4062XL 6.8 / 0.0 - ns XQ4085XL - 9.6 / 0.0 ns No Delay TPSN/TPHN Global early clock and IFF(3) Global early clock and FCL(4) Partial Delay TPSP/TPHP Global early clock and IFF(3) Global early clock and FCL(4) Full Delay TPSD/TPHD Global early clock and IFF(3) Notes: 1. The XQ4013XL, XQ4036XL, and XQ4062XL have significantly faster partial and full delay setup times than other devices. 2. Input setup time is measured with the fastest route and the lightest load. Input hold time is measured using the furthest distance and a reference load of one clock pin per IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin no-delay input hold specification. 3. IFF = Input Flip-Flop or Latch 4. FCL = Fast Capture Latch DS029 (v1.3) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 13 R QPRO XQ4000XL Series QML High-Reliability FPGAs Global Early Clock BUFEs 1, 2, 5, and 6 Setup and Hold for IFF and FCL(1,2) Symbol Description -3 -1 Device Min Min XQ4013XL 1.2 / 4.7 - XQ4036XL 1.2 / 6.7 - XQ4062XL 1.2 / 8.4 - XQ4085XL - 0.9 / 6.6 XQ4013XL 6.4 / 0.0 - XQ4036XL 7.0 / 0.8 - XQ4062XL 9.0 / 0.8 - XQ4085XL - 11.0 / 0.0 XQ4013XL 12.0 / 0.0 - XQ4036XL 13.8 / 0.0 - XQ4062XL 13.1 / 0.0 - XQ4085XL - 13.6 / 0.0 No Delay TPSEN/TPHEN TPFSEN/TPFHEN Global early clock and IFF(3) Global early clock and FCL(4) Partial Delay TPSEPN/TPHEP TPFSEP/TPFHEP Global early clock and IFF(3) Global early clock and FCL(4) Full Delay TPSEPD/TPHED Global early clock and IFF(3) Notes: 1. The XQ4013XL, XQ4036XL, and XQ4062XL have significantly faster partial and full delay setup times than other devices. 2. Input setup time is measured with the fastest route and the lightest load. Input hold time is measured using the furthest distance and a reference load of one clock pin per IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin no-delay input hold specification. 3. IFF = Input Flip-Flop or Latch 4. FCL = Fast Capture Latch 14 www.xilinx.com 1-800-255-7778 DS029 (v1.3) June 25, 2000 Product Specification R QPRO XQ4000XL Series QML High-Reliability FPGAs Global Early Clock BUFEs 3, 4, 7, and 8 Setup and Hold for IFF and FCL(1,2) Symbol Description -3 -1 Device Min Min XQ4013XL 1.2 / 4.7 - XQ4036XL 1.2 / 6.7 - XQ4062XL 1.2 / 8.4 - XQ4085XL - 0.9 / 6.6 XQ4013XL 5.4 / 0.0 - XQ4036XL 6.4 / 0.8 - XQ4062XL 8.4 / 1.5 - XQ4085XL - 11.0 / 0.0 XQ4013XL 10.0 / 0.0 - XQ4036XL 12.2 / 0.0 - XQ4062XL 13.1 / 0.0 - XQ4085XL - 13.6 / 0.0 No Delay TPSEN/TPHEN TPFSEN/TPFHEN Global early clock and IFF(3) Global early clock and FCL(4) Partial Delay TPSEPN/TPHEP TPFSEP/TPFHEP Global early clock and IFF(3) Global early clock and FCL(4) Full Delay TPSEPD/TPHED Global early clock and IFF(3) Notes: 1. The XQ4013XL, XQ4036XL, and XQ4062XL have significantly faster partial and full delay setup times than other devices. 2. Input setup time is measured with the fastest route and the lightest load. Input hold time is measured using the furthest distance and a reference load of one clock pin per IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin no-delay input hold specification. 3. IFF = Input Flip-Flop or Latch 4. FCL = Fast Capture Latch DS029 (v1.3) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 15 R QPRO XQ4000XL Series QML High-Reliability FPGAs XQ4000XL IOB Input Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). -3 Symbol Description -1 Device Min Max Min Max Units Clocks TECIK Clock enable (EC) to clock (IK) All devices 0.1 - 0.1 - ns TOKIK Delay from FCL enable (OK) active edge to IFF clock (IK) active edge All devices 2.2 - 1.6 - ns Setup Times TPICK Pad to clock (IK), no delay All devices 1.7 - 1.3 - ns TPICKF Pad to clock (IK), via transparent fast capture latch, no delay All devices 2.3 - 1.8 - ns TPOCK Pad to fast capture latch enable (OK), no delay All devices 1.2 - 0.9 - ns All devices 0 - 0 - ns Hold Times All Hold Times Global Set/Reset TMRW Minimum GSR pulse width All devices - 19.8 - 15.0 ns TRRI Delay from GSR input to any Q(2) XQ4013XL - 15.9 - - ns XQ4036XL - 22.5 - - ns XQ4062XL - 29.1 - - ns XQ4085XL - - - 26.0 ns Propagation Delays TPID Pad to I1, I2 All devices - 1.6 - 1.7 ns TPLI Pad to I1, I2 via transparent input latch, no delay All devices - 3.1 - 2.4 ns TPFLI Pad to I1, I2 via transparent FCL and input latch, no delay All devices - 3.7 - 2.8 ns TIKRI Clock (IK) to I1, I2 (flip-flop) All devices - 1.7 - 1.3 ns TIKLI Clock (IK) to I1, I2 (latch enable, active Low) All devices - 1.8 - 1.4 ns TOKLI FCL enable (OK) active edge to I1, I2 (via transparent standard input latch) All devices - 3.6 - 2.7 ns Notes: 1. IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch 2. Indicates Minimum Amount of Time to Assure Valid Data. 16 www.xilinx.com 1-800-255-7778 DS029 (v1.3) June 25, 2000 Product Specification R QPRO XQ4000XL Series QML High-Reliability FPGAs XQ4000XL IOB Output Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Develop- ment System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless otherwise noted. Values are expressed in nanoseconds unless otherwise noted. -3 Symbol Description -1 Min Max Min Max Units Clocks TCH Clock High 3.0 - 2.5 - ns TCL Clock Low 3.0 - 2.5 - ns Propagation Delays TOKPOF Clock (OK) to pad - 5.0 - 3.8 ns TOPF Output (O) to pad - 4.1 - 3.1 ns TTSHZ High-Z to pad High-Z (slew-rate independent) - 4.4 - 3.0 ns TTSONF High-Z to pad active and valid - 4.1 - 3.3 ns TOFPF Output (O) to pad via fast output MUX - 5.5 - 4.2 ns TOKFPF Select (OK) to pad via fast MUX - 5.1 - 3.9 ns Setup and Hold Times TOOK Output (O) to clock (OK) setup time 0.5 - 0.3 - ns TOKO Output (O) to clock (OK) hold time 0 - 0 - ns TECOK Clock Enable (EC) to clock (OK) setup time 0 - 0 - ns TOKEC Clock Enable (EC) to clock (OK) hold time 0.3 - 0.1 - ns 19.8 - 15.0 - ns XQ4013XL - 20.5 - - ns XQ4036XL - 27.1 - - ns XQ4062XL - 33.7 - - ns XQ4085XL - - 29.5 ns - 2.0 ns Global Set/Reset TMRW TRPO Minimum GSR pulse width Delay from GSR input to any pad(2) Slew Rate Adjustment TSLOW For output SLOW option add - 3.0 Notes: 1. Output timing is measured at ~50% V CC threshold, with 50 pF external capacitive loads. 2. Indicates Minimum Amount of Time to Assure Valid Data. DS029 (v1.3) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 17 R QPRO XQ4000XL Series QML High-Reliability FPGAs CB228 Pinouts Table 2: CB228 Package Pinouts (Continued) Pin Name Table 2: CB228 Package Pinouts Pin Name CB228 VTT GND P1 BUFGP_TL_A16_GCK1_IO P2 A17_IO P3 IO P4 IO P5 TDI_IO P6 TCK_IO P7 IO P8 IO P9 IO P10 IO P11 IO P12 IO P13 GND P14 IO_FCLK1 P15 IO P16 TMS_IO P17 IO P18 IO P19 IO P20 IO P21 IO P22 IO P23 IO P24 IO P25 IO P26 GND P27 VCC P28 IO P29 IO P30 IO P31 IO P32 IO P33 IO P34 IO P35 IO P36 VCC P37 IO P38 18 CB228 IO P39 IO P40 IO_FCLK2 P41 GND P42 IO P43 IO P44 IO P45 IO P46 IO P47 IO P48 IO P49 IO P50 IO P51 IO P52 IO P53 BUFGS_BL_GCK2_IO P54 M1 P55 GND P56 M0 P57 VCC P58 M2 P59 BUFGP_BL_GCK3_IO P60 HDC_IO P61 IO P62 IO P63 IO P64 LDC_IO P65 IO P66 IO P67 IO P68 IO P69 IO P70 IO P71 GND P72 IO P73 IO P74 IO P75 IO P76 IO P77 IO P78 www.xilinx.com 1-800-255-7778 DS029 (v1.3) June 25, 2000 Product Specification R QPRO XQ4000XL Series QML High-Reliability FPGAs Table 2: CB228 Package Pinouts (Continued) Pin Name Table 2: CB228 Package Pinouts (Continued) Pin Name CB228 CB228 IO P79 IO P119 IO P80 IO P120 IO P81 IO P121 IO P82 IO P122 IO P83 D6_IO P123 /ERR_INIT_IO P84 IO P124 VCC P85 IO P125 GND P86 IO P126 IO P87 IO P127 IO P88 IO P128 IO P89 GND P129 IO P90 IO P130 IO P91 IO P131 IO P92 IO_FCLK3 P132 IO P93 IO P133 IO P94 D5_IO P134 VCC P95 /CS0_IO P135 IO P96 IO P136 IO P97 IO P137 IO P98 IO P138 IO P99 IO P139 GND P100 D4_IO P140 IO P101 IO P141 IO P102 VCC P142 IO P103 GND P143 IO P104 D3_IO P144 IO P105 /RS_IO P145 IO P106 IO P146 IO P107 IO P147 IO P108 IO P148 IO P109 IO P149 IO P110 D2_IO P150 IO P111 IO P151 BUFGS_BR_GCK4_IO P112 VCC P152 GND P113 IO P153 DONE P114 IO_FCLK4 P154 VCC P115 IO P155 /PROGRAM P116 IO P156 D7_IO P117 GND P157 BUFGP_BR_GCK5_IO P118 IO P158 DS029 (v1.3) June 25, 2000 Product Specification www.xilinx.com 1-800-255-7778 19 R QPRO XQ4000XL Series QML High-Reliability FPGAs Table 2: CB228 Package Pinouts (Continued) Pin Name Table 2: CB228 Package Pinouts (Continued) CB228 Pin Name CB228 IO P159 A7_IO P199 IO P160 GND P200 IO P161 VCC P201 IO P162 A8_IO P202 IO P163 A9_IO P203 D1_IO P164 A19_IO P204 BUSY_/RDY_RCLK_IO P165 A18_IO P205 IO P166 IO P206 IO P167 IO P207 D0_DIN_IO P168 A10_IO P208 BUFGS_TR_GCK6_DOUT_IO P169 A11_IO P209 CCLK P170 VCC P210 VCC P171 IO P211 TDO P172 IO P212 GND P173 IO P213 A0_/WS_IO P174 IO P214 BUFGP_TR_GCK7_A1_IO P175 GND P215 IO P176 IO P216 IO P177 IO P217 CSI_A2_IO P178 IO P218 A3_IO P179 IO P219 IO P180 A12_IO P220 IO P181 A13_IO P221 IO P182 IO P222 IO P183 IO P223 IO P184 IO P224 IO P185 IO P225 GND P186 A14_IO P226 IO P187 BUFGS_TL_GCK8_A15_IO P227 IO P188 VCC P228 IO P189 IO P190 VCC P191 A4_IO P192 A5_IO P193 IO P194 IO P195 A21_IO P196 A20_IO P197 A6_IO P198 20 www.xilinx.com 1-800-255-7778 DS029 (v1.3) June 25, 2000 Product Specification R QPRO XQ4000XL Series QML High-Reliability FPGAs Ordering Information Example for QPRO™ military temperature part: XQ 4062XL -3 PG 475 M Mil-PRF-38535 (QML) Processed Temperature Range M = Military Ceramic (TC = –55oC to +125 oC) N = Military Plastic (TJ = –55°C to +125°C) Device Type XQ4085XL XQ4062XL XQ4036XL XQ4013XL Number of Pins Speed Grade Package Type CB = Top Brazed Ceramic Quad Flat Pack PG = Ceramic Pin Grid Array PQ/HQ = Plastic Quad Flat Back BG = Plastic Ball Grid Array -3 -1 (XQ4085XL only) Example for SMD part: 5962 98511 01 Q X C Generic Standard Microcircuit Drawing (SMD) Prefix Lead Finish C = Gold B = Solder Device Type XQ4013XL = 98513 XQ4036XL = 98510 XQ4062XL = 98511 XQ4085XL = 99575 Package Type X = Pin Grid Y = Ceramic Quad Flat Pack (Base Mark) Z = Ceramic Quad Flat Pack (Lid Mark) T = Plastic Quad Flat Pack U = Plastic Ball Grid Speed Grade 01 = -3 for XQ4103XL/4036XL/4062XL 01 = -1 for XQ4085XL Q = QML Certified N = QML Plastic (N - Grade) Revision History The following table shows the revision history for this document Date Version 05/01/98 1.0 Original document release. 01/01/99 1.1 Addition of new packages, clarification of parameters. 02/09/00 1.2 Addition of XQ4085XL-1 speed grade part. 06/25/00 1.3 Updated timing specifications to match with commercial data sheet. Updated format. DS029 (v1.3) June 25, 2000 Product Specification Description www.xilinx.com 1-800-255-7778 21 QPRO XQ4000XL Series QML High-Reliability FPGAs 22 www.xilinx.com 1-800-255-7778 R DS029 (v1.3) June 25, 2000 Product Specification