ONSEMI 74HC541

MC74HC541A
Octal 3-State Non-Inverting
Buffer/Line Driver/
Line Receiver
High–Performance Silicon–Gate CMOS
The MC74HC541A is identical in pinout to the LS541. The device
inputs are compatible with Standard CMOS outputs. External pullup
resistors make them compatible with LSTTL outputs.
The HC541A is an octal non–inverting buffer/line driver/line
receiver designed to be used with 3–state memory address drivers,
clock drivers, and other bus–oriented systems. This device features
inputs and outputs on opposite sides of the package and two ANDed
active–low output enables.
The HC541A is similar in function to the HC540A, which has
inverting outputs.
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MARKING
DIAGRAMS
20
PDIP–20
N SUFFIX
CASE 738
20
1
20
1
SOIC WIDE–20
DW SUFFIX
CASE 751D
20
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2 to 6V
Low Input Current: 1µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 134 FETs or 33.5 Equivalent Gates
1
A
WL
YY
WW
A2
A3
Data
Inputs
A4
A5
A6
A7
A8
Output
Enables
OE1
OE2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
1
Y1
Y2
Y3
Y4
Non–Inverting
Outputs
FUNCTION TABLE
Output Y
OE1
OE2
A
L
L
H
X
L
L
X
H
L
H
X
X
L
H
Z
Z
Z = High Impedance
X = Don’t Care
Y5
Y6
ORDERING INFORMATION
Y7
Device
MC74HC541AN
Y8
PIN 20 = VCC
PIN 10 = GND
19
= Assembly Location
= Wafer Lot
= Year
= Work Week
Inputs
2
HC541A
AWLYYWW
1
LOGIC DIAGRAM
A1
MC74HC541AN
AWLYYWW
Package
Shipping
PDIP–20
1440 / Box
MC74HC541ADW
SOIC–WIDE
38 / Rail
MC74HC541ADWR2
SOIC–WIDE
1000 / Reel
Pinout: 20–Lead Packages (Top View)
VCC
20
OE2
19
Y1
18
Y2
17
Y3
16
Y4
15
Y5
14
Y6
13
Y7
12
Y8
11
1
2
3
4
5
6
7
8
9
10
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
 Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 2
1
Publication Order Number:
MC74HC541A/D
MC74HC541A
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MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 35
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air,
750
500
mW
Tstg
Storage Temperature Range
– 65 to + 150
_C
Iin
TL
Plastic DIP†
SOIC Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP or SOIC Package
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Min
Max
Unit
2.0
6.0
V
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature Range, All Package Types
tr, tf
Input Rise/Fall Time
(Figure 1)
0
VCC
V
– 55
+ 125
_C
0
0
0
1000
500
400
ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Condition
Guaranteed Limit
VCC
V
–55 to 25°C
≤85°C
≤125°C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1V
|Iout| ≤ 20µA
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
VIL
Maximum Low–Level Input
Voltage
Vout = VCC – 0.1V
|Iout| ≤ 20µA
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
Minimum High–Level Output
Voltage
Vin = VIL
|Iout| ≤ 20µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
6.0
±0.1
±1.0
±1.0
VOH
|Iout| ≤ 3.6mA
|Iout| ≤ 6.0mA
|Iout| ≤ 7.8mA
Vin = VIL
VOL
Maximum Low–Level Output
Voltage
Vin = VIH
|Iout| ≤ 20µA
|Iout| ≤ 3.6mA
|Iout| ≤ 6.0mA
|Iout| ≤ 7.8mA
Vin = VIH
Iin
Maximum Input Leakage Current
Vin = VCC or GND
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2
V
µA
MC74HC541A
DC CHARACTERISTICS (Voltages Referenced to GND)
Parameter
Symbol
Condition
Guaranteed Limit
VCC
V
–55 to 25°C
≤85°C
≤125°C
Unit
IOZ
Maximum Three–State Leakage
Current
Output in High Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
±0.5
±5.0
±10.0
µA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0µA
6.0
4
40
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
Guaranteed Limit
VCC
V
–55 to 25°C
≤85°C
≤125°C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
2.0
3.0
4.5
6.0
80
30
18
15
100
40
23
20
120
55
28
25
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
110
45
25
21
140
60
31
26
165
75
38
31
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
2.0
3.0
4.5
6.0
110
45
25
21
140
60
31
26
165
75
38
31
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
2.0
3.0
4.5
6.0
60
22
12
10
75
28
15
13
90
34
18
15
ns
Maximum Input Capacitance
10
10
10
pF
Maximum Three–State Output Capacitance (Output in High
Impedance State)
15
15
15
pF
Cin
Cout
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD
Power Dissipation Capacitance (Per Buffer)*
pF
35
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
SWITCHING WAVEFORMS
VCC
tf
tr
VCC
90%
INPUT A
OE1 or OE2
50%
50%
GND
50%
tPZL tPLZ
10%
tPLH
tPHL
OUTPUT Y
50%
90%
10%
VOL
90%
VOH
tPZH tPHZ
50%
OUTPUT Y
HIGH
IMPEDANCE
GND
10%
OUTPUT Y
tTHL
tTLH
50%
HIGH
IMPEDANCE
Figure 1.
Figure 2.
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3
MC74HC541A
TEST CIRCUITS
TEST
POINT
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ and tPZH.
1kΩ
OUTPUT
CL*
*Includes all probe and jig capacitance
Figure 3.
Figure 4.
PIN DESCRIPTIONS
INPUTS
outputs are enabled and the device functions as an
non–inverting buffer. When a high voltage is applied to
either input, the outputs assume the high impedance state.
A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8,
9) — Data input pins. Data on these pins appear in
non–inverted form on the corresponding Y outputs, when
the outputs are enabled.
OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
13, 12, 11) — Device outputs. Depending upon the state of
the output enable pins, these outputs are either
non–inverting outputs or high–impedance outputs.
CONTROLS
OE1, OE2 (PINS 1, 19) — Output enables (active–low).
When a low voltage is applied to both of these pins, the
LOGIC DETAIL
To 7 Other
Buffers
VCC
One of Eight
Buffers
INPUT A
OUTPUT Y
OE1
OE2
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MC74HC541A
PACKAGE DIMENSIONS
PDIP–20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738–03
ISSUE E
–A–
20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
–T–
K
SEATING
PLANE
M
N
E
G
F
J
D
20 PL
0.25 (0.010)
20 PL
0.25 (0.010)
M
T A
M
T B
M
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01
SO–20
DW SUFFIX
CASE 751D–05
ISSUE F
q
A
20
X 45 _
M
E
h
0.25
1
10
20X
B
B
0.25
M
T A
S
B
S
A
L
H
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
11
B
M
D
18X
e
A1
SEATING
PLANE
DIM
A
A1
B
C
D
E
e
H
h
L
q
C
T
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MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
MC74HC541A
Notes
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MC74HC541A
Notes
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MC74HC541A
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are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
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MC74HC541A/D