ONSEMI 74HC373DTR2G

74HC373
Octal 3−State Non−Inverting
Transparent Latch
High−Performance Silicon−Gate CMOS
The 74HC373 is identical in pinout to the LS373. The device inputs
are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the
high−impedance state. Thus, data may be latched even when the
outputs are not enabled.
The HC373A is identical in function to the HC573A which has the
data inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
The HC373A is the non−inverting version of the HC533A.
Features
•
•
•
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the JEDEC Standard No. 7.0 A Requirements
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 186 FETs or 46.5 Equivalent Gates
This is a Pb−Free Device
© Semiconductor Components Industries, LLC, 2007
March, 2007 − Rev. 0
1
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MARKING
DIAGRAM
20
HC
373
ALYW G
G
TSSOP−20
DT SUFFIX
CASE 948E
20
1
1
HC373
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
Publication Order Number:
74HC373/D
74HC373
PIN ASSIGNMENT
LOGIC DIAGRAM
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
LATCH ENABLE
OUTPUT ENABLE
3
2
4
5
7
6
8
9
13
12
14
15
17
16
18
19
11
1
1
20
VCC
Q0
OUTPUT
ENABLE
Q0
2
19
Q7
Q1
D0
3
18
D7
Q2
D1
4
17
D6
Q1
5
16
Q6
Q2
6
15
Q5
D2
7
14
D5
D3
8
13
D4
Q3
9
12
Q4
10
11
LATCH
ENABLE
Q3
NONINVERTING
OUTPUTS
Q4
Q5
Q6
Q7
GND
PIN 20 = VCC
PIN 10 = GND
FUNCTION TABLE
Inputs
Output
Enable
Latch
Enable
L
H
L
H
L
L
H
X
X = Don’t Care
Z = High Impedance
Design Criteria
Value
Units
Internal Gate Count*
46.5
ea
Internal Gate Propagation Delay
1.5
ns
5.0
mW
0.0075
pJ
Internal Gate Power Dissipation
Speed Power Product
*Equivalent to a two−input NAND gate.
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2
Output
D
Q
H
L
X
X
H
L
No Change
Z
74HC373
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
– 0.5 to + 7.0
V
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Output Voltage (Referenced to GND)
VCC
DC Supply Voltage (Referenced to GND)
Vin
Vout
– 0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
±20
mA
Iout
DC Output Current, per Pin
±35
mA
ICC
DC Supply Current, VCC and GND Pins
±75
mA
450
mW
– 65 to + 150
_C
PD
Power Dissipation in Still Air,
Tstg
Storage Temperature
TSSOP Package†
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(TSSOP Package)
_C
260
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
†Derating — TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Min
Max
Unit
2.0
6.0
V
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
0
VCC
V
– 55
+ 125
_C
0
0
0
1000
500
400
ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
ORDERING INFORMATION
Package
Shipping †
TSSOP−20*
2500 Units / Reel
Device
74HC373DTR2G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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3
74HC373
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
VIH
Parameter
Minimum High−Level Input
Voltage
Test Conditions
Vout = VCC – 0.1 V
|Iout| v 20 mA
VIL
Maximum Low−Level Input
Voltage
Vout = 0.1 V
|Iout| v 20 mA
VOH
Minimum High−Level Output
Voltage
Vin = VIH
|Iout| v 20 mA
Vin = VIH
VOL
Maximum Low−Level Output
Voltage
Vin = VIL
|Iout| v 20 mA
Vin = VIL
Iin
IOZ
Maximum Input Leakage Current
Maximum Three−State
Leakage Current
|Iout| v 2.4 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
|Iout| v 2.4 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
Vin = VCC or GND
Output in High−Impedance State
Vin = VIL or VIH
Vout = VCC or GND
ICC
VCC
(V)
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
6.0
6.0
– 55 to 25_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
±0.1
±0.5
v 85_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
±1.0
±5.0
v 125_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.2
3.7
5.2
0.1
0.1
0.1
0.4
0.4
0.4
±1.0
±10
Unit
V
V
V
V
mA
mA
Maximum Quiescent Supply
Vin = VCC or GND
6.0
4.0
40
40
mA
Current (per Package)
Iout = 0 mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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4
74HC373
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
tPLH
tPHL
VCC
(V)
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
Parameter
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
tPLH
tPHL
Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
tPLZ
tPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
tPZL
tPZH
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
tTLH
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
Cin
Cout
Guaranteed Limit
– 55 to 25_C
125
80
25
21
140
90
28
24
150
100
30
26
150
100
30
26
60
23
12
10
10
15
v 85_C
155
110
31
26
175
120
35
30
190
125
38
33
190
125
38
33
75
27
15
13
10
15
v 125_C
190
130
38
32
210
140
42
36
225
150
45
38
225
150
45
38
90
32
18
15
10
15
Unit
ns
ns
ns
ns
ns
Maximum Input Capacitance
pF
Maximum Three−State Output Capacitance
pF
(Output in High−Impedance State)
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
36
CPD
Power Dissipation Capacitance (Per Enabled Output)*
pF
* Used to determine the no−load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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5
74HC373
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
Figure
VCC
(V)
– 55 to 25_C
Min
v 85_C
Max
Min
v 125_C
Max
Min
Max
Unit
tsu
Minimum Setup Time, Input D to Latch Enable
4
2.0
3.0
4.5
6.0
25
20
5.0
5.0
30
25
6.0
6.0
40
30
8.0
7.0
ns
th
Minimum Hold Time, Latch Enable to Input D
4
2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
50
5.0
5.0
5.0
5.0
5.0
ns
tw
Minimum Pulse Width, Latch Enable
2
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
ns
tr, tf
Maximum Input Rise and Fall Times
1
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
SWITCHING WAVEFORMS
tr
tf
INPUT D
tPLH
tPHL
90%
50%
10%
Q
tw
VCC
90%
50%
10%
LATCH ENABLE
GND
GND
Q
50%
Figure 1.
OUTPUT
ENABLE
VCC
GND
tPLZ
50%
tPZH
Q
Figure 2.
50%
tPZL
Q
tPHL
tPLH
tTHL
tTLH
VCC
50%
HIGH
IMPEDANCE
10%
VOL
90%
VOH
tPHZ
1.3 V
VALID
INPUT D
tsu
LATCH ENABLE
Figure 4.
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6
th
50%
HIGH
IMPEDANCE
Figure 3.
VCC
50%
GND
VCC
GND
74HC373
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
C L*
C L*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 5.
D0
3
Figure 6.
D1
4
D
Q
D2
7
D
LE
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
1 kW
OUTPUT
Q
D3
8
D
LE
Q
D4
13
D
LE
Q
D5
14
D
LE
Q
D6
17
D
LE
Q
D7
18
D
LE
Q
D
LE
Q
LE
11
1
2
Q0
5
Q1
6
Q2
9
Q3
12
Q4
Figure 7. EXPANDED LOGIC DIAGRAM
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7
15
Q5
16
Q6
19
Q7
74HC373
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
20X
0.15 (0.006) T U
2X
L
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
K
K1
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
S
J J1
11
B
−U−
PIN 1
IDENT
SECTION N−N
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
PLANE
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
−−− 0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
74HC373
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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For additional information, please contact your local
Sales Representative
74HC373/D