FAIRCHILD ACE12022EN

ACE1202 Product Family
Arithmetic Controller Engine (ACEx™)
for Low Power Applications
■ Hardware Bit - Coder (HBC) (ACE1202-2 only)
General Description
■ On-chip oscillator
— No external components
— 1µs instruction cycle time
The ACE1202 (Arithmetic Controller Engine) family of
microcontrollers is a dedicated programmable monolithic integrated circuit for applications requiring high performance, low
power, and small size. It is a fully static part fabricated using
CMOS technology.
■ On-chip Power-on Reset
■ Programmable read and write disable functions
■ Memory mapped I/O
The ACE1202 product family has an 8-bit microcontroller core, 64
bytes of RAM, 64 bytes of data EEPROM and 2K bytes of code
EEPROM. Its on-chip peripherals include a multi-function 16-bit
timer, watchdog/idle timer, and programmable undervoltage detection circuitry. The on-chip clock and reset functions reduce the
number of required external components. The ACE1202 product
family is available in 8- and 14-pin SOIC and DIP packages.
■ Multilevel Low Voltage Detection
■ Brown-out Reset
■ Software selectable I/O option
— Push-pull outputs with tri-state option
— Weak pull-up or high impedance
■ Fully static CMOS
— Low power HALT mode (100nA @ 3.3V)
— Power saving IDLE mode
Features
■ Arithmetic Controller Engine
■ Single supply operation
— 1.8-5.5V (P.N. ACE1202L)
— 2.2-5.5V (P.N. ACE1202, ACE12022)
— 2.7-5.5V (P.N. ACE1202B, ACE12022B)
■ 2K bytes on-board code EEPROM
■ 64 bytes data EEPROM
■ 64 bytes RAM
■ Instruction set geared for block encryption
■ 40 years data retention
■ Watchdog
■ 1,000,000 data changes
■ Multi-input wake-up on all I/O pins
■ 16-bit multifunction timer with difference capture
■ 8 and 14-pin SOIC, 8 and 14-pin DIP packages. (CSP
package available upon request)
■ 12-bit idle timer
■ In-circuit programming
Block and Connection Diagram
VCC1
GND1
RESET2
Power-on Reset
(CKO) G0
Internal Oscillator
(CKI) G1
(T1/TX3)
GPORT
ACE1202 core
(Input only) G3
general
purpose
I/O with
multiinput
wakeup
(4 interrupt
sources
and vectors)
(TX3) G5
HALT & IDLE Power
Saving Modes
12-bit Timer0 with
Watchdog Timer
G2
G4
Brown-out Reset/Low
Battery Detect
16-bit Multi-function
Timer1 with Difference
Capture
Hardware Bit-Coder3
G62
Programming Interface
64 bytes of RAM
G72
2K bytes of Code
EEPROM
64 bytes of Data
EEPROM
1. 100nf Decoupling capacitor recommended
2. Available only in the 14-pin package option
3. Available only on the ACE1202-2 device
© 2001 Fairchild Semiconductor Corporation
ACE1202 Product Family Rev. B.1
1
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ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
PRELIMINARY
August 2001
VCC
Optional
LED
G4
VCC
G0
G1
G3
RF Interface
G5
GND
RF Stage
G2
Figure 3: ACE1202/ACE1202-2 8-pin Device Pinout
a) Normal Mode Operation
b) Programming Mode Operation
G3
1
8
VCC
LOAD
1
8
VCC
G4
2
7
GND
SFT_IN
2
7
GND
G5
G0
3
6
6
5
NC/VCC
NC
3
4
G2
G1
4
5
SFT_OUT
CKI
Figure 4: ACE1202/ACE1202-2 14-pin Device Pinout
a) Normal Mode Operation
b) Programming Mode Operation
G3
1
14
VCC
LOAD
1
14
VCC
G4
2
13
GND
13
3
12
3
12
GND
NC
4
11
NC
G2
SFT_IN
NC
2
NC
G6
NC
4
11
SFT_OUT
G7
G5
5
10
NC
10
NC
9
NC
NC/VCC
5
6
6
9
G0
7
8
NC
7
8
RESET
G1
2
ACE1202 Product Family Rev. B.1
RESET
CKI
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ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 2: ACEx Application Example (Remote Keyless Entry)
Operating Conditions
Ambient Storage Temperature
-65°C to +150°C
Relative Humidity (non-condensing)
Input Voltage not including G3
-0.3V to VCC+0.3V
G3 Input Voltage
EEPROM write limits
0.3V to 13V
Lead Temperature (10s max)
Electrostatic Discharge on all pins
95%
See DC Electrical
Characteristics
+300°C
2000V min
Part Number Operating Voltage Ambient Operating Temperature
ACE1202
2.2 to 5.5V
0°C to 70°C
ACE12022
2.2 to 5.5V
0°C to 70°C
ACE1202E
2.2 to 5.5V
-40°C to +85°C
ACE12022E
2.2 to 5.5V
-40°C to +85°C
ACE1202V
2.2 to 5.5V
-40°C to +125°C
ACE1202B
2.7 to 5.5V
0°C to 70°C
ACE12022B
2.7 to 5.5V
0°C to 70°C
ACE1202BE
2.7 to 5.5V
-40°C to +85°C
ACE12022BE
2.7 to 5.5V
-40°C to +85°C
ACE1202BV
2.7 to 5.5V
-40°C to +125°C
ACE12022BV
2.7 to 5.5V
-40°C to +125°C
ACE1202L
1.8 to 5.5V
0°C to 70°C
3
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ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
2.0 Electrical Characteristics
Absolute Maximum Ratings
VCC = 1.8/2.2/2.7 to 5.5V
All measurements valid for ambient operating temperature range unless otherwise stated.
Symbol
ICC
4
Parameter
Conditions
MIN
TYP
MAX
Units
0.2
0.4
0.7
1.2
3.7
0.5
1.0
1.2
2.0
5.5
mA
mA
mA
mA
mA
Supply Current –
no data EEPROM write in
progress
1.8V
2.2V
2.7V
3.3V
5.5V
ICCH
HALT Mode current
3.3V @ -40°C to +25°C
5.5V @ -40°C to +25°C
3.3V @ +85°C
5.5V @ +85°C
3.3V @ +125°C
5.5V @+125°C
10
60
75
400
600
1550
100
1000
1000
2500
5000
8000
nA
nA
nA
nA
nA
nA
ICCL5
IDLE Mode Current
3.3V
5.5V
150
200
200
300
µA
µA
VCCW
EEPROM Write Voltage
Code EEPROM in
Programming Mode
4.5
5.0
5.5
V
Data EEPROM in
Operating Mode
2.4
5.5
V
1µs/V
10ms/V
SVCC
Power Supply Slope
VIL
Input Low with Schmitt
Trigger Buffer
VCC = 1.8 -5.5V
VIH
Input High with Schmitt
Trigger Buffer
VCC = 1.8 - 5.5V
IIP
Input Pull-up Current
VCC =5.5V, VIN =0V
ITL
TRI-STATE Leakage
VCC =5.5V
VOL
Output Low Voltage
VCC = 1.8 - 2.2V
G0, G1, G2, G4, G6, G7
VOH
0.2VCC
0.8VCC
V
V
65
350
µA
2
200
nA
0.8 mA sink
0.2VCC
V
G5
1.0 mA sink
0.2VCC
V
Output Low Voltage
VCC = 2.2V – 3.3V
G0, G1, G2, G4, G6, G7
3.0 mA sink
0.2VCC
V
G5
5.0 mA sink
0.2VCC
V
Output Low Voltage
VCC = 3.3V – 5.5V
G0, G1, G2, G4, G6, G7
5.0 mA sink
0.2VCC
V
G5
10.0 mA sink
0.2VCC
V
Output High Voltage
VCC = 1.8 - 2.2V
G0, G1, G2, G4, G6, G7
0.1 mA source
0.8VCC
V
G5
0.2 mA source
0.8VCC
V
Output High Voltage
VCC = 3.3V – 5.5V
G0, G1, G2, G4, G6, G7
0.4 mA source
0.8VCC
V
G5
0.8 mA source
0.8VCC
V
Output High Voltage
VCC = 3.3V – 5.5V
G0, G1, G2, G4, G6, G7
0.4 mA source
0.8VCC
V
G5
1.0 mA source
0.8VCC
V
4
ICC active current is dependent on the program code.
5
Based on a continuous IDLE looping program.
4
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ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Preliminary ACE1202/ACE1202-2 DC Electrical Characteristics
All measurements valid for ambient operating temperature range unless otherwise stated.
Parameter
Conditions
MIN
TYP
MAX
Units
0.9
1.0
1.1
µs
Instruction cycle time from
internal clock - setpoint
5.0V at +25°C
Internal clock voltage dependent
frequency variation
3.0V to 5.5V,
constant temperature
+5
%
Internal clock temperature
dependent frequency variation
3.0V to 5.5V,
full temperature range
+10
%
Internal clock frequency
deviation for 0.5V drop
3.0V to 4.5V,
constant temperature
+2
%
Crystal oscillator frequency
(Note 6)
4
MHz
External clock frequency
(Note 7)
4
MHz
EEPROM write time
10
ms
Internal clock start up time
(Note 7)
3
2
ms
Oscillator start up time
(Note 7)
2400
cycles
6
The maximum permissible frequency is guaranteed by design but not 100% tested.
7
The parameter is guaranteed by design but not 100% tested.
Preliminary ACE1202/ACE1202-2 Electrical Characteristics for programming
All data following is valid between 4.5V and 5.5V at ambient temperature. The following characteristics are guaranteed by design but are not 100% tested. See "EEPROM write time" in the AC
Electrical Characteristics for definition of the programming ready time.
Parameter
Description
MIN
MAX
Units
tHI
CLOCK high time
500
DC
ns
tLO
CLOCK low time
500
DC
ns
tDIS
SHIFT_IN setup time
100
ns
tDIH
SHIFT_IN hold time
100
ns
tDOS
SHIFT_OUT setup time
100
ns
tDOH
SHIFT_OUT hold time
900
ns
tSV1, tSV2
LOAD supervoltage timing
50
µs
tLOAD1, tLOAD2, tLOAD3, tLOAD4
LOAD timing
5
µs
VSUPERVOLTAGE
Supervoltage level
11.5
5
ACE1202 Product Family Rev. B.1
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ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Preliminary ACE1202/ACE1202-2 AC Electrical Characteristics
VCC = 1.8/2.2/2.7 to 5.5V
VCC = 2.2/1.8 to 5.5V
The following characteristics are guaranteed by design but are not 100% tested.
Parameter
LBD Voltage Threshold
Conditions
MIN
TYP
MAX
Units
Level 1 @ -40°C
2.84
V
Level 8 @ -40°C
2.02
V
Level 1 @ 0°C
2.98
V
Level 8 @ 0°C
2.05
V
Level 1 @ -25°C
3.08
V
Level 8 @ +25°C
2.12
V
Level 1 @ +85°C
3.31
V
Level 8 @ +85°C
2.27
V
Level 1 @ +125°C
3.36
V
Level 8 @ +125°C
2.40
V
Preliminary ACE1202/ACE1202-2 Brown-out Reset (BOR) Characteristics
VCC = 2.2 to 5.5V
The following characteristics are guaranteed by design but are not 100% tested.
Parameter
BOR Trigger Threshold
Conditions
MIN
TYP
MAX
Units
-40°C
1.98
V
0°C
2.06
V
+25°C
2.12
V
+85°C
2.27
V
+125°C
2.37
V
Preliminary ACE1202L Brown-out Reset (BOR) Characteristics
VCC = 1.8 to 5.5V
The following characteristics are guaranteed by design but are not 100% tested.
Parameter
BOR Trigger Threshold
Conditions
MIN
MAX
Units
0°C
1.78
V
+25°C
1.82
V
+70°C
1.96
V
6
ACE1202 Product Family Rev. B.1
TYP
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ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Preliminary ACE1202/ACE1202-2 Low Battery Detect (LBD) Characteristics
Frequency (MHz)
Figure 5: RC Oscillator Frequency vs. Temperature (VCC=5.0V)
2.600
2.400
2.200
2.000
1.800
1.600
1.400
1.200
1.000
Avg
Min
Max
3.3k/82pF
5.6k/100pF
6.8K/100pF
Resistor & Capacitor Values [k & pF]
Figure 6: RC Oscillator Frequency vs. Temperature(VCC=2.5V)
Frequency (MHz)
1.600
1.400
Avg
Min
Max
1.200
1.000
0.800
0.600
3.3k/82pF
5.6k/100pF
6.8K/100pF
Resistor & Capacitor Values [k & pF]
Frequency (MHz)
Figure 7: Internal Oscillator Frequency
Temperature [°C]
7
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ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
3.0 AC & DC Electrical Characteristic Graphs
ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 8: Power Supply Rise Time
VCC
VBATT
1V
tS min
tS actual
Name
tS max
Parameter
time
Unit
VCC
Supply Voltage
[V]
VBATT
Battery Voltage (Nominal Operating Voltage)
[V]
tS min
Minimum Time for VCC to Rise by 1V
[ms]
tS actual
Actual Time for VCC to Rise by 1V
[ms]
tS max
Maximum Time for VCC to Rise by 1V
[ms]
SVCC
Power Supply Slope
[ms/V]
8
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ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 9: ICC Active
Icc Active (mA)
ICC Active (no data EEPROM writes) vs. Temperature
Temperature [°C]
Icc Active (mA)
ICC Active (data EEPROM writes) vs. Temperature
Temperature [°C]
9
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ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 10: HALT Mode Currents
Icc HALT (nA)
HALT current vs. Temperature
Temperature [°C]
10
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ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 11: IDLE Mode Currents
Icc IDLE (µA)
IDLE current vs. Temperature
Temperature [°C]
11
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segment of the memory map. This modification improves the
overall code efficiency of the ACEx microcontroller and takes
advantage of the flexibility found on Von Neumann style machines.
The ACEx microcontroller core is specifically designed for low
cost applications involving bit manipulation, shifting and block
encryption.It is based on a modified Harvard architecture meaning
peripheral, I/O, and RAM locations are addressed separately from
instruction data.
4.1 CPU Registers
The ACEx microcontroller has five general-purpose registers.
These registers are the Accumulator (A), X-Pointer (X), Program
Counter (PC), Stack Pointer (SP), and Status Register (SR). The
X, SP, and SR registers are all memory-mapped.
The core differs from the traditional Harvard architecture by
aligning the data and instruction memory sequentially. This allows
the X-pointer (12-bits) to point to any memory location in either
Figure 12: Programming Model
7
A
0
8-bit accumulator register
X
11
0
12-bit X pointer register
PC
10
0
11-bit program counter
0
4-bit stack pointer
SP
SR
3
8-bit status register
R 0 0GZCHN
NEGATIVE flag
HALF CARRY flag (from bit 3)
CARRY flag (from MSB)
ZERO flag
GLOBAL Interrupt Mask
READY flag (from EEPROM)
12
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ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
4.0 Arithmetic Controller Core
from the stack and loads it into the program counter. Execution
then continues at the recovered return address.
The Accumulator is a general-purpose 8-bit register that is used to
hold data and results of arithmetic calculations or data manipulations.
4.1.5 Status Register (SR)
The 8-bit Status register (SR) contains four condition code indicators
(C, H, Z, and N), one interrupt masking bit (G), and an EEPROM write
flag (R). The condition codes are automatically updated by most
instructions. (See Table 10)
4.1.2 X-Pointer (X)
The X-Pointer register allows for a 12-bit indexing value to be added
to an 8-bit offset creating an effective address used for reading and
writing between the entire memory space. (Software can only read
from code EEPROM.) This provides software with the flexibility of
storing lookup tables in the code EEPROM memory space for the
core’s accessibility during normal operation.
Carry/Borrow (C)
The carry flag is set if the arithmetic logic unit (ALU) performs a carry
or borrow during an arithmetic operation and by its dedicated
instructions. The rotate instruction operates with and through the
carry bit to facilitate multiple-word shift operations. The LDC and
INVC instructions facilitate direct bit manipulation using the carry flag.
The ACEx core allows software to access the entire 12-bit X-Pointer
register using the special X-pointer instructions (e.g. LD X, #000H). (See
Table 9) However, software may also access the register through any of
the memory-mapped instructions using the XHI (X[11:8]) and XLO
(X[7:0]) variables located at 0xBE and 0xBF, respectively. (See Table 11)
Half Carry (H)
The half carry flag indicates whether an overflow has taken place on the
boundary between the two nibbles in the accumulator. It is primarily
used for Binary Coded Decimal (BCD) arithmetic calculation.
The X register is divided into two sections. The 11 least significant
bits (LSBs) of the register is the address of the program or data
memory space. The most significant bit (MSB) of the register is
write only and selects between the data (0x000 to 0x0FF) or
program (0x800 to 0xFFF) memory space.
Zero (Z)
The zero flag is set if the result of an arithmetic, logic, or data
manipulation operation is zero. Otherwise, it is cleared.
Example: If Bit 11 = 0, then the LD A, [00,X] instruction will take a
value from address range 0x000 to 0x0FF and load it into A. If Bit
11 = 1, then the LD A, [00,X] instruction will take a value from
address range 0x800 to 0xFFF and load it into A.
Negative (N)
The negative flag is set if the MSB of the result from an arithmetic,
logic, or data manipulation operation is set to one. Otherwise, the
flag is cleared. A result is said to be negative if its MSB is a one.
The X register can also serve as a counter or temporary storage
register. However, this is true only for the 11-LSBs since the 12th
bit is dedicated for memory space selection.
Interrupt Mask (G)
4.1.3 Program Counter (PC)
The interrupt request mask (G) is a global mask that disables all
maskable interrupt sources. If the G Bit is cleared, interrupts can
become pending, but the operation of the core continues uninterrupted. However, if the G Bit is set an interrupt is recognized. After any
reset, the G bit is cleared by default and can only be set by a software
instruction. When an interrupt is recognized, the G bit is cleared after
the PC is stacked and the interrupt vector is fetched. Once the interrupt
is serviced, a return from interrupt instruction is normally executed to
restore the PC to the value that was present before the interrupt
occurred. The G bit is reset to one after a return from interrupt is
executed. Although the G bit can be set within an interrupt service
routine, “nesting” interrupts in this way should only be done when there
is a clear understanding of latency and of the arbitration mechanism.
The 10-bit program counter register contains the address of the
next instruction to be executed. After a reset, if in normal mode the
program counter is initialized to 0x800.
4.1.4 Stack Pointer (SP)
The ACEx microcontroller has an automatic program stack with a 4bit stack pointer. The stack can be initialized to any location between
addresses 0x30-0x3F. Normally, the stack pointer is initialized by one
of the first instructions in an application program. After a reset, the
stack pointer is defaulted to 0xF pointing to address 0x3F.
The stack is configured as a data structure which decrements
from high to low memory. Each time a new address is pushed
onto the stack, the core decrements the stack pointer by two.
Each time an address is pulled from the stack, the core increments the stack pointer is by two. At any given time, the stack
pointer points to the next free location in the stack.
4.2 Interrupt handling
When an interrupt is recognized, the current instruction completes its
execution. The return address (the current value in the program
counter) is pushed onto the stack and execution continues at the
address specified by the unique interrupt vector (see Table 11). This
process takes five instruction cycles. At the end of the interrupt service
routine, a return from interrupt (RETI) instruction is executed. The RETI
instruction causes the saved address to be pulled off the stack in
reverse order. The G bit is set and instruction execution resumes at the
return address.
When a subroutine is called by a jump to subroutine (JSR)
instruction, the address of the instruction is automatically pushed
onto the stack least significant byte first. When the subroutine is
finished, a return from subroutine (RET) instruction is executed.
The RET instruction pulls the previously stacked return address
Table 8: Interrupt Priority Sequence
Priority (4 highest, 1 lowest)
Interrupt
4
MIW (EDGEI)
3
Timer0 (TMRI0)
2
Timer1 (TMRI1)
1
Software (INTR)
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ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
4.1.1 Accumulator (A)
Indirect
In case of multiple interrupts occurring at the same time, the ACEx
microcontroller core has prioritized the interrupts. The interrupt
priority sequence in shown in Table 8.
This instruction has no operands associated with it.
The instruction allows the X-pointer to address any location within
the data memory space.
Direct
The instruction contains an 8-bit address field that directly points
to the data memory space as an operand.
Immediate
The instruction contains an 8-bit immediate field as an operand.
Inherent
Absolute
The instruction contains a 11-bit address that directly points to a
location in the program memory space. There are two operands
associated with this addressing mode. Each operand contains a
byte of an address. This mode is used only for the long jump (JMP)
and JSR instructions.
4.3 Addressing Modes
The ACEx microcontroller has seven addressing modes indexed,
indirect, direct, immediate, absolute jump, and relative jump.
Indexed
Relative
The instruction allows an 8-bit unsigned offset value to be added to
the 11-LSBs of the X-pointer yielding a new effective address. This
mode can be used to address either data or program memory space.
This mode is used for the short jump (JP) instructions where the
operand is a value relative to the current PC address. With this
instruction, software is limited to the number of bytes it can jump,
-31 or +32.
Interrupt Source with Priority
Figure 13: Basic Interrupt Structure
INTR
T1
T1PND
T0
T0PND
MIW
WKPND
Interrupt
Pending
Flags
Interrupt
T1EN
T0INT
EN
WKINT
EN
G
Global Interrupt
Enable
Interrupt Enable Bits
14
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ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
The ACEx microcontroller is capable of supporting four interrupts.
Three are maskable through the G bit of the SR and the fourth
(software interrupt) is not inhibited by the G bit (see Figure 13). The
software interrupt instruction is generated by the execution of the
INTR instruction. once the INTR instruction is executed, the ACEx
core will interrupt whether the G bit is set or not. The INTR interrupt
is executed in the same manner as the other maskable interrupts
where the program counter register is stacked and the G bit is
cleared. This means, if the G bit was enabled prior to the software
interrupt the RETI instruction must be used to return from interrupt
in order to restore the G bit to its previous state. However, if the G
bit was not enabled prior to the software interrupt the RET
instruction must be used.
Instruction
Immediate
Direct
Indexed
Indirect
ADC
A, #
A, M
A, [X]
ADD
A, #
A, M
A, [X]
AND
A, #
A, M
A, [X]
OR
A, #
A, M
A, [X]
SUBC
A, #
A, M
A, [X]
XOR
A, #
A, M
A, [X]
Inherent
CLR
M
A
X
INC
M
A
X
DEC
M
A
X
IFEQ
A, #
X, #
IFGT
A, #
X, #
IFNE
A, #
IFLT
M,#
A, M
A, [00,X]
A, [X]
A, M
A, [00,X]
A, [X]
A, M
A, [00,X]
A, [X]
no-op
RC
no-op
IFC
no-op
IFNC
no-op
INVC
no-op
LDC
#, M
STC
#, M
RLC
M
A
RRC
M
A
A, M
A, [00,X]
A, [X]
ST
A, M
A, [00,X]
A, [X]
LD
M, M
A, #
X, #
M, #
NOP
IFBIT
Absolute
X, #
SC
LD
Relative
no-op
#, A
#, M
SBIT
#, M
#, [X]
RBIT
#, M
#, [X]
JP
Rel
JSR
[00,X]
JMP
[00,X]
M
M
RET
no-op
RETI
no-op
INTR
no-op
15
ACE1202 Product Family Rev. B.1
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ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Table 9: Instruction Addressing Modes
Mnemonic Operand Bytes Cycles
Flags
affected
Mnemonic Operand Bytes Cycles
Flags
affected
ADC
A, [X]
1
1
C,H,Z,N
JMP
M
3
4
None
ADC
A, M
2
2
C,H,Z,N
JMP
[00,X]
2
3
None
ADC
A, #
2
2
C,H,Z,N
JP
1
1
None
ADD
A, [X]
1
1
Z,N
JSR
3
5
None
ADD
A, M
2
2
Z,N
JSR
[00,X]
2
5
None
ADD
A, #
2
2
Z,N
LD
A, #
2
2
None
AND
A, #
2
2
Z,N
LD
A, [00,X]
2
3
None
AND
A, M
2
2
Z,N
LD
A, [X]
1
1
None
AND
A, [X]
1
1
Z,N
LD
A, M
2
2
None
CLR
X
1
1
Z
LD
M, #
3
3
None
CLR
A
1
1
C,H,Z,N
LD
X, #
3
3
None
CLR
M
2
2
C,H,Z,N
LDC
#, M
2
2
C
DEC
A
1
1
Z,N
LD
M, M
3
3
None
DEC
M
2
2
Z,N
NOP
1
1
None
DEC
X
1
1
Z
OR
A, #
2
2
Z,N
IFBIT
#, A
1
1
None
OR
A, [X]
1
1
Z,N
IFBIT
#, M
2
2
None
OR
A, M
2
2
Z,N
1
1
None
IFC
M
RBIT
#, [X]
1
2
Z,N
IFEQ
A, [00,X]
2
3
None
RBIT
#, M
2
2
Z,N
IFEQ
A, [X]
1
1
None
RC
1
1
C,H
IFEQ
A, #
2
2
None
RET
1
5
None
IFEQ
A, M
2
2
None
RETI
1
5
None
IFEQ
M, #
3
3
None
RLC
A
1
1
C,Z,N
IFEQ
X, #
3
3
None
RLC
M
2
2
C,Z,N
IFGT
A, #
2
2
None
RRC
A
1
1
C,Z,N
IFGT
A, [00,X]
2
3
None
RRC
M
2
2
C,Z,N
IFGT
A, [X]
1
1
None
SBIT
#, [X]
1
2
Z,N
IFGT
A, M
2
2
None
SBIT
#, M
2
2
Z,N
IFGT
X, #
3
3
None
SC
1
1
C,H
IFNE
A, #
2
2
None
ST
A, [00,X]
2
3
None
IFNE
A, [00,X]
2
3
None
ST
A, [X]
1
1
None
IFNE
A, [X]
1
1
None
ST
A, M
2
2
None
IFNE
A, M
2
2
None
STC
#, M
2
2
Z,N
IFLT
X, #
3
3
None
SUBC
A, #
2
2
C,H,Z,N
1
1
None
SUBC
A, [X]
1
1
C,H,Z,N
IFNC
INC
A
1
1
Z,N
SUBC
A, M
2
2
C,H,Z,N
INC
M
2
2
Z,N
XOR
A, #
2
2
Z,N
INC
X
1
1
Z
XOR
A, [X]
1
1
Z,N
INTR
1
5
None
XOR
A, M
2
2
Z,N
INVC
1
1
C
16
ACE1202 Product Family Rev. B.1
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ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Table 10: Instruction Cycles and Bytes
All I/O ports, peripheral registers and core registers, except the accumulator and the program counter are mapped into memory space.
Table 11: Memory Map
Address
Memory Space
Block
Contents
0x00 - 0x3F
Data
SRAM
Data RAM
0x40 - 0x7F
Data
EEPROM
0xA0
Data
HBC
HBCNTRL register (ACE1202-2 only)
0xA1
Data
HBC
PSCALE register (ACE1202-2 only)
0xA2
Data
HBC
HPATTERN register (ACE1202-2 only)
0xA3
Data
HBC
LPATTERN register (ACE1202-2 only)
0xA4
Data
HBC
BPSEL register (ACE1202-2 only)
0xA9
Data
HBC
DAT0 register (ACE1202-2 only)
0xAA
Data
Timer1
Data EEPROM
T1RALO register
0xAB
Data
Timer1
T1RAHI register
0xAC
Data
Timer1
TMR1LO register
0xAD
Data
Timer1
TMR1HI register
0xAE
Data
Timer1
T1CNTRL register
0xAF
Data
MIW
WKEDG register
0xB0
Data
MIW
WKPND register
0xB1
Data
MIW
WKEN register
0xB2
Data
I/O
PORTGD register
0xB3
Data
I/O
PORTGC register
0xB4
Data
I/O
PORTGP register
0xB5
Data
Timer0
WDSVR register
0xB6
Data
Timer0
T0CNTRL register
0xB7
Data
Clock
0xB8 - 0xBC
HALT mode register
Reserved
0xBD
Data
LBD
LBD register
0xBE
Data
Core
XHI register
0xBF
Data
Core
XLO register
0xC0
Data
Core
Power mode clear (PMC) register
0xCE
Data
Core
SP register
0xCF
Data
Core
Status register (SR)
0x800 - 0xFF5
Program
EEPROM
0xFF6 - 0xFF7
Program
Core
Timer0 Interrupt vector
0xFF8 - 0xFF9
Program
Core
Timer1 Interrupt vector
0xFFA - 0xFFB
Program
Core
MIW Interrupt vector
0xFFC - 0xFFD
Program
Core
Software Interrupt vector
0xFFE - 0xFFF
Reserved
17
ACE1202 Product Family Rev. B.1
Code EEPROM
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ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
4.4 Memory Map
enter HALT/IDLE mode while the data EEPROM is busy (R = 0)
can affect the current data being written.
The ACEx microcontroller device has 64 bytes of SRAM and 64
bytes of EEPROM available for data storage. The device also has
2K bytes of EEPROM for program storage. Software can read and
write to SRAM and data EEPROM but can only read from the code
EEPROM. While in normal mode, the code EEPROM is protected
from any writes. The code EEPROM can only be rewritten when
the device is in program mode and if the write disable (WDIS) bit
of the initialization register is not set to 1.
4.6 Initialization Registers
The ACEx microcontroller has two 8-bit wide initialization registers. These registers are read from the memory space on powerup to initialize certain on-chip peripherals. Figure 14 provides a
detailed description of Initialization Register 1. The Initialization
Register 2 is used to trim the internal oscillator to its appropriate
frequency. This register is pre-programmed in the factory to yield
an internal instruction clock of 1MHz.
While in normal mode, the user can write to the data EEPROM
array by 1) polling the ready (R) flag of the SR, then 2) executing
the appropriate instruction. If the R flag is 1, the data EEPROM
block is ready to perform the next write. If the R flag is 0, the data
EEPROM is busy. The data EEPROM array will reset the R flag
after the completion of a write cycle. Attempts to read, write, or
Both Initialization Registers 1 and 2 can be read from and written
to during programming mode. However, re-trimming the internal
oscillator (writing to the Initialization Register 2) once it has left the
factory is discouraged.
Figure 14: Initialization Register 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CMODE[0]
CMODE[1]
WDEN
BOREN
BLSEL 10
UBD 8,9
WDIS 8,9
RDIS 8,9
(0) RDIS 8,9
If set, disables attempts to read the contents from the memory while in programming mode
(1) WDIS 8,9
If set, disables attempts to write new contents to the memory while in programming mode
(2) UBD 8,9
If set, the device will not allow any writes to occur in the upper block of data EEPROM (0x60-0x7F)
(3) BLSEL 10
If set, the Brown-out Reset (BOR) voltage reference level is set to its higher range for P.N. ACE1202/ACE12022
If not set, the BOR voltage reference level is set to its lower range for P.N. ACE1202L
(4) BOREN
If set, allows a BOR to occur if VCC falls below the voltage reference level
(5) WDEN
If set, enables the on-chip processor watchdog circuit
(6) CMODE[1]
Clock mode select bit 1 (See Table 17)
(7) CMODE[0]
Clock mode select bit 0 (See Table 17)
8
If both the WDIS and RDIS bits are set, the device will no longer be able to be placed into program mode.
9
If the RDIS or UBD bits are not set while the WDIS bit is not set, then the RDIS and UBD bits can be reset.
10
The BLSEL bit is set to its appropriate level in the factory. If writing to the initialization register is necessary, be sure to maintain BLSEL set value.
18
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ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
4.5 Memory
default, the TMR1 is reset to 0xFFFF, T1RA is reset to 0x0000,
and T1CNTRL is reset to 0x00.
Timer 1 is a versatile 16-bit timer that can operate in one of four
modes:
The timer can be started or stopped through the T1CNTRL
register bit T1C0. When running, the timer counts down (decrements) every clock cycle. Depending on the operating mode, the
timer’s clock is either the instruction clock or a transition on the T1
input. In addition, occurrences of timer underflow (transitions from
0x0000 to 0xFFFF/T1RA value) can either generate an interrupt
and/or toggle the T1 output pin.
• Pulse Width Modulation (PWM) mode, which generates
pulses of a specified width and duty cycle
• External Event Counter mode, which counts occurrences
of an external event
• Standard Input Capture mode, which measures the
elapsed time between occurrences of external events
Timer 1’s interrupt (TMRI1) can be enabled by interrupt enable
(T1EN) bit in the T1CNTRL register. When the timer interrupt is
enabled, depending on the operating mode, the source of the
interrupt is a timer underflow and/or a timer capture.
• Difference Input Capture mode, which automatically
measures the difference between edges
Timer 1 contains a 16-bit timer/counter register (TMR1), a 16-bit
auto-reload/capture register (T1RA), and an 8-bit control register
(T1CNTRL). All register are memory-mapped for simple access
through the core with both the 16-bit registers organized as a pair
of 8-bit register bytes {TMR1HI, TMR1LO} and {T1RAHI, T1RALO}.
Depending on the operating mode, the timer contains an external
input or output (T1) that is multiplexed with the I/O pin G2. By
12 and 13.
5.1 Timer control bits
Reading and writing to the T1CNTRL register controls the timer’s
operation. By writing to the control bits, the user can enable or
disable the timer interrupts, set the mode of operation, and start or
stop the timer. The T1CNTRL register bits are described in Tables
Table 12: TIMER1 Control Register (T1CNTRL)
T1CNTRL Register
Name
Function
Bit 7
T1C3
Timer TIMER1 control bit 3 (see Table 13)
Bit 6
T1C2
Timer TIMER1 control bit 2 (see Table 13)
Bit 5
T1C1
Timer TIMER1 control bit 1 (see Table 13)
Bit 4
T1C0
Timer TIMER1 run: 1 = Start timer, 0 = Stop timer;
or Timer TIMER1 underflow interrupt pending flag
in input capture mode
Bit 3
T1PND
Timer1 interrupt pending flag: 1 = Timer1 interrupt
pending, 0 = Timer1 interrupt not pending
Bit 2
T1EN
Timer1 interrupt enable bit: 1 = Timer1 interrupt enabled,
0 = Timer1 interrupt disabled
Bit 1
M4S1
Capture type: 0 = Pulse capture, 1 = Cycle capture (see Table 13)
Bit 0
-----------
Reserved
Table 13: TIMER1 Operating Modes
T1
C3
T1
C2
T1
C1
M4
S1
Timer Mode
Source
Interrupt A
0
0
0
x
MODE 2
TIMER1 Underflow
T1 Pos. Edge
0
0
1
x
MODE 2
TIMER1 Underflow
T1 Neg. Edge
1
0
1
x
MODE 1 T1 Toggle
Autoreload T1RA
Instruction Clock
1
0
0
x
MODE 1 No T1 Toggle
Autoreload T1RA
Instruction Clock
0
1
0
x
MODE 3 Captures: T1 Pos. edge
Pos. T1 Edge
Instruction Clock
0
1
1
x
MODE 3 Captures: T1 Neg. Edge
Neg. T1 Edge
Instruction Clock
1
1
0
0
MODE 4 Difference Capture
Pos. to Neg.
Instruction Clock
1
1
0
1
MODE 4 Difference Capture
Pos. to Pos.
Instruction Clock
1
1
1
0
MODE 4 Difference Capture
Neg. to Pos.
Instruction Clock
1
1
1
1
MODE 4 Difference Capture
Neg. to Neg.
Instruction Clock
19
ACE1202 Product Family Rev. B.1
Timer Counts On
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ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
5.0 Timer 1
1. Configure T1 as an output by setting bit 2 of PORTGC.
- SBIT 2, PORTGC
; Configure G2 as an output
In the PWM mode, the timer counts down at the instruction clock
rate. When an underflow occurs, the timer register is reloaded from
T1RA and the count down proceeds from the loaded value. At every
underflow, a pending flag (T1PND) located in the T1CNTRL register is set. Software must then clear the T1PND flag and load the
T1RA register with an alternate PWM value. In addition, the timer
can be configured to toggle the T1 output bit upon underflow.
Configuring the timer to toggle T1 results in the generation of a
signal outputted from port G2 with the width and duty cycle
controlled by the values stored in the T1RA. A block diagram of the
timer’s PWM mode of operation is shown in Figure 15.
2. Initialize T1 to 1 (or 0) by setting (or clearing) bit 2 of
PORTGD.
- SBIT 2, PORTGD
; Set G2 high
3. Load the initial PWM high (low) time into the timer register.
- LD TMR1LO, #6FH
; High (Low) for 1.391ms
(1MHz clock)
- LD TMR1HI, #05H
4. Load the PWM low (high) time into the T1RA register.
- LD T1RALO, #2FH
; Low (High) for .303ms
(1MHz clock)
- LD T1RAHI, #01H
The timer has one interrupt (TMRI1) that is maskable through the
T1EN bit of the T1CNTRL register. However, the core is only
interrupted if the T1EN bit and the G (Global Interrupt enable) bit of
the SR is set. If interrupts are enabled, the timer will generate an
interrupt each time T1PND flags is set (whenever the timer
underflows provided that the pending flag was cleared.) The
interrupt service routine is responsible for proper handling of the
T1PND flag and the T1EN bit.
5. Write the appropriate control value to the T1CNTRL
register to select PWM mode with T1 toggle, to clear the
enable bit and pending flag, and to start the timer. (See
Table 12 and 13)
- LD T1CNTRL, #0B0H
; Setting the T1C0 bit starts
the timer
6. After every underflow, load T1RA with alternate values. If
the user wishes to generate an interrupt on a T1 output
transition, reset the pending flags and then enable the
interrupt using T1EN. The G bit must also be set. The
interrupt service routine must reset the pending flag and
perform whatever processing is desired.
- RBIT T1PND, T1CNTRL
; T1PND equals 3
- LD T1RALO, #6FH
; High (Low) for 1.391ms
(1MHz clock)
- LD T1RAHI, #05H
The interrupt will be synchronous with every rising and falling edge
of the T1 output signal. Generating interrupts only on rising or falling
edges of T1 is achievable through appropriate handling of the T1EN
bit or T1PND flag through software.
The following steps show how to properly configure Timer 1 to
operate in the PWM mode. For this example, the T1 output signal
is toggled with every timer underflow and the “high” and “low” times
for the T1 output can be set to different values. The T1 output signal
can start out either high or low depending on the configuration of
G2; the instructions below are for starting with the T1 output high.
Follow the instructions in parentheses to start the T1 output low.
Figure 15: Pulse Width Modulation Mode
16-bit Auto-Reload
Register (T1RA)
Underflow
Interrupt
T1
Data
Bus
Data
Latch
16-bit Timer (TMR1)
Instruction
Clock
20
ACE1202 Product Family Rev. B.1
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ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
5.2 Mode 1: Pulse Width Modulation (PWM) Mode
1. Configure T1 as an input by clearing bit 2 of PORTGC.
- RBIT 2, PORTGC
; Configure G2 as an input
The External Event Counter mode operates similarly to the PWM
mode; however, the timer is not clocked by the instruction clock
but by transitions of the T1 input signal. The edge is selectable
through the T1C1 bit of the T1CNTRL register. A block diagram of
the timer’s External Event Counter mode of operation is shown in
Figure 16.
2. Initialize T1 to input with pull-up by setting bit 2 of PORTGD.
- SBIT 2, PORTGD
; Set G2 high
3. Enable the global interrupt enable bit.
- SBIT 4, STATUS
4. Load the initial count into the TMR1 and T1RA registers.
When the number of external events is detected, the counter
will reach zero; however, it will not underflow until the next
event is detected. To count N pulses, load the value N-1 into
the registers. If it is only necessary to count the number of
occurrences and no action needs to be taken at a particular
count, load the value 0xFFFF into the registers.
- LD TMR1LO, #0FFH
- LD TMR1HI, #00H
- LD T1RALO, #0FFH
- LD T1RAHI, #00H
The T1 input should be connected to an external device that
generates a positive/negative-going pulse for each event. By
clocking the timer through T1, the number of positive/negative
transitions can be counted therefore allowing software to capture
the number of events that occur. The input signal on T1 must have
a pulse width equal to or greater than one instruction clock cycle.
The counter can be configured to sense either positive-going or
negative-going transitions on the T1 pin. The maximum frequency
at which transitions can be sensed is one-half the frequency of the
instruction clock.
5. Write the appropriate control value to the T1CNTRL register
to select External Event Counter mode, to clock every falling
edge, to set the enable bit, to clear the pending flag, and to
start the counter. (See Table 12 and 13)
- LD T1CNTRL, #34H (#00h) ; Setting the T1C0 bit
starts the timer
As with the PWM mode, when the counter underflows the counter
is reloaded from the T1RA register and the count down proceeds
from the loaded value. At every underflow, a pending flag (T1PND)
located in the T1CNTRL register is set. Software must then clear
the T1PND flag and can then load the T1RA register with an
alternate value.
6. When the counter underflows, the interrupt service routine
must clear the T1PND flag and take whatever action is
required once the number of events occurs. If the software
wishes to merely count the number of events and the
anticipated number may exceed 65,536, the interrupt service
routine should record the number of underflows by
incrementing a counter in memory. Software can then
calculate the correct event count.
- RBIT T1PND, T1CNTRL
; T1PND equals 3
The counter has one interrupt (TMRI1) that is maskable through
the T1EN bit of the T1CNTRL register. However, the core is only
interrupted if the T1EN bit and the G (Global Interrupt enable) bit
of the SR is set. If interrupts are enabled, the counter will generate
an interrupt each time the T1PND flag is set (whenever timer
underflows provided that the pending flag was cleared.) The
interrupt service routine is responsible for proper handling of the
T1PND flag and the T1EN bit.
The following steps show how to properly configure Timer 1 to
operate in the External Event Counter mode. For this example, the
counter is clocked every falling edge of the T1 input signal. Follow
the instructions in parentheses to clock the counter every rising
edge.
Figure 16: External Event Counter Mode
16-bit Auto-Reload
Register (T1RA)
Data
Bus
Underflow
Interrupt
16-bit Counter (TMR1)
T1
Edge Selector
Logic
21
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ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
5.3 Mode 2: External Event Counter Mode
For example, the T1 pin can be programmed to be sensitive to a
positive-going edge. When the positive edge is sensed, the TMR1
register contents is transferred to the T1RA register and a Timer 1
interrupt is generated. The Timer 1 interrupt service routine records
the contents of the T1RA register, changes the edge sensitivity from
positive to negative-going edge, and clears the T1PND flag. When the
negative-going edge is sensed another Timer 1 interrupt is generated.
The interrupt service routine reads the T1RA register again. The
difference between the previous reading and the current reading
reflects the elapsed time between the positive edge and negative
edge of the T1 input signal i.e. the width of the positive-going pulse.
In the Input Capture mode, the timer is used to measure elapsed time
between edges of an input signal. Once the timer is configured for this
mode, the timer starts counting down immediately at the instruction
clock rate. The Timer 1 will then transfer the current value of the TMR1
register into the T1RA register as soon as the selected edge of T1 is
sensed. The input signal on T1 must have a pulse width equal to or
greater than one instruction clock cycle. At every T1RA capture,
software can then store the values into RAM to calculate the elapsed
time between edges on T1. At any given time (with proper consideration of the state of T1) the timer can be configured to capture on
positive-going or negative-going edges. A block diagram of the
timer’s Input Capture mode of operation is shown in Figure 17.
Remember that the Timer1 interrupt service routine must test the
T1C0 and T1PND flags to determine the cause of the interrupt. If the
T1C0 flag caused the interrupt, the interrupt service routine should
record the occurrence of an underflow by incrementing a counter in
memory or by some other means. The software that calculates the
elapsed time between captures should take into account the
number of underflow that occurred when making its calculation.
The timer has one interrupt (TMRI1) that is maskable through the
T1EN bit of the T1CNTRL register. However, the core is only
interrupted if the T1EN bit and the G (Global Interrupt enable) bit of the
SR is set. The Input Capture mode contains two interrupt pending
flags 1) the TMR1 register capture in T1RA (T1PND) and 2) timer
underflow (T1C0). If interrupts are enabled, the timer will generate an
interrupt each time a pending flag is set (provided that the pending flag
was previously cleared.) The interrupt service routine is responsible
for proper handling of the T1PND flag, T1C0 flag, and the T1EN bit.
The following steps show how to properly configure Timer 1 to
operate in the Input Capture mode.
1. Configure T1 as an input by clearing bit 2 of PORTGC.
- RBIT 2, PORTGC
; Configure G2 as an input
For this operating mode, the T1C0 control bit serves as the timer
underflow interrupt pending flag. The Timer 1 interrupt service
routine must read both the T1PND and T1C0 flags to determine the
cause of the interrupt. A set T1C0 flag means that a timer underflow
occurred whereas a set T1PND flag means that a capture occurred
in T1RA. It is possible that both flags will be found set, meaning that
both events occurred at the same time. The interrupt service routine
should take this possibility into consideration.
2. Initialize T1 to input with pull-up by setting bit 2 of PORTGD.
- SBIT 2, PORTGD
; Set G2 high
3. Enable the global interrupt enable bit.
- SBIT 4, STATUS
4. With the timer stopped, load the initial time into the TMR1
register (typically the value is 0xFFFF.)
- LD TMR1LO, #0FFH
- LD TMR1HI, #00H
Because the T1C0 bit is used as the underflow interrupt pending
flag, it is not available for use as a start/stop bit as in the other modes.
5. Write the appropriate control value to the T1CNTRL register
to select Input Capture mode, to sense the appropriate edge,
to set the enable bit, and to clear the pending flags. (See
Table 12 and 13)
- LD T1CNTRL, #64H
; T1C1 is the edge select bit
The TMR1 register counts down continuously at the instruction
clock rate starting from the time that the input capture mode is
selected. (See Table 12 and 13) To stop the timer from running,
you must change the mode to an alternate mode (PWM or
External Event Counter) while resetting the T1C0 bit.
6. As soon as the input capture mode is enabled, the timer
starts counting. When the selected edge is sensed on T1,
the T1RA register is loaded and a Timer 1 interrupt is
triggered.
The input pins can be independently configured to sense positivegoing or negative-going transitions. The edge sensitivity of pin T1
is controlled by bit T1C1 as indicated in Table 13.
The edge sensitivity of a pin can be changed without leaving the
input capture mode even while the timer is running. This feature
allows you to measure the width of a pulse received on an input pin.
Figure 17: Input Capture Mode
Capture
Interrupt
16-bit Input Capture
Register (T1RA)
T1
Edge Selector
Logic
Underflow
Interrupt
Data
Bus
16-bit Timer (TMR1)
Instruction
Clock
22
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5.4 Mode 3: Input Capture Mode
Once configured, the Difference Capture timer waits for the first
selected edge. when the edge transition has occurred, the 16-bit
timer starts counting up based every instruction clock cycle. It will
continue to count until the second selected edge transition occurs
at which time the timer stops and stores the elapse time into the
T1RA register.
The Difference Input Capture mode works similarly to the standard Input Capture mode. However, for the Difference Input
Capture the timer automatically captures the elapsed time between the selected edges without the core needing to perform the
calculation.
Software can now read the differnce between transitions directly
without using any processor resources. However, like the standard Input Capture mode both the capture (T1PND) and the
underflow (T1C0) flags must be monitored and handled appropriately. This feature allows the ACEx microcontroller to capture very
small pulses where standard microcontrollers might have missed
cycles due to the limited bandwidth.
For example, the standard Input Captrue mode requires that the
timer be configured to capture a particular edge (rising or falling)
at which time the timer's value is copied into the capture register.
if the elapsed time is required, software must move the captured
data into RAM and reconfigure the Input Capture mode to capture
on the next edge (rising or falling). Software must then subtract the
difference between the two edges to yield useful information.
The Difference Capture mode eliminates the need for software
intervention and allows for capturing very short pulse or cycle
widths. it can be configured to capture the elapsed time between:
1. positive to negative-going edges
2. positive to positive-going edges
3. negative to positive-going edges
4. negative to negative-going edges
Figure 18: Difference Capture Mode
Capture
Interrupt
16-bit Input Capture
Register (T1RA)
Difference
Logic
T1
Data
Bus
Edge Selector
Logic
Underflow
Interrupt
16-bit Timer (TMR1)
Instruction
Clock
23
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ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
5.5 Mode 4: Difference Input Capture Mode
reset by software or system reset.
Timer 0 is a 12-bit free running idle timer. Upon power-up or any
reset, the timer is reset to 0x000 and then counts up continuously
based on the instruction clock of 1MHz (1 µs). Software cannot
read from or write to this timer. However, software can monitor the
timer’s pending (T0PND) bit that is set every 8192 cycles (initially
4096 cycles after a reset). The T0PND flag is set every other time
the timer overflows (transitions from 0xFFF to 0x000) through a
divide-by-2 circuit. After an overflow, the timer will reset and restart
its counting sequence.
The WKINTEN bit is used in the Multi-input Wakeup/Interrupt
block. See Section 8 for details.
7.0 Watchdog timer
The Watchdog timer is used to reset the device and safely recover
in the rare event of a processor “runaway condition.” The 12-bit
Timer 0 is used as a pre-scaler for Watchdog timer. The Watchdog
timer must be serviced before every 61,440 cycles but no sooner
than 4096 cycles since the last Watchdog reset. The Watchdog is
serviced through software by writing the value 0x1B to the
Watchdog Service (WDSVR) register (see Figure 20). The part
resets automatically if the Watchdog is serviced too frequent, or
not frequent enough.
Software can either poll the T0PND bit or vector to an interrupt
subroutine. In order to interrupt on a T0PND, software must be
sure to enable the Timer 0 interrupt enable (T0INTEN) bit in the
Timer 0 control (T0CNTRL) register and also make sure the G bit
is set in SR. Once the timer interrupt is serviced, software should
reset the T0PND bit before exiting the routine. Timer 0 supports
the following functions:
The Watchdog timer must be enabled through the Watchdog
enable bit (WDEN) in the initialization register. The WDEN bit can
only be set while the device is in programming mode. Once set, the
Watchdog will always be powered-up enabled. Software cannot
disable the Watchdog. The Watchdog timer can only be disabled
in programming mode by resetting the WDEN bit as long as the
memory write protect (WDIS) feature is not enabled.
1. Exiting from IDLE mode (See Section 17.0 for details.)
2. Start up delay from HALT mode
3. Watchdog pre-scaler (See Section 7.0 for details.)
The T0INTEN bit is a read/write bit. If set to 0, interrupt requests
from the Timer 0 are ignored. If set to 1, interrupt requests are
accepted. Upon reset, the T0INTEN bit is reset to 0.
WARNING
Ensure that the Watchdog timer has been serviced before entering IDLE mode because it remains operational during this time.
The T0PND bit is a read/write bit. If set to 1, it indicates that a Timer
0 interrupt is pending. This bit is set by a Timer 0 overflow and is
Figure 19: Timer 0 Control Register (T0CNTRL)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WKINTEN
x
x
x
x
x
T0PND
T0INTEN
Figure 20: Watchdog Server Register (WDSVR)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
1
0
1
1
24
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ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
6.0 Timer 0
either port G2 or G5. If IOSEL is 1, G5 is selected as the output port
otherwise G2 is selected.
The ACE1202-2 contains a dedicated hardware bit-encoding
peripheral block, Hardware Bit-Coder (HBC), for IR/RF data
transmission (see Figure 21.) The HBC is completely software
programmable and can be configured to emulate various bitencoding formats. The software developer has the freedom to
encode each bit of data into a desired pattern and output the
encoded data at the desired frequency through either the G2 or G5
output (TX) ports.
The TXBUSY signal is read only and is used to inform software
that a transmission is in progress. TXBUSY goes high when the
encoded data begins to shift out of the output port and will remains
high during each consecutive DAT0 frame bit transmission (see
Figure 25). The HBC will clear the TXBUSY signal when the last
DAT0 encoded bit of the frame is transmitted and the STOP signal
is 0.
The START / STOP signal controls the encoding and transmission
process for each data frame. When software sets the START /
STOP bit the DAT0 frame transmission process begins. The
START signal will remain high until the beginning of the last
encoded DAT0 frame bit transmission. The HBC then clears the
START / STOP bit allowing software to either continue with a new
DAT0 frame transmission or stop the transmission all together
(see Figure 25). If TXBUSY is 0 when the START signal is
enabled, a synchronization period occurs before any data is
transmitted lasting the amount of time to transmit a 0 encoded bit
(see Figure 24).
The HBC contains six 8-bit memory-mapped configuration registers PSCALE, HPATTERN, LPATTERN, BPSEL, HBCNTRL, and
DAT0. The registers are used to select the transmission frequency, store the data bit-encoding patterns, configure the data
bit-pattern/frame lengths, and control the data transmission flow.
To select the IR/RF transmission frequency, an 8-bit divide
constant must be written into the IR/RF Pre-scalar (PSCALE)
register. The IR/RF transmission frequency generator divides the
1MHz instruction clock down by 4 and the PSCALE register is
used to select the desired IR/RF frequency shift. Together, the
transmission frequency range can be configured between 976Hz
(PSCALE = 0xFF) and 125kHz (PSCALE = 0x01). Upon a reset,
the PSCALE register is initialized to zero disabling the IR/RF
transmission frequency generator. However, once the PSCALE
register is programmed, the desired IR/RF frequency is maintained as long as the device is powered.
The OCFLAG signal is read only and goes high when the last
encoded bit of the DAT0 frame is transmitting. The OCFLAG
signal is used to inform software that the DAT0 frame transmission
operation is completing (see Figure 25). If multiple DAT0 frames
are to be transmitted consecutively, software should poll the
OCFLAG signal for a 1. Once OCFLAG is 1, DAT0 must be reload
and the START / STOP bit must be restored to 1 in order to begin
the new frame transmission without interruptions (the synchronization period). Since OCFLAG remains high during the entire last
encoded DAT0 frame bit transmission, software should wait for
the HBC to clear the OCFLAG signal before polling for the new
OCFLAG high pulse. If new data is not reloaded into DAT0 and the
START signal (STOP is active) is not set before the OCFLAG is
0, the transmission process will end (TXBUSY is cleared) and a
new process will begin starting with the synchronization period.
Once the transmission frequency is selected, the data bit-encoding patterns must be stored in the appropriate registers. The HBC
contains two 8-bit bit-encoding pattern registers, High-pattern
(HPATTERN) and Low-pattern (LPATTERN). The encoding pattern stored in the HPATTERN register is transmitted when the
data bit value to be encoded is a 1. Similarly, the pattern stored in
the LPATTERN register is transmitted when the data bit value to
be encoded is a 0. The HBC transmits each encoded pattern MSB
first.
The number of bits transmitted from the HPATTERN and
LPATTERN registers is software programmable through the Bit
Period Configuration (BPSEL) register (see Figure 22). During the
transmission of HPATTERN, the number of bits transmitted is
configured by BPH[2:0] (BPSEL[2:0]) while BPL[2:0] (BPSEL[5:3])
configures the number of transmitted bits for the LPATTERN. The
HBC allows from 2 (0x1) to 8 (0x7) encoding pattern bits to be
transmitted from each register. Upon a reset, BPSEL is initially 0
disabling the HBC from transmitting pattern bits from either
register.
Figure 24 and 25 shows how the HBC performs its data encoding.
In the example, two frames are encoded and transmitted consecutively with the following bit encoding format specification:
1. Transmission frequency = 62.5KHz
2. Data to be encoded = 0x52, 0x92 (all 8-bits)
3. Each bit should be encoded as a 3-bit binary value, ‘1’ =
110b and ‘0’ = 100b
4. Transmission output port : G2
To perform the data transmission, software must first initialize the
PSCALE, BPSEL, HPATTERN, LPATTERN, and DAT0 registers
with the appropriate values.
The Data (DAT0) register is used to store up to 8 bits of data to be
encoded and transmitted by the HBC. This data is shifted, bit by
bit, MSB to LSB into a 1-bit decision register. If the active bit shifted
into the decision register is 1, the pattern in the HPATTERN
register is shifted out of the output port. Similarly, if the active bit
is 0 the pattern in the LPATTERN register is shifted out.
The HBC control (HBCNTRL) register is used to configure and
control the data transmission. HBCNTRL is divided in 5 different
controlling signal FRAME[2:0], IOSEL, TXBUSY, START/STOP,
and OCFLAG (see Figure 23.)
; (1MHz ÷ 4) ÷ 4 = 62.5KHz
LD BPSEL, #012H
; BPH = 2, BPL = 2 (3 bits each)
LD HPATTERN, #0C0H
; HPATTERN = 0xC0
LD LPATTERN, #090H
; LPATTERN = 0x90
LD DAT0, #052H
; DAT0 = 0x52
Once the basic registers are initialized, the HBC can be started.
(At the same time, software must set the number of data bits per
data frame and select the desired output port.)
FRAME[2:0] selects the number of bits of DAT0 to encode and
transmit. The HBC allows from 2 (0x1) to 8 (0x7) DAT0 bits to be
encoded and transmitted. Upon a reset, FRAME is initialized to
zero disabling the DAT0’s decision register transmitting no data.
LD HBCNTRL, #27H
The IOSEL signal selects the transmission to output (TX) through
25
ACE1202 Product Family Rev. B.1
LD PSCALE, #03H
; START / STOP = 1,
FRAME = 7, IOSEL = 0
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8.0 Hardware Bit-Coder (ACE1202-2 only)
If software is to proceed with another data transmission, the
OCFLAG must be zero before polling for the next OCFLAG high
pulse. However, since the specification in the example requires no
other data transmission software can proceed as desired.
LOOP_HI:
IFBIT OCFLAG, HBCNTRL
JP
NXT_FRAME
JP
LOOP_HI
LOOP_LO:
; Wait for OCFLAG = 1
IFBIT OCFLAG, HBCNTRL
JP
LOOP_LO
Etc.
NXT_FRAME:
LD
DAT0, #092H
SBIT START, HBCNTRL
; Wait for OCFLAG = 0
; Program proceeds as desired
; DAT0 = 0x92
; START / STOP = 1
Figure 21: Hardware Bit-Coder (HBC) Block Diagram
IR/RF
CLOCK
RFCLK
b7
HPATTERN
StopShift
A
Y
G2
B
CPU
CLOCK
Fixed
Clock Divider
by 4
PSCALE
RFCLK
G5
b7
LPATTERN
StopShift
8
IOSEL
HBCNTRL[6]
[PSCALE]
ShiftCLK
Down
Counter
DAT0
NoShift
b7
OCFLAG
Sync
LOGIC
3
3
FRAME[2:0]
[HBCNTRL]
Y
A
3
BPH[2:0]
[BPSEL]
OCFLAG
HBCNTRL[7]
START/STOP
HBCNTRL[5]
B
TXBUSY
HBCNTRL[4]
3
BPL[2:0]
[BPSEL]
Figure 22: Bit Period Configuration (BPSEL) Register
Bit 7
Bit 6
0
0
Bit 5
Bit 4
Bit 3
Bit 2
BPL[2:0]
Bit 1
Bit 0
BPH[2:0]
Figure 23: HBC Control (HBCNTRL) Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
OCFLAG
IOSEL
START/STOP
TXBUSY
0
26
ACE1202 Product Family Rev. B.1
Bit 2
Bit 1
Bit 0
FRAME[2:0]
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ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
After the HBC has started, software must then poll the OCFLAG
for a high pulse and restore the DAT0 register and the START
signal to continue with the next data transmission.
Condition:
BPSEL = 0x12 [ "1", " 0 " = 3 * IR/RF Clocks]
DAT0 = 0x52
No. bit to encode = 8 (HBCNTRL = XXXX0111b)
TXBUSY
START/STOP
ShiftCLK
OCFLAG
SYNC
Period
Bit 7
DAT0
"0"
"0"
"1"
"0"
"1"
"0"
"0"
"0"
"1"
G2/G5
Output
IR/RF
CLOCK
¡
Figure 25: Sending series of encoded messages
Conditions:
BPSEL = 0x12 [ "1", " 0 " = 3 * IR/RF Clocks]
DAT0 = 0x52 , 0x92
No. bit to encode = 8 (HBCNTRL = XXXX0111b)
Software must set the START bit while OCFLAG is set in
order to send another message without introducing a delay.
TXBUSY
STOP bit clear,
transmission ends.
START/STOP
ShiftCLK
OCFLAG
Bit 7
DAT0
SYNC
Period
"0"
"0"
"1" "0"
"1" "0"
"0"
"1" "0"
"1"
"0" "0"
"1"
"0"
"0"
"1"
"0"
G2/G5
Output
IR/RF
CLOCK
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Figure 24: HBC signals for one byte message in PWM format
6. Set the WKEN bits associated with the pins to be used, thus
enabling those pins for the Wakeup/Interrupt function.
- LD WKEN, #10H
; Enabling G4
The Multi-Input Wakeup (MIW)/Interrupt contains three memory-mapped
registers associated with this circuit: WKEDG (Wakeup Edge), WKEN
(Wakeup Enable), and WKPND (Wakeup Pending). Each register has
8-bits with each bit corresponding to an input pins as shown in Figure
26. All three registers are initialized to zero upon reset.
Once the Multi-Input Wakeup/Interrupt function has been configured, a transition sensed on any of the I/O pins will set the
corresponding bit in the WKPND register. The WKPND bits , where
the corresponding enable (WKEN ) bits are set, will bring the device
out of the HALT mode and can also trigger an interrupt if interrupts
are enabled. The interrupt service routine can read the WKPND
register to determine which pin sensed the interrupt.
The WKEDG register establishes the edge sensitivity for each of
the wake-up input pin: either positive going-edge (0) or negativegoing edge (1).
The WKEN register enables (1) or disables (0) each of the port
pins for the Wakeup/Interrupt function. The wakeup I/Os used for
the Wakeup/Interrupt function must also be configured as an input
pin in its associated port configuration register. However, an
interrupt of the core will not occur unless interrupts are enabled for
the block via bit 7 of the T0CNTRL register (see Figure 19) and the
G (global interrupt enable) bit of the SR is set.
The interrupt service routine or other software should clear the
pending bit. The device will not enter HALT mode as long as a
WKPND pending bit is pending and enabled. The user has the
responsibility of clearing the pending flags before attempting to
enter the HALT mode.
Upon reset, the WKEDG register is configured to select positivegoing edge sensitivity for all wakeup inputs. If the user wishes to
change the edge sensitivity of a port pin, use the following procedure to avoid false triggering of a Wakeup/Interrupt condition.
The WKPND register contains the pending flags corresponding to
each of the port pins (1 for wakeup/interrupt pending, 0 for
wakeup/interrupt not pending).
1. Clear the WKEN bit associated with the pin to disable that pin.
To use the Multi-Input Wakeup/Interrupt circuit, perform the steps listed
below. Performing the steps in the order shown will prevent false
triggering of a Wakeup/Interrupt condition. This same procedure
should be used following any type of reset because the wakeup inputs
are left floating after resets resulting in unknown data on the port inputs.
2. Write the WKEDG register to select the new type of edge
sensitivity for the pin.
1. Clear the WKEN register.
- CLR WKEN
PORTG provides the user with three fully selectable, edge sensitive interrupts that are all vectored into the same service subroutine. The interrupt from PORTG shares logic with the wakeup
circuitry. The WKEN register allows interrupts from PORTG to be
individually enabled or disabled. The WKEDG register specifies
the trigger condition to be either a positive or a negative edge. The
WKPND register latches in the pending trigger conditions.
3. Clear the WKPND bit associated with the pin.
4. Set the WKEN bit associated with the pin to re-enable it.
2. If necessary, write to the port configuration register to select
the desired port pins to be configured as inputs.
- RBIT 4, PORTGC
; G4
3. If necessary, write to the port data register to select the
desired port pins input state.
- SBIT 4, PORTGD
; Pull-up
Since PORTG is also used for exiting the device from the HALT mode,
the user can elect to exit the HALT mode either with or without the interrupt
enabled. If the user elects to disable the interrupt, then the device restarts
execution from the point at which it was stopped (first instruction cycle of
the instruction following HALT mode entrance instruction). In the other
case, the device finishes the instruction that was being executed when the
part was stopped and then branches to the interrupt service routine. The
device then reverts to normal operation.
4. Write the WKEDG register to select the desired type of edge
sensitivity for each of the pins used.
- LD WKEDG, #0FFH
; All negative-going edges
5. Clear the WKPND register to cancel any pending bits.
- CLR WKPND
Figure 26: Multi-input Wakeup (MIW) Register bit assignments
WKEDG, WKEN, WKPND
11
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
11G7
11G6
G5
G4
G3
G2
G1
G0
Available only on the 14-pin package option
Figure 27: Multi-input Wakeup (MIW) Block Diagram
Data Bus
7
0
WKEN[7:0]
G0
0
WKOUT
EDGEI
G7
7
WKEDG[0:7]
12
WKINTEN 11
WKPND[0:7]
WKINTEN: Bit 7 of T0CNTRL
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9.0 Multi-Input Wakeup/Interrupt Block
(PORTGC), a port data register (PORTGD), and a port input
register (PORTGP). PORTGC is used to configure the pins as
inputs or outputs. A pin may be configured as an input by writing
a 0 or as an output by writing a 1 to its corresponding PORTGC bit.
If a pin is configured as an output, its PORTGD bit represents the
state of the pin (1 = logic high, 0 = logic low). If the pin is configured
as an input, its PORTGD bit selects whether the pin is a weak pullup or a high-impedence input. Table 14 provides details of the port
configuration options. The port configuration and data registers
can both be read from or written to. Reading PORTGP returns the
value of the port pins regardless of how the pins are configured.
Since this device supports MIW, PORTG inputs have Schmitt
triggers.
The eight I/O pins (six on 8-pin package option) are bi-directional
(see Figure 28) with the exception of G3 which is always an input
with weak pull-up. The bi-directional I/O pins can be individually
configured by software to operate as high-impedance inputs, as
inputs with weak pull-up, or as push-pull outputs. The operating
state is determined by the contents of the corresponding bits in the
data and configuration registers. Each bi-directional I/O pin can be
used for general purpose I/O, or in some cases, for a specific
alternate function determined by the on-chip hardware.
10.1 I/O registers
The I/O pins (G0-G7) have three memory-mapped port registers
associated with the I/O circuitry: a port configuration register
Figure 28: PORTG Logic Diagram
GXPULLEN
GXBUFEN
PADGX
GXOUT
GXIN
Figure 29: I/O Register bit assignments (PORTGC,PORTGD, PORTGD)
Bit 7
Bit 6
13G7
13G6
13
Available only on the 14-pin package option
14
G3 is always an input with weak pull-up
Bit 5
G5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
G4
14G3
G2
G1
G0
Table 14: I/O configuration options
Configuration Bit
Data Bit
Port Pin Configuration
0
0
High-impedence input (TRI-STATE input)
0
1
Input with pull-up (weak one input)
1
0
Push-pull zero output
1
1
Push-pull one output
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10.0 I/O Port
The ACEx microcontroller supports in-circuit programming of the
internal data EEPROM, code EEPROM, and the initialization registers.
0V phase (if the timing specifications in Figure 30 are obeyed).
The device will set the R bit of the Status register when the write
operation has completed. The external programmer must wait for
the SHIFT_OUT pin to go high before bringing the LOAD signal to
5V to initiate a normal command cycle.
An externally controlled four wire interface consisting of a LOAD
control pin (G3), a serial data SHIFT-IN input pin (G4), a serial data
SHIFT-OUT output pin (G2), and a CLOCK pin (G1) is used to access
the on-chip memory locations. Communication between the ACEx
microcontroller and the external programmer is made through a 32bit command and response word described in Table 15.
11.2 Read Sequence
When reading the device after a write, the external programmer
must set the LOAD signal to 5V before it sends the new command
word. Next, the 32-bit serial command word (for during a READ)
should be shifted into the device using the SHIFT_IN and the
CLOCK signals while the data from the previous command is
serially shifted out on the SHIFT_OUT pin. After the Read command has been shifted into the device, the external programmer
must, once again, set the LOAD signal to 0V and apply two clock
pulses as shown in Figure 30 to complete READ cycle. Data from
the selected memory location, will be latched into the lower 8 bits
of the command word shortly after the second rising edge of the
CLOCK signal.
The serial data timing for the four-wire interface is shown in Figure
31 and the programming protocol is shown in Figure 30.
11.1 Write Sequence
The external programmer brings the ACEx microcontroller into
programming mode by applying a super voltage level to the LOAD
pin. The external programmer then needs to set the LOAD pin to 5V
before shifting in the 32-bit serial command word using the SHIFT_IN
and CLOCK signals. By definition, bit 31 of the command word is
shifted in first. At the same time, the ACEx microcontroller shifts out
the 32-bit serial response to the last command on the SHIFT_OUT
pin. It is recommended that the external programmer samples this
signal tACCESS (500ns) after the rising edge of the CLOCK signal.
The serial response word, sent immediately after entering programming mode, contains indeterminate data.
Writing a series of bytes to the device is achieved by sending a
series of Write command words while observing the devices
handshaking requirements.
Reading a series of bytes from the device is achieved by sending
a series of Read command words with the desired addresses in
sequence and reading the following response words to verify the
correct address and data contents.
After 32 bits have been shifted into the device, the external
programmer must set the LOAD signal to 0V, and then apply two
clock pulses as shown in Figure 30 to complete program cycle.
The addresses of the data EEPROM and code EEPROM locations are the same as those used in normal operation.
The SHIFT_OUT pin acts as the handshaking signal between the
device and programming hardware once the LOAD signal is
brought low. The device sets SHIFT_OUT low by the time the
programmer has sent the second rising edge during the LOAD =
Powering down the device will cause the part to exit programming
mode.
Table 15: 32-Bit Command and Response Word
Bit number
Input command word
Output response word
bits 31 – 30
Must be set to 0
X
bit 29
Set to 1 to read/write data EEPROM, or the
initialization registers, otherwise 0
X
bit 28
Set to 1 to read/write code EEPROM,
otherwise 0
X
bits 27 – 25
Must be set to 0
X
bit 24
Set to 1 to read, 0 to write
X
bits 23 – 19
Must be set to 0
X
bits 18 – 8
Address of the byte to be read or written
Same as Input command word
bits 7 – 0
Data to be programm ed or zero if data is to be read
Programmed data or data read at specified address
15
For further information see Application Note AN-8005.
16
During in-circuit programming, G5 must be either not connected or driven high.
30
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ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
11.0 In-circuit Programming Specification15,16
tSV1
tSV2
A
A
tload1 tload2
LOAD (G3)
enter prog.
mode
tready
tload3
tload4
32 clock pulses
CLOCK (G1)
SHIFT_IN (G4)
bit 31
bit 30
bit 0
bit 31
BUSY low by
2nd clock pulse
SHIFT_OUT (G2)
(in write mode)
READY
BUSY
SHIFT_OUT (G2)
(in read mode)
A: start of programming cycle
Figure 31: Serial Data Timing
tHI
tLO
CLOCK (G1)
tDIS
SHIFT_IN (G4)
tDIH
Valid
tDOS
tDOH
Valid
SHIFT_OUT (G2)
tACCESS
31
ACE1202 Product Family Rev. B.1
www.fairchildsemi.com
ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 30: Programming Protocol16
zero before rising back to operating range. The Brown-out Reset
can be thought of as a supplement function to the Power-on Reset
when VCC does not fall below ~1.5V. The Power-on Reset circuit
works best when VCC starts from zero and rises sharply. So in
applications where VCC is not constant, the BOR will give added
device stability.
The Brown-out Reset (BOR) and Low Battery Detect (LBD)
circuits on the ACEx microcontroller have been designed to offer
two types of voltage reference comparators. The sections below
will describe the functionality of both circuits.
Figure 32: BOR/LBD Block Diagram
The BOR circuit must be enabled through the BOR enable bit
(BOREN) in the initialization register. The BOREN bit can only be
set while the device is in programming mode. Once set, the BOR
will always be powered-up enabled. Software cannot disable the
BOR. The BOR can only be disabled in programming mode by
resetting the BOREN bit as long as the global write protect (WDIS)
feature is not enabled.
Vcc
1.8V
0
2.2V
1
S
_
BOR
to RESET logic
+
BLSEL17
18
_
LBD
7
17
6
5
12.2 Low Battery Detect
+
Adjust Reference Voltage
4
3
2
BOR is not available on the P.N. ACE1202B/ACE12022B device
1
0
The Low Battery Detect (LBD) circuit allows software to monitor
the VCC level at the lower voltage ranges. LBD has an eight level
software programmable voltage reference threshold that can be
changed on the fly. Once VCC falls below the selected threshold,
the LBD flag in the LBD control register is set. The LBD flag will
hold its value until VCC rises above the threshold. (See Table 16)
LBD
Control
Register
See Figure 14 for information on BLSEL.
12.1 Brown Out Reset 18
The LBD bit is read only. If LBD is 0, it indicates that the VCC level
is higher than the selected threshold. If LBD is 1, it indicates that
the VCC level is below the selected threshold. The threshold level
can be adjusted up to eight levels using the three trim bits
(Bat_trim[2:0]) of the LBD control register. The LBD flag does not
cause any hardware actions or an interruption of the processor. It
is for software monitoring only.
The Brown-out Reset (BOR) function is used to hold the device in
reset when VCC drops below a fixed threshold. (See BOR Electrical Characteristics for threshold voltage.) While in reset, the
device is held in its initial condition until VCC rises above the
threshold value. Shortly after VCC rises above the threshold value,
an internal reset sequence is started. After the reset sequence, the
core fetches the first instruction and starts normal operation.
The LBD function is disabled during HALT/IDLE mode. After
exiting HALT/IDLE, software must wait at least 10 µs before
reading the LBD bit to ensure that the internal circuit has stabilized.
On the devices, the BOR should be used in situations when VCC
rises and falls slowly and in situations when VCC does not fall to
Table 16: LBD Control Register Definition
Bit 7
Bit 6
Bit 5
Bat_trim[2:0]
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
X
X
X
LBD
Level
Bat_trim[2]
Bat_trim[1]
1
0
0
0
2.9 - 3.0
2
0
0
1
2.8 - 2.9
3
0
1
0
2.7 - 2.8
4
0
1
1
2.6 - 2.7
5
1
0
0
2.5 - 2.6
6
1
0
1
2.4 - 2.5
7
1
1
0
2.3 - 2.4
8
1
1
1
2.2 - 2.3
32
ACE1202 Product Family Rev. B.1
Voltage
Reference
Bat_trim[0] Range (±20%)
www.fairchildsemi.com
ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
12.0 Brown-out/Low Battery Detect Circuit
The external reset provides a way to properly reset the ACEx
microcontroller if POR cannot be used in the application. The
external reset pin contains an internal pull-up resistor. Therefore,
to reset the device the reset pin should be held low for at least 2ms
so that the internal clock has enough time to stabilize.
When a RESET sequence is initiated, all I/O registers will be reset
setting all I/Os to high-impedence inputs. The system clock is
restarted after the required clock start-up delay. A reset is generated by any one of the following three conditions:
15.0 CLOCK
• Power-on Reset (as described in Section 14.0)
The ACEx microcontroller has an on-board oscillator trimmed to
a frequency of 2MHz who is divided down by two yielding a 1MHz
frequency. (See AC Electrical Characteristics.) Upon power-up,
the on-chip oscillator runs continuously unless entering HALT
mode or using an external clock source.
• Brown-out Reset (as described in Section 12.1)
• Watchdog Reset (as described in Section 7.0)
• External Reset18 (as described in Section 14.0)
18
Available only on the 14-pin package option.
14.0 Power-On-Reset
If required, an external oscillator circuit may be used depending on
the states of the CMODE bits of the initialization register. (See
Table 17) When the device is driven using an external clock, the
clock input to the device (G1/CKI) can range between DC to
4MHz. For external crystal configuration, the output clock (CKO)
is on the G0 pin. (See Figure 34) If an external crystal or RC is
used, internally the input frequency (CKI) is divided-down by four
to yield the corresponding instruction clock. If the device is
configured for an external square clock, it will not be divided.
The Power-On Reset (POR) circuit is guaranteed to work if the
rate of rise of VCC is no slower than 10ms/1volt. The POR circuit
was designed to respond to fast low to high transitions between 0V
and VCC. The circuit will not work if VCC does not drop to 0V before
the next power-up sequence. In applications where 1) the VCC rise
is slower than 10ms/1 volt or 2) VCC does not drop to 0v before the
next power-up sequence the external reset option should be used.
Table 17: CMODEx Bit Definition
CMODE[1]
CMODE[0]
Clock Type
0
0
Internal 1 MHz clock
0
1
External square clock
1
0
External crystal/resonator
1
1
External RC clock
Figure 33: BOR and POR Circuit Relationship Diagram
VCC (Pin 8)
BOR
output
VCC
1.75
VCC
0
VCC
0
Time
BOR Output
A
POR
output
External
Reset
Pin
(14-Pin Only)
VCC
5.0V
(Pin 7)
1.8V
0
VCC
POR
output 0
Global Reset
to Logic
B
The Reset circuit will trigger
when inputs A or B transition
from High to Low. At that time
the Global Reset signal will go
high which will reset all controller
logic. The Global Reset will go
high and stay high for around 1µs.
POR Output
Pulse
33
ACE1202 Product Family Rev. B.1
Reset
circuit
output
www.fairchildsemi.com
ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
13.0 RESET block
a)
b)
CKI
(G1)
CKO
(G0)
CKI
(G1)
CKO
(G0)
1M
R
VCC
C
33pF
33pF
15.0 HALT Mode
17.0 IDLE Mode
The HALT mode is a power saving feature that almost completely
shuts down the device for current conservation. The device is
placed into HALT mode by setting the HALT enable bit (EHALT)
of the HALT register through software using only the “LD M, #”
instruction. EHALT is a write only bit and is automatically cleared
upon exiting HALT. When entering HALT, the internal oscillator
and all the on-chip systems including the LBD and the BOR
circuits are shut down.
In addition to the HALT mode power saving feature, the device
also supports an IDLE mode operation. The device is placed into
IDLE mode by setting the IDLE enable bit (EIDLE) of the HALT
register through software using only the “LD M, #” instruction.
EIDLE is a write only bit and is automatically cleared upon exiting
IDLE. The IDLE mode operation is similar to HALT except the
internal oscillator, the Watchdog, and the Timer 0 remain active
while the other on-chip systems including the LBD and the BOR
circuits are shut down.
The device can exit HALT mode only by the MIW circuit. Therefore, prior to entering HALT mode, software must configure the
MIW circuit accordingly. (See Section 9) After a wakeup from
HALT, a 1ms start-up delay is initiated to allow the internal
oscillator to stabilize before normal execution resumes. Immediately after exiting HALT, software must clear the Power Mode
Clear (PMC) register by only using the “LD M, #” instruction. (See
Figure 36)
The device automatically wakes from IDLE mode by the Timer 0
overflow every 8192 cycles (see Section 6). Before entering IDLE
mode, software must clear the WKEN register to disable the MIW
block. Once a wake from IDLE mode is triggered, the core will begin
normal operation by the next clock cycle. Immediately after exiting
IDLE mode, software must clear the Power Mode Clear (PMC)
register by using only the "LD M, #" instruction. (See Figure 37)
Figure 35: HALT Register Definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
undefined
undefined
undefined
undefined
undefined
undefined
EIDLE
EHALT
Figure 36: Recommended HALT Flow
Figure 37: Recommended IDLE Flow
Normal Mode
Normal Mode
CLR WKEN
LD HALT, #02h
LD HALT, #01h
Multi-Input
Wakeup
Timer 0
Overflow
Halt
LD PMC, #00h
LD PMC, #00h
Resume
Normal Mode
Resume
Normal Mode
34
ACE1202 Product Family Rev. B.1
IDLE
www.fairchildsemi.com
ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 34: Crystal (a) and RC (b) Oscillator Diagrams
Part Number
Core Type
0
1
2
Max. #
I/Os
8
Program
Memory Size
1K
2K
Operating Voltage
Range
1.8 – 2.2 – 2.7 –
5.5V 5.5V 5.5V
Temperature Range
0 to
70°C
-40 to -40 to
+85C +125°C
Package
8-pin
SOIC
14-pin
SOIC
ACE1202M8
X
X
X
X
X
X
ACE1202M8X
X
X
X
X
X
X
ACE1202M
X
X
X
X
X
X
X
ACE1202MX
X
X
X
X
X
ACE1202N
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ACE1202EM8X
X
X
X
X
X
X
ACE1202EM
X
X
X
X
X
X
X
X
X
ACE1202EMX
X
X
X
X
X
ACE1202EN
X
X
X
X
X
ACE1202EN14
X
X
X
X
X
ACE1202VM8
X
X
X
X
X
X
ACE1202VM8X
X
X
X
X
X
X
ACE1202VM
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ACE1202VN
X
X
X
X
X
ACE1202VN14
X
X
X
X
ACE1202BM8
X
X
X
X
X
X
ACE1202BM8X
X
X
X
X
X
X
ACE1202BM
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ACE1202BN
X
X
X
X
X
ACE1202BN14
X
X
X
X
X
ACE1202BEM8
X
X
X
X
X
X
ACE1202BEM8X
X
X
X
X
X
X
ACE1202BEM
X
X
X
X
X
X
X
X
X
X
X
X
X
ACE1202BEN
X
X
X
X
X
X
X
X
X
X
X
ACE1202BVM8
X
X
X
X
X
X
ACE1202BVM8X
X
X
X
X
X
X
ACE1202BVM
X
X
X
X
X
X
X
X
ACE1202BVMX
X
X
X
X
X
ACE1202BVN
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ACE1202LM
X
X
X
X
X
X
ACE1202LMX
X
X
X
X
X
X
ACE1202LN
X
X
X
X
X
ACE1202LN14
X
X
X
X
X
ACE1202 Product Family Rev. B.1
X
X
ACE1202LM8X
35
X
X
ACE1202BEN14
X
X
X
ACE1202BEMX
X
X
X
ACE1202BMX
X
X
X
ACE1202VMX
X
X
X
ACE1202EM8
ACE1202LM8
14-pin
DIP
X
ACE1202N14
ACE1202BVN14
8-pin
DIP
Tape &
Reel
X
X
X
X
www.fairchildsemi.com
ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Ordering Information (ACE1202)
Part Number
Core Type
2
Max. #
I/Os
8
ACE12022M8
X
X
X
X
X
X
ACE12022M8X
X
X
X
X
X
X
ACE12022M
X
X
X
X
X
X
ACE12022MX
X
X
X
X
X
X
ACE12022N
X
X
X
X
X
ACE12022N14
X
X
X
X
X
ACE12022EM8
X
X
X
X
0
1
Program
Memory Size
1K
2K
Operating Voltage
Range
1.8 – 2.2 – 2.7 –
5.5V 5.5V 5.5V
Temperature Range
0 to
70°C
-40 to -40 to
+85C +125°C
Package
8-pin
SOIC
14-pin
SOIC
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ACE12022EMX
X
X
X
X
X
X
ACE12022EN
X
X
X
X
X
ACE12022EN14
X
X
X
X
X
ACE12022VM8
X
X
X
X
X
X
X
X
X
X
X
ACE12022VM8X
X
X
X
X
X
ACE12022VM
X
X
X
X
X
X
ACE12022VMX
X
X
X
X
X
X
ACE12022VN
X
X
X
X
X
ACE12022VN14
X
X
X
X
ACE12022BM8
X
X
X
X
X
X
X
X
X
X
X
ACE12022BM8X
X
X
X
X
X
ACE12022BM
X
X
X
X
X
X
ACE12022BMX
X
X
X
X
X
X
ACE12022BN
X
X
X
X
X
ACE12022BN14
X
X
X
X
X
ACE12022BEM8
X
X
X
X
X
X
X
X
X
X
X
ACE12022BEM8X
X
X
X
X
X
ACE12022BEM
X
X
X
X
X
X
ACE12022BEMX
X
X
X
X
X
X
ACE12022BEN
X
X
X
X
X
ACE12022BEN14
X
X
X
X
X
ACE12022BVM8
X
X
X
X
X
X
X
X
X
X
X
ACE12022BVM8X
X
X
X
X
X
ACE12022BVM
X
X
X
X
X
X
ACE12022BVMX
X
X
X
X
X
X
ACE12022BVN
X
X
X
X
X
ACE12022BVN14
X
X
X
X
X
ACE1202 Product Family Rev. B.1
X
X
ACE12022EM
X
14-pin
DIP
X
ACE12022EM8X
36
8-pin
DIP
Tape &
Reel
X
X
X
X
www.fairchildsemi.com
ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Ordering Information (ACE1202-2)
0.189 - 0.197
(4.800 - 5.004)
8 7 6 5
0.228 - 0.244
(5.791 - 6.198)
1 2 3 4
Lead #1
IDENT
0.010 - 0.020
x 45¡
(0.254 - 0.508)
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.150 - 0.157
(3.810 - 3.988)
0.053 - 0.069
(1.346 - 1.753)
8¡ Max, Typ.
All leads
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.004
(0.102)
All lead tips
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.014 - 0.020 Typ.
(0.356 - 0.508)
0.050
(1.270)
Typ
Molded Small Out-Line Package (M8)
Order Number ACE1202(12022, 1202L)M8/ACE1202(12022)EM8/ACE1202VM8
ACE1202(12022)BM8/ACE1202(12022)BEM8/ACE1202(12022)BVM8
Package Number M08A
0.373 - 0.400
(9.474 - 10.16)
0.090
(2.286)
8
0.092
DIA
(2.337)
7
6
0.250 - 0.005
(6.35 ± 0.127)
+
Pin #1 IDENT
8
0.032 ± 0.005
(0.813 ± 0.127)
RAD
5
Pin #1
IDENT
1
Option 1
1
0.280 MIN
(7.112)
0.300 - 0.320
(7.62 - 8.128)
7
2
3
0.040 Typ.
(1.016)
0.030
MAX
(0.762)
20° ± 1°
4
Option 2
0.145 - 0.200
0.039
(0.991)
(3.683 - 5.080)
0.130 ± 0.005
(3.302 ± 0.127)
95° ± 5°
0.009 - 0.015
(0.229 - 0.381)
+0.040
0.325 -0.015
+1.016
8.255 -0.381
0.125
(3.175)
DIA
NOM
0.125 - 0.140
(3.175 - 3.556)
0.065
(1.651)
90° ± 4°
Typ
0.018 ± 0.003
0.020
(0.508)
Min
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.045 ± 0.015
(1.143 ± 0.381)
0.060
(1.524)
0.050
(1.270)
8-Pin DIP (N)
Order Number ACE1202(12022, 1202L)N/ACE1202(12022)EN/ACE1202VN
ACE1202(12022)BN/ACE1202(12022)BEN/ACE1202(12022)BVN
Package Number N08A
37
ACE1202 Product Family Rev. B.1
www.fairchildsemi.com
ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Physical Dimensions inches (millimeters) unless otherwise noted
0.335 - 0.344
(8.509 - 8.788)
14 13 12 11 10 9
8
0.228 - 0.244
(5.791 - 6.198)
0.010
Max.
(0.254)
1
2
3
Lead #1
IDENT
0.010 - 0.020
x 45°
(0.254 - 0.508)
0.008 - 0.010
(0.203 - 0.254)
Typ. all leads
0.150 - 0.157
(3.810 - 3.988)
8° Max, Typ.
All leads
0.04
(0.102)
All lead tips
4
5
6
7
30° Typ.
0.053 - 0.069
(1.346 - 1.753)
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020 Typ.
(0.356 - 0.508)
0.008
Typ
(0.203)
Molded Small Out-Line Package (M)
Order Number ACE1202(12022, 1202L)M/ACE1202(12022)EM/ACE1202VM
ACE1202(12022)BM/ACE1202(12022)BEM/ACE1202(12022)BVM
Package Number M14A
14-Pin DIP (N14)
Order Number ACE1202(12022, 1202L)N14/ACE1202(12022)EN14/ACE1202VN14
ACE1202(12022)BN14/ACE1202(12022)BEN14/ACE1202(12022)BVN14
Package Number N14A
38
ACE1202 Product Family Rev. B.1
www.fairchildsemi.com
ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Physical Dimensions inches (millimeters) unless otherwise noted
ACEx Emulator Kit: Fairchild also offers a low cost real-time incircuit emulator kit that includes:
General Information
Emulator board
Fairchild Semiconductor offers different possibilities to evaluate
and emulate software written for ACEx.
Emulator software
ACEx Starter Kit includes:
Power supply
Assembler and Manuals
Programmer Board
DIP14 target cable
Simulator Software
PC cable
Programmer Software
The ACEx emulator allows for debugging the program code in a
symbolic format. It is possible to place one breakpoint and watch
various data locations. It also has built-in programming capability.
Assembler and Manuals
Cables and samples devices
Prototype Board Kits: Fairchild offer two solutions for the simplification of the breadboard operation so that ACEx Applications
can be quickly tested.
DIP programming sockets
Programmer board: Interfaces with a PC through a Windows
program using the serial communication port. This board is
intended for engineering prototype and can be used for small
volume production. Fairchild offers factory pre-programming and
serialization (for justified quantities) for a small additional cost.
Please refer to your local distributor for details regarding factory
programming.
1) ACEDEMO is can be used for general purpose applications
2) ACETXRX for transmitting / receiving (RF, IR, RS232,
RS485) applications.
ACEDEMO has 8 switches, 8 LEDs, RS232 voltage translator,
buzzer, and a lamp with a small breadboard area.
Simulator: Is a Windows program able to load, assemble, and
debug ACEx programs. It is possible to place as many breakpoints
as needed, trace the program execution in symbolic format, and
program a device with the proper options. The ACEx Simulator is
available free-of-charge and can be downloaded from Fairchild’s
web site at www.fairchildsemi.com/products/memory/ace
Ordering P/Ns
Starter Kit:
ACESTART1101
ACESTART1202
Programming Adapters:
DIP8 - ACESDIP8
DIP14 - ACESDIP14
TSSOP8 - ACESTSSOP8
SO8 - ACESSOP8
SO14 - ACESSOP15
Emulator Kit: ACEICE (110Vac)
ACEICE_EU (220Vac)
Prototype Boards:
ACEDEMO
ACETXRX (specify RF freq. 433 or 315MHz)
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant
injury to the user.
Fairchild Semiconductor
Americas
Customer Response Center
Tel. 1-888-522-5372
2. A critical component is any component of a life support device
or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,
or to affect its safety or effectiveness.
Fairchild Semiconductor
Europe
Fax:
+44 (0) 1793-856858
Deutsch
Tel:
+49 (0) 8141-6102-0
English
Tel:
+44 (0) 1793-856856
Français
Tel:
+33 (0) 1-6930-3696
Italiano
Tel:
+39 (0) 2-249111-1
Fairchild Semiconductor
Hong Kong
8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
Fairchild Semiconductor
Japan Ltd.
4F, Natsume Bldg.
2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
39
ACE1202 Product Family Rev. B.1
www.fairchildsemi.com
ACE1202 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
ACEx Development Tools