FAIRCHILD TMC22052AKHC

www.fairchildsemi.com
TMC22x5yA
Multistandard Digital Video Decoder
Three-Line Adaptive Comb Decoder Family, 8 & 10 bit
Features
Description
• Very high performance, low cost
• Adaptive comb-based decoding
• Multiple pin-compatible versions
- 3-line, 2-line, and band-split
- 8- and 10-bit processing
• Internal digital linestores
• Supports NTSC/PAL field and NTSC frame based
decoding
• Multiple input formats
- CCIR-601/624 (D1), D2, CVBS, YC
• Multiple output formats
- CCIR-601/624 (D1), RGB, YCBCR
• 10-18 Mpps data rate
• Parallel and serial control interface
• Single +5V power supply
The TMC22x5yA family of Digital Video Decoders offers
unprecedented, broadcast-quality video processing performance in a single chip. It accepts line-locked or subcarrierlocked composite, YC, or D1 digital video and produces digital components in a variety of formats.
Applications
Related Products
• Studio television equipment
• Personal computer video input
• MPEG and JPEG compression inputs
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An internal three-line adaptive comb decoder structure produces optimal picture quality with a wide range of source
material. NTSC/PAL field and NTSC frame based decoding
is supported with external memory. Full comb programmability allows the user to tailor the decoder’s response to a
particular systems goals.
A family of products offers 3-line, 2-line, and simple decoders in 8-bit and 10-bit versions—all in a pin and softwarecompatible format. Serial and parallel control ports are provided. These submicron CMOS devices are packaged in a
100-lead Metric Quad Flat Pack (MQFP).
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TMC2192 10 bit video encoder
TMC2072 Enhanced Genlocking Video Digitizer
Block Diagram
BUFFER
MASTER1-0
Y/C Split0
VIDEOA9-0
Input
Processor
Linestore1
Y/C Split1
VIDEOB9-0
Linestore2
CLOCK
LDV
HSYNC
VSYNC
Adaptive
Comb
Filter
G/Y9-0
Chroma
Demod
Output
Processor
R/Cr9-0
Burst
Locked
Loop
Comb
Fail
Y/C Split2
B/Cb9-0
FID2-0
DREF
DHSYNC
DVSYNC
Internal
Sync Pulse
Generator
Global Control
Parallel Control
A1-0
R/W
CS
D 7-0
SET
RESET
SER
Serial Control
SA2-0
SDA
SCL
65-22x5y-01
REV. 1.0.0 2/4/03
TMC22x5yA
PRODUCT SPECIFICATION
Table of Contents
Features ......................................................................1
Applications ...............................................................1
Description .................................................................1
Block Diagram ............................................................1
Contents .....................................................................2
List of Tables and Figures ........................................3
General Description ...................................................4
Input Processor...............................................................4
Adaptive Comb Filter.....................................................4
Output Processor ............................................................5
Parallel and Serial Microprocessor Interfaces................5
Pin Assignments ........................................................5
Pin Descriptions.........................................................6
Control Register Map.................................................8
Control Register Definitions ...................................11
Decoder Introduction...............................................40
YC Separation ..............................................................40
Comb Filter Architecture for YC Separation ...............41
YC Line-Based Comb Filters.......................................42
D1 Line-Based Comb Filters .......................................42
NTSC Frame and Field Based Decoders ...............42
Composite Frame-Based Comb Filters ........................42
Composite Field-Based Comb Filters ..........................42
PAL Field Comb Decoders ......................................42
Composite PAL Field Comb Filters.............................42
The TMC22x5yA Comb Filter Architecture ............43
TMC22x5yA Functional Description.......................44
Input Processor.............................................................44
Bandsplit Filter (BSF) ..................................................44
Comb Filter Input.........................................................45
Adaptive Comb Filter...................................................47
Comb Fails................................................................49
Comb Fail Detection ....................................................49
Generation of the Comb Fail Signals .....................50
Luma Error Signals ......................................................50
Hue and Saturation Error Signals.................................50
Picture Correlation .......................................................50
Adapting the Comb Filter ............................................50
XLUT ...........................................................................51
Digital Burst Locked Loop ..........................................53
Color Kill Counter .......................................................53
PAL Color Frame Bit ...................................................55
Hue Control..................................................................55
System Monitoring of the Burst Loop Error ................55
2
Clamp Circuit .............................................................. 55
Pedestal Removal ........................................................ 55
Clamp Generator ......................................................... 55
Luma Notch Filter ....................................................... 56
Matrix .......................................................................... 56
Programmable U Scalar............................................... 56
Programmable V Scalar............................................... 56
Programmable Y Scalar............................................... 56
Programmable MS Scalar............................................ 56
Fixed (B-Y) and (R-Y) Scalars ................................... 56
Y Offset ....................................................................... 57
Matrix Limiters............................................................ 57
Examples of Output Matrix Operation ........................ 57
Simple Luma Color Correction ................................... 58
CBCR MSB Inversion ................................................. 58
Output Rounding ......................................................... 58
Output Formats............................................................ 58
Decimating CBCR Data............................................... 58
Multiplexed YCBCR Output (TRS Words Inserted)... 58
YC Outputs.................................................................. 58
The LDV Clock ........................................................... 58
Sync Pulse Generator ............................................. 59
Internal Field and Line Numbering Scheme ............... 59
Timing Parameters .................................................. 61
Subcarrier Programming ............................................. 61
Horizontal Timing ....................................................... 61
Horizontal and Vertical Timing Parameters................ 61
Vertical Blanking ........................................................ 62
VINDO Operation ....................................................... 65
Video Measurement................................................. 65
Pixel Grab.................................................................... 65
Composite Line Grab .................................................. 67
Parallel Microprocessor Interface ............................... 67
Serial Control Port (R-Bus)......................................... 68
Equivalent Circuits and Threshold Levels ............ 71
Absolute Maximum Ratings.................................... 72
Operating Conditions .............................................. 73
Electrical Characteristics........................................ 75
Switching Characteristics....................................... 76
System Performance Characteristics .................... 76
Programming Examples.......................................... 77
Programming Worksheet ........................................ 81
Related Products ..................................................... 82
Ordering Information ............................................... 84
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
List of Tables and Figures
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
TMC22x5yA Decoder Family ................. 4
Normalized Subcarrier Frequency
as a Function of Pixel Data Rates....... 45
Comb Filter Architecture ..................... 48
Simple Example of an Adaptive
Comb Filter Architecture ..................... 48
Adaption Modes ................................... 51
XLUT Input Selection ........................... 52
XLUT Output Function ......................... 52
XLUT Special Function Definitions..... 52
PAL-B,G,H,I Bruch
Blanking Sequence .............................. 53
PAL-M Bruch Blanking Sequence ...... 54
Blanking Level Selection ..................... 55
Adaptive Notch Threshold Control..... 55
Matrix Limiters...................................... 57
Output Format ...................................... 58
NTSC Field and Line Numbering ........ 59
PAL B,G,H,I Field and
Line Numbering .................................... 59
PAL M Field and Line Numbering ....... 59
Vertical Blanking Period ...................... 60
Vertical Burst Blanking Period............ 60
Table of Line Idents, LID[4:0] .............. 60
Timing Offsets ...................................... 61
PAL VINDO operation .......................... 63
Pixel Grab Control................................ 66
Parallel Port Control............................. 67
Serial Port Addresses .......................... 69
Figure 1.
Figure 2.
Figure 3.
Logic Symbol.......................................... 4
Pixel Data Format ................................... 4
Fundamental Decoder
Block Diagram ...................................... 40
Figure 4. Comparison of the Frequency
Spectrum of NTSC and PAL
Composite Video Signals .................... 40
Figure 5. Examples of Notch and Bandpass
Filters..................................................... 41
Figure 6. ............................................................... 41
Figure 7. Chrominance Vector Rotation in
PAL and NTSC ...................................... 42
Figure 8. Chrominance Vector Rotation Over
4 Fields in NTSC ................................... 42
Figure 9. Chrominance Vector Rotation Over
4 Fields in PAL...................................... 42
Figure 10. TMC22x5yA Line Based Comb
Filter Architecture ................................ 43
REV. 1.0.0 2/4/03
Figure 11. Input Processor .................................... 44
Figure 12. Complementary Bandsplit Filter ......... 44
Figure 13. Bandsplit Filter, Full Frequency
Response .............................................. 45
Figure 14. Bandsplit Filter, Passband
Response .............................................. 45
Figure 15. Block Diagram of Comb Filter Input ... 46
Figure 16. Signal Flow Around the Adaptive
Comb Filter ........................................... 47
Figure 17. Example of a Comb Fail Using a NTSC
Two Line Comb Filter........................... 49
Figure 18. Generation of Upper and Lower Comb
Fail Signals ........................................... 50
Figure 19. Comb Filter Selection .......................... 51
Figure 20. XLUT Input Selection ........................... 52
Figure 21. Block Diagram of Digital Burst
Locked Loop ......................................... 53
Figure 22. Gaussian Low Pass Filters.................. 54
Figure 23. Gaussian LPF Passband Detail........... 54
Figure 24. Output Processor Block Diagram....... 55
Figure 25. Adaptive Notch Filters ......................... 56
Figure 26. Luminance Notch Filter ....................... 56
Figure 27. Horizontal Timing ................................. 61
Figure 28. External HSYNC and VSYNC Timing
for Field 1(3, 5, or 7) ............................. 62
Figure 29. NTSC Vertical Interval.......................... 62
Figure 30. PAL-B,G,H,I,N Vertical Interval............ 62
Figure 31. PAL-M Vertical Interval ........................ 63
Figure 32. Pixel Grab Locations............................ 64
Figure 33. Relationship Between Pixel Count
and Pixel Grab Value............................ 65
Figure 34. Microprocessor Parallel Port –
Write Timing.......................................... 66
Figure 35. Microprocessor Parallel Port –
Read Timing.......................................... 68
Figure 36. Serial Port Read/Write Timing............. 69
Figure 37. Serial Interface –
Typical Byte Transfer........................... 70
Figure 38. Equivalent Digital Input Circuit ........... 71
Figure 39. Equivalent Digital Output .................... 71
Figure 40. Threshold Levels for Three-state........ 71
Figure 41. Input Timing Parameters ..................... 72
Figure 42. Functional Block Diagram of the
TMC22x5yA G/Y, B/U, and R/V Output
Stage...................................................... 73
Figure 43. Output Timing Parameters .................. 74
3
TMC22x5yA
PRODUCT SPECIFICATION
General Description
The TMC22x5yA digital decoder can be used as a universal
input to digital video processing systems by decoding digital
composite video and transcoding digital component inputs
into a common data format.
The digital comb filter decoder implements one of sixteen
comb filter architectures to produce luminance and color difference component signals which are virtually free of the
cross-color and cross-luminance artifacts associated with
simple bandsplit filter decoders.
Table 1. TMC22x5yA Decoder Family
3
2
1
10-bit Data
✔
✔
✔
8-bit Data
✔
✔
D1 Interface
✔
Line-Locked Mode
✔
fSC-Locked Mode
3
2
1
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
Genlock Mode
✔
✔
✔
✔
✔
✔
NTSC Frame Comb
✔
✔
NTSC/PAL Field Comb ✔
✔
3-Line Comb
✔
✔
2-Line Comb
✔
✔
✔
✔
Line Grab
✔
✔
✔
✔
Pixel Grab
✔
✔
✔
✔
✔
CLOCK
LDV
HSYNC
VSYNC
MASTER
BUFFER
✔
D7-0
A1-0
G/Y9-0
B/CB9-0
R/CR9-0
TMC22x5yA
Multistandard
Digital
Video
Decoder
FID2-0
AVOUT
DHSYNC
DVSYNC
SER
SET
RESET
SA2-0
SDA
SCL
CS
R/W
65-22x5yA-02
Figure 1. Logic Symbol
The devices come in 8- and 10-bit resolution versions (see
Figure 2 for data alignment between 8- and 10-bit versions).
Within each resolution version there are three models, offering three-line adaptive comb filtering, two-line adaptive
4
The digitized video and clocks provided to the decoder can
be either locked to the line frequency or the subcarrier frequency of the digitized waveform, providing broadcast quality decoding from the NTSC square pixel rate of 12.27 MHz
to the PAL four times subcarrier pixel rate of 17.73 MHz.
LSB
VA8
VA9
VB9
VB8
G/Y9 G/Y8
B/CB9 B/CB 8
R/CR9 R/CR8
VA9
VA8
VB9
VB8
G/Y9 G/Y8
B/CB9 B/CB 8
R/CR9 R/CR8
•••
VA2
VA1
VA0
VB2
VB1
VB0
G/Y2 G/Y1 G/Y0 10 bit
B/CB2 B/CB1 B/CB0
R/CR2 R/CR1 R/CR0
•••
VA2
VB2
G/Y2
B/CB2
R/CR2
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
8 bit
Figure 2. Pixel Data Format
Because the cost/performance tradeoff varies among applications, the TMC22x5yA decoder has been developed as a
family of six parts. They are all assembled in the same
package, and fit the same footprint. The register maps are
identical.
VIDEOA9-0
VIDEOB9-0
Input Processor
MSB
TMC2215yA TMC2205yA
Function
comb filtering, and simple decoding. The TMC22153A
10-bit three-line comb filter can be programmed to emulate
any of the other parts. All prototyping can be performed with
this version to evaluate performance tradeoffs, and lowercost versions are easily substituted in production.
Inputs containing embedded GRS (Fairchild Video Input
Processors), TRS words (D1 multiplexed component signals), and TRS-ID words (deserialized D2 signals) can be
used to lock the internal horizontal and vertical state
machines to the embedded information. If this information is
not provided, external horizontal and vertical syncs are
required for all line-locked input formats, and are optional
for NTSC inputs locked to four times the subcarrier (4*Fsc).
A simple sync separator is provided for digitized inputs
locked to the subcarrier frequency: the internal sync separator locks to the mid point of syncs during the vertical field
group, then flywheels during the active portion of the field.
For this reason, the DHSYNC and DVSYNC operations are
not guaranteed in subcarrier mode.
Adaptive Comb Filter
The line based adaptive comb filter in the TMC22x5yA adds
or subtracts the high frequency data from three adjacent field
lines to produce the average of the high frequency luminance
by canceling the chrominance signals, which in flat fields of
color are 180 degrees apart. Unfortunately flat fields of color
are rare and, when vertical transitions in the picture occur,
the output of the comb filter contains a mixture of both high
frequency luminance and chrominance, at which time the
comb fails. To avoid the comb filter artifacts that occur when
this happens, three sets of error signals are sent to a user-programmable lookup table, allowing the output of the comb filter to be mixed with the output of an internal bandsplit
decoder.
To produce these comb fail error signals, the video on each
of the inputs to the comb filter is passed through a simple
bandsplit decoder. The low-frequency portion of the signal is
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
assumed to be luminance and the high frequency portion is
processed as chrominance to find the magnitude and phase of
the chrominance vector. These three components are then
compared across the (0H & 1H) and (1H & 2H) taps of the
comb filter to produce the difference in luminance, chrominance magnitude, and chrominance phase. These differences
are then translated in the user-programmable lookup table to
produce the “K” signal which controls the complementary
mix between the output of the comb filter and the simple
bandsplit decoder. That is, the “K” signals controls how
much of the combed high frequency luminance signal is subtracted from the simple bandsplit chrominance for chroma
combs, or added to the low frequency output of the bandsplit
for luma comb filters.
Output Processor
The demodulated chrominance signal and the luminance
signal are passed through a programmable output matrix,
producing RGB, YUV, or YCBCR. When the clock is at
27MHz, a D1 signal can be produced on the R/V output with
the embedded TRS words fixed to the external HSYNC and
VSYNC timing.
Parallel and Serial Microprocessor Interfaces
The parallel microprocessor interface employs 12 pins, the
serial port uses 5. A single pin, SER, selects between the two
interface modes.
In parallel interface mode, one address line is decoded for
access to the internal control register and its pointer.
Controls are reached by loading a desired address through
the 8-bit D7-0 port, followed by the desired data (read or
write) for that address. The control register address pointer
auto-increments to address 3Fh and then remains there.
A 2-line serial interface may also be used for initialization
and control. The same set of registers accessed by the parallel port is available to the serial port. The device address in
the serial interface is selected via pins SA2-0.
The RESET pin sets all internal state machines to their initialized conditions and places the decoder in a power-down
mode. All register data are maintained while in power-down
mode.
Pin Assignments
100
81
1
80
30
51
31
50
65-22x5y-03
REV. 1.0.0 2/4/03
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Name
G/Y1
G/Y0
LDV
GND
VDD
B/Cb9
B/Cb8
B/Cb7
B/Cb6
B/Cb5
B/Cb4
B/Cb3
B/Cb2
B/Cb1
B/Cb0
GND
VDD
R/Cr9
R/Cr8
R/Cr7
R/Cr6
R/Cr5
R/Cr4
R/Cr3
R/Cr2
Pin
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Name
R/Cr1
R/Cr0
GND
VDD
DREF
FID0
FID1
FID2
DHSYNC
DVSYNC
D0
D1
D2
GND
VDD
D3
D4
D5
D6
D7
GND
VDD
HSYNC
VSYNC
BUFFER
Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Name
RESET
SET
SER
SA0
SA1
SA2
GND
SDA
SCL
CS
R/W
A0
A1
GND
VDD
VIDEOB0
VIDEOB1
VIDEOB2
VIDEOB3
VIDEOB4
VIDEOB5
VIDEOB6
VIDEOB7
VIDEOB8
VIDEOB9
Pin Name
76
GND
77
VIDEOA0
VIDEOA1
78
VIDEOA2
79
VIDEOA3
80
81
VIDEOA4
82
VIDEOA5
VIDEOA6
83
84
VIDEOA7
VIDEOA8
85
86
VIDEOA9
87
MASTER0
MASTER1
88
89
CLOCK
GND
90
91
VDD
GND
92
G/Y9
93
G/Y8
94
95
G/Y7
96
G/Y6
G/Y5
97
G/Y4
98
99
G/Y3
100 G/Y2
5
TMC22x5yA
PRODUCT SPECIFICATION
Pin Descriptions
Pin Name
Pin Number
Value
Pin Function Description
Inputs
VIDEOA9-0
86, 85, 84, 83,
82, 81, 80, 79,
78, 77
TTL
Video input A. An 8 or 10 bit data input to the input multiplexer.
For 8-bit versions (TMC2205yA) the data are left-justified (VIDEOA9-2).
VIDEOB9-0
75, 74, 73, 72,
71, 70, 69, 68,
67, 66
TTL
Video input B. An 8 or 10 bit data input to the input multiplexer.
For 8-bit versions (TMC2205yA) the data are left-justified (VIDEOB9-2).
VSYNC
49
TTL
Vertical sync input. A vertical sync signal (active low) occurring at the
start of the first vertical sync pulse in a vertical field group. A falling edge
of VSYNC which is coincident with a falling edge of HSYNC indicates
field 1. This signal is active only when SPGIP1-0 = 00.
HSYNC
48
TTL
Horizontal sync input. A horizontal sync signal (active low) occurring
at the falling edge of the video sync. This signal is active only when
SPGIP1-0 = 00.
88, 87
TTL
Master decoder control.
MASTER1-0
00
01
10
11
Adaptive comb decoder
Simple bandsplit decoder
Reserved
Flat notched luma and simple bandsplit chroma
BUFFER
50
TTL
Control register select. This signal switches between two sets of
registers which control the gain or hue values in the output matrix.
When BUFFER = 0, registers 17-1F are active. When BUFFER = 1,
registers 27-2F take control.
CLOCK
89
TTL
Master processing clock. The clock signal can either be at twice the
pixel data rate in the line locked modes, or at four times the subcarrier
frequency in the subcarrier mode. The interpretation of the CLOCK
signal is set by the CKSEL register bit.
SET
52
TTL
Programmable function pin. The function specified by the SET
register is active when SET is low. The decoder returns to its previous
operation when SET goes high.
G/Y9-0
93, 94, 95, 96,
97, 98, 99, 100,
1, 2
TTL
Green or Luminance digital output. For 8-bit versions (TMC2205yA)
the data are left-justified (G/Y9-2).
B/CB9-0
6, 7, 8, 9, 10,
11, 12, 13, 14,
15
TTL
Blue or CB digital output. For 8-bit versions (TMC2205y) the data are
left-justified (B/CB 9-2).
R/CR9-0
18, 19, 20, 21,
22, 23, 24, 25,
26, 27
TTL
Red or CR digital output. For 8-bit versions (TMC2205yA) the data are
left-justified (R/CR 9-2).
DVSYNC
35
TTL
Vertical sync output. The DVSYNC signal occurs once per field and
lasts for 1 video line.
DHSYNC
34
TTL
Horizontal sync output. The DHSYNC signal occurs once per line and
lasts for 64 clock periods.
LDV
3
TTL
Data synchronization output. LDV can be an internally or externally
generated clock signal. The internal LDV signal is produced when the
CLOCK input is at twice the pixel data rate (PXCK); and is a pixel data
rate clock phase locked to the falling edge of the HSYNC. The external
LDV can be selected under software control, and must be at the
CLOCK, or a sub multiple of the CLOCK, frequency.
Outputs
6
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Pin Descriptions (cont.)
Pin Name
Pin Number
Value
Pin Function Description
DREF
30
TTL
Decoder reference signal. This is a dual function pin, controlled by
register 24, that can function as an active video output indicator or
output as a clamp pulse. When set to the active video output function,
the DREF pin is HIGH during the video portion of each line and LOW
during the horizontal and vertical blanking levels. When set to output a
clamp pulse, the clamp pulse is controlled by register 24 and 25
allowing a user to program when a 0.5 µSec pulse is output relative to
HSYNC.
FID2-0
33, 32, 31
TTL
Field identification output. A 3 bit field ident from the DRS signal.
D7-0
45, 44, 43, 42,
41, 38, 37, 36
TTL
Parallel control port data I/O. All control parameters are loaded into
and read back over this 8 bit data port.
A1-0
63, 62
TTL
Parallel control port address inputs. These pins govern whether the
microprocessor interface selects a table/register address or reads/
writes table/register contents.
CS
60
TTL
Parallel control port chip select. When CS is high the microprocessor
interface port, D7-0, is set to HIGH impedance and ignored. When CS
is LOW, the microprocessor can read or write parameters over D7-0.
R/W
61
TTL
Parallel control port read/write control. When R/W and CS are LOW,
the microprocessor can write to the control registers or XLUT over
D7-0. When R/W is HIGH and CS is LOW, it can read the contents of
any selected XLUT address or control register over D7-0.
RESET
51
TTL
Chip master reset. Bringing RESET LOW sets the software reset
control bit, SRESET, LOW and disables the digital outputs. If HRESET
is LOW the decoder outputs remain disabled after RESET goes HIGH
until the SRESET bit is set high by the host. If HRESET is HIGH when
RESET goes HIGH the decoder the internal state machines are
enabled.
SER
53
TTL
Serial/parallel interface select. This pin will select between a parallel
(HIGH) or serial (LOW) interface port.
SDA
58
R-Bus
Serial data interface. Bi-directional serial interface to the control port.
SCL
59
R-Bus
Serial interface clock.
56, 55, 54
TTL
Serial Address. Three bits providing the lsbs of the serial chip ID used
to identify the decoder.
VDD
5, 17, 29, 40,
47, 65, 91
+5 V
Power Supply. Positive power supply for digital circuits, +5V.
GND
4, 16, 28, 39,
46, 57, 64, 76,
90, 92
0.0 V
Ground. Ground for digital circuits, 0V.
µP Interface
SA2-0
Power Supply
REV. 1.0.0 2/4/03
7
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Map
Reg
The TMC22x5yA is initialized and controlled by a set of
registers which determine the operating modes.
An external controller is employed to write and read the
Control Registers through either the 8-bit parallel or 2-line
serial interface port. The parallel port, D7-0, is governed by
pins CS, R/W, and A1-0. The serial port is controlled by SDA
and SCL.
Reg
Bit
Name
Function
Bit
Name
Luma Processor Control
06
7-6
06
5
ANEN
Adaptive notch enable
06
4
ANR
Adaptive notch rounding
06
3-2
ANT
Adaptive notch threshold
06
1
ANSEL
Adaptive notch select
06
0
NOTCH
reserved, set to zero
Notch enable
Comb Processor Control
Global Control
00
7
SRST
Software reset
07
7
LS1BY
Line store 1 bypass
00
6
HRST
Hardware reset
07
6
LS1IN
Line store 1 input
00
5-3
SET
SET pin function
07
5
LS2DLY
Line store 2 delay
00
2
DHVEN
Output H&V sync enable
07
4
SPLIT
Line store 2 data width
Selects video standard
07
3
BSFBY
Bandsplit filter bypass
07
2
BSFSEL
Bandsplit filter select
07
1
BSFMSB
Inverts msb of bandsplit
filter
07
0
GRSDLY
Delays input to GRS
decode by 1H
00
1-0
STD
Input Processor Control
01
7
reserved, set to zero
01
6
IPMUX
Input mux control
01
5
IP8B
8 bit input format
01
4
TDEN
TRS detect enable
01
3
TBLK
TRS blank enable
01
2
IPCMSB
Chroma input msb invert
01
1
ABMUX
AB mux control
09
7-4
PCKF
Clock rate
01
0
CKSEL
Input clock rate select
09
3-0
VSTD
Video standard
Mid-Sync Level
08
7-0
MIDS
Mid-sync level
Extended DRS
Burst Loop Control
Output Control
02
7
BLLRST
BLL auto. reset enable
0A
7
02
6
VIPEN
Video Input Processor
enable
0A
6-5
02
5-4
LOCK
Global lock mode
0A
4-3
MSEN
Mixed sync enable
02
3
BLM
BLL lock mode
0A
2
OPCMSB
Chroma output msb invert
02
2
KILD
Color kill disable
0A
1
YBAL
Luma color correction
02
1
DMODBY
Demod bypass
0A
0
BUREN
Output burst enable
02
0
CINT
CBCR interpolation enable
0B
7
FMT422
Enables CBCR output mux
0B
6
CDEC
CBCR decimation enable
0B
5
YUVT
Enables D1 output
0B
4-2
0B
1
DRSEN
DRS output enable
0B
0
DRSCK
DRS data rate
0C
7-6
ADAPT
Adaption mode
0C
5
YCES
YC input error signal
control
0C
4
YCSEL
luma/chroma comb filter
select
0C
3-0
COMB
Comb filter architecture
Chroma Processor Control
03
7-5
BLFS
Burst loop filter select
03
4
CCEN
Chroma coring enable
03
3-2
CCOR
Chroma coring threshold
03
1
GAUBY
Gaussian filter bypass
03
0
GAUSEL
Gaussian filter select
Burst Threshold
04
7-0
BTH
Burst threshold
Pedestal
05
8
Function
7-0
PED
OP8B
Output rounded to 8 bits
OPLMT
Output limit select
reserved, set to zero
Comb Filter Control
Pedestal level
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
Reg
Bit
Name
0D
7-6
CEST
0D
5
0D
TMC22x5yA
Function
Reg
Bit
Name
Chroma error signal
transform
1A
7-0
VG07-0
V gain, 8 lsbs
1B
7-6
YG09-8
Y gain, 2 msbs
CESG
Chroma error signal gain
1B
5-3
UG010-8
U gain, 3 msbs
4
YESG
Luma error signal gain
1B
2
0D
3
CESTBY
Chroma error signal
bypass
1B
1-0
VG09-8
V gain, 2 msbs
0D
2
XFEN
XLUT filter enable
1C
7-0
YOFF07-0
Y offset, 8 lsbs
0D
1
FAST
Adaption speed select
1D
7-3
0D
0
YWBY
Luma weighting bypass
1D
2
YOFF08
Y offset, msb
0E
7-6
XIP
XLUT input select
1D
1-0
SG07-0
Msync gain, 2 msbs
0E
5-4
XSF
XLUT special function
1E
7-1
SYSPH06-0
7 lsbs of phase
0E
3-2
YMUX
Y output select
1E
0
VAXISO
V axis flip
0E
1-0
CMUX
C output select
1F
7-0
SYSPH014-7
8 msbs of phase
0F
7
0F
6-5
0F
reserved, set to zero
CAT
Adaption Threshold
4
DCES
D1 CBCR error signal
0F
3-2
IPCF
Comb filter input select
0F
1
YCCOMP
YC or Composite input
select
0F
0
SYNC
Sync processor select
Sync Pulse Generator
Function
reserved, set to zero
reserved, set to zero
Normalized Subcarrier Frequency
20
7-4
FSC3-0
20
3-0
21
7-0
FSC11-4
Lower 8 bits of fSC
22
7-0
FSC19-12
Middle 8 bits of fSC
23
7-0
FSC27-20
Top 8 bits of fSC
Bottom 4 bits of fSC
reserved, set to zero
Clamp Control
24
7
DRFSEL
Clamp pulse enable
PFLTBY
Phase filter enable
10
7-0
STS7-0
Sync to sync 8 lsbs
24
6
11
7-0
STB
Sync to burst
24
5-4
CLPSEL1-0
Int. clamp selection
3
VCLPEN
Clamp bypass
12
7-0
BTV
Burst to video
24
13
7-0
AV7-0
Active video line 8 lsbs
24
2-0
BAND2-0
Clamp offset
14
7-6
reserved, set to zero
25
7-0
CPDLY7-0
Clamp pulse delay
14
5-4
14
3
AV9-8
Output Format Control
Active video line 2 msbs
reserved, set to zero
26
7-6
Sync to sync 3 msbs
26
5
LDVIO
LDV clock select
reserved, set to zero
26
4
OPCKS
Output clock select
VINDO
Number of lines in vertical
window
26
3
DPCEN
DPC enable
26
2-0
DPC
Decoder product code
14
2-0
STS10-8
15
7
15
6-2
15
1
VDIV
Action inside VINDO
15
0
VDOV
Action outside VINDO
16
7-6
16
5-4
16
16
reserved, set to zero
Buffered register set 1
Active when BUFFER pin set HIGH
reserved, set to zero
27
7-0
SG17-0
Msync gain, 8 lsbs
NFDLY
new field detect delay
28
7-0
YG17-0
Y gain, 8 lsbs
3-2
SPGIP
SPG input select
29
7-0
UG17-0
U gain, 8 lsbs
1-0
MSIP
Mixed sync separator input
select
2A
7-0
VG17-0
V gain, 8 lsbs
2B
7-6
YG19-8
Y gain, 2 msbs
2B
5-3
UG110-8
U gain, 3 msbs
2B
2
2B
1-0
VG19-8
V gain, 2 msbs
2C
7-0
YOFF17-0
Y offset, 8 lsbs
2D
7-3
Buffered register set 0
Active when BUFFER pin set LOW
17
7-0
SG07-0
Msync gain, 8 lsbs
18
7-0
YG07-0
Y gain, 8 lsbs
19
7-0
UG07-0
U gain, 8 lsbs
REV. 1.0.0 2/4/03
reserved, set to zero
reserved, set to zero
9
TMC22x5yA
Reg
Bit
2D
2
PRODUCT SPECIFICATION
Name
Function
YOFF18
Y offset, msb
Reg
Bit
Name
Function
Status - Read Only
2D
1-0
SG17-0
Msync gain, 2 msbs
40
7-0
DDSPH
DDS phase, 8 msbs
2E
7-1
SYSPH16-0
7 lsbs of phase
41
7
LINEST
Pixel count reset
2E
0
VAXIS1
V axis flip
41
6
BGST
Start of burst gate
2F
7-0
SYSPH114-7
8 msbs of phase
41
5
VACT2
Half line flag
41
4
PALODD
PAL Ident
Video Measurement
30
7
set to zero
41
3
VFLY
Vertical count reset
30
6
LGF
Line grab flag
41
2
FGRAB
Field grab
30
5
LGEN
Line grab enable
41
1
LGRAB
Line grab
30
4
LGEXT
Ext line grab enable
41
0
PGRAB
Pixel grab
30
3
reserved, set to zero
42
7
FLD
Field flag (F in D1 output)
30
2
PGG
Pixel grab gate
42
6
VBLK
30
1
PGEN
Pixel grab enable
Vertical blanking (V in D1
output)
30
0
PGEXT
Ext pixel grab enable
42
5
HBLK
31
7-0
PG7-0
Pixel grab, 8 lsbs
Horizontal blanking (H in
D1 output)
32
7-0
LG7-0
Line grab, 8 lsbs
42
4-0
LID
Line identification
33
7
43
7
YGO
Y/G overflow
33
6-4
FG
Field grab number
43
6
YGU
Y/G underflow
33
3
LG8
Msb of line grab
43
5
UBO
CB/B overflow
33
2-0
PG10-8
Pixel grab, 3 msbs
43
4
UBU
CB/B underflow
34
7-0
GY9-2
G/Y grab, 8 msbs
43
3
VRO
CR/R overflow
35
7-0
BU9-2
B/U grab, 8 msbs
43
2
VRU
CR/R underflow
36
7-0
RV9-2
R/V grab, 8 msbs
43
1-0
37
7-6
44
7
MONO
Color kill active
37
5-4
GY1-0
G/Y grab, 2 lsbs
44
6-0
FPERR
Frequency/Phase error
37
3-2
BU1-0
B/U grab, 2 lsbs
45
7-0
DRS
DRS signal
37
1-0
RV1-0
R/V grab, 2 lsbs
38
7-0
Y9-2
Luma grab, 8 msbs
39
7-0
M9-2
3A
7-0
3B
reserved, set to zero
reserved
reserved
46
7-0
PARTID
Reads back xxh
47
7-0
REVID
Revision number
Msync grab, 8 msbs
484A
7-0
U9-2
U grab, 8 msbs
4B
7
PKILL
Phase kill from comb fail
7-0
V9-2
V grab, 8 msbs
4B
6-5
CFSTAT
Comb filter status
3C
7-6
Y1-0
Luma grab, 2 lsbs
4B
4-0
XOP
XLUT output
3C
5-4
M1-0
Msync grab, 2 lsbs
3-2
U1-0
U grab, 2 lsbs
4CFF
7-0
3C
3C
1-0
V1-0
V grab, 2 lsbs
Test Control
3D
7-0
TEST
Must be set to zero
3E
7-0
TEST
Must be set to zero
reserved
reserved
Notes:
1. Functions are listed in the order of reading and writing.
2. For each register listed above up to register 3F, all bits not
specified are reserved and must be set to zero to ensure
proper operation.
Vertical Blanking Control
3F
7
VBIT20
V bit control
3F
6
PEDDIS
Pedestal control
3F
5-0
CCDEN5-0
Closed caption control
Auto-increment stops at 3F
10
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions
Global Control Register (00)
7
6
SRST
HRST
5
4
3
SET
2
DHVEN
1
0
STD
Reg
Bit
Name
Description
00
7
SRST
Software reset. When LOW, resets and holds internal state machines and
disables outputs. When HIGH (normal), starts and runs state machines and
enables outputs. This bit is ignored while HRST is high.
00
6
HRST
Hardware reset. When HRST is HIGH, SRST is forced low when RESET pin
is taken LOW. State machines are reset and held. When HRST is low the
RESET pin can be taken HIGH at any time. The state machines remain
disabled until SRST is programmed HIGH. When HRST is high the state
machines are enabled as soon as the RESET pin goes HIGH.
00
5-3
SET
SET pin function. These bits control the set function when the SET pin goes
low.
A = all outputs high-impedance
B = internal state machines
C = burst locked loop
SET
Function
000
Reset and hold A, B, & C.
001
Set output to BLUE and flywheel B & C. (RGB outputs)
Set output to "color" and flywheel B & C (YCBCR outputs)
010
Hold A, lock B & C to external input
011
Reset C only
100
Reset B & C
101
Set output to BLUE and lock B & C to input video (RGB output)
110
Line and pixel grab depending on VMCR6-0 (reg 30)
111
Toggle reset function of SET = 010. For each SET = 0 pulse the
chip operation will change from normal to that of SET = 010 or
visa versa.
The first SET pulse after a software or hardware reset, with SET = 111,
causes a toggle to SET = 010.
00
2
DHVEN
Output H&V sync enable. Disables DHSYNC and DVSYNC signals when
HIGH.
00
1-0
STD
Selects video standard. Selects video standard.
REV. 1.0.0 2/4/03
SET
Function
00
NTSC
01
reserved
10
PAL/M
11
All PAL standards except PAL/M
11
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Input Processor Control (01)
7
6
5
4
3
2
1
0
Reserved
IPMUX
IP8B
TDEN
TBLK
IPCMSB
ABMUX
CKSEL
Reg
Bit
Name
Description
01
7
Reserved
Reserved, set to zero.
01
6
IPMUX
Input mux control. Used to select the Video Input Processor, D1, or D2 data
as the VA input to the input processor.
VIDEOA is selected for VA and VIDEOB is selected for VB when IPMUX is
set LOW. VIDEOB is selected for VA and VIDEOA for VB when IPMUX is set
HIGH. For YC inputs, the luma data must be passed through the VA input and
chroma through the VB input.
IPMUX should be set LOW for line locked composite inputs.
01
5
IP8B
8 bit input format. Bottom two bits of inputs VIDEOA9-0 and VIDEOB9-0 are
set to zero when HIGH.
01
4
TDEN
TRS detect enable. When HIGH, the TRS words embedded in incoming
video are used to reset the horizontal and vertical state machines. When LOW
the externally provided or internally generated HSYNC and VSYNC are used
to reset the horizontal and vertical state machines.
01
3
TBLK
TRS blank enable. Blanks the TRS and AUX data words when HIGH. For line
locked and D1 data, the TRS and AUX data words are set to the luma and
chroma blanking levels as appropriate. For D2 (4*fSC) data, the TRS and
AUX data words are set to the sync tip level.
01
2
IPCMSB
Chroma input msb invert. The msb of the chroma or CBCR data are inverted
when HIGH.
01
1
ABMUX
AB mux control. Selects the primary and secondary inputs to the decoder
from the DA and DB outputs of the input processor. When ABMUX is LOW,
DA is selected as the primary and DB as the secondary decoder input.
01
0
CKSEL
Input clock rate select. Set HIGH for line locked clocks and LOW for
subcarrier locked clocks. Line locked clocks should be at twice the pixel data
rate, and the subcarrier clock should be at four times the subcarrier
frequency.
12
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Burst Loop Control (02)
7
6
BLLRST
VIPEN
5
4
LOCK
3
2
1
0
BLM
KILD
DMODBY
CINT
Reg
Bit
Name
Description
02
7
BLLRST
BLL reset enable. When LOW, the automatic BLL reset is disabled. When
HIGH, the BLL will be reset if the BLL loses lock and fails to reacquire lock
within 8 fields.
02
6
VIPEN
Video Input Processor enable. Selects interface protocol for Fairchild video
input devices. Active only when LOCK1-0 = 10.
VIPEN Function
02
5-4
LOCK
0
Video Input Processor Interface
1
TMC22071 Interface
Global Lock mode. Sets the decoder locking mode.
LOCK
02
3
BLM
Function
00
Line Locked Mode
01
Subcarrier Locked Mode
10
Video Input Processor Mode
11
D1 Mode
BLL lock mode. Sets the decoder burst locking mode.
BLM
Function
0
Frequency Lock
1
Phase Lock
02
2
KILD
Color kill disable. Color killer is disabled when HIGH.
02
1
DMODBY
Demod bypass. Chroma data bypasses the demodulator when HIGH.
02
0
CINT
CBCR interpolation enable. Interpolation of CBCR input data from 0:2:2 to
0:4:4 is enabled when HIGH.
REV. 1.0.0 2/4/03
13
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Chroma Processor Control (03)
7
6
5
4
BLFS
3
CCEN
2
CCOR
Reg
Bit
Name
Description
03
7-5
BLFS
Burst loop filter select.
BLFS fS (Mpps)
1
0
GAUBY
GAUSEL
Recommended Criteria
000
13.5
PAL, Line-Locked YC
000
15
PAL, Line-Locked YC
001
12.27
NTSC, Line-Locked YC
001
13.5
PAL, Line-Locked Composite
010
13.5
NTSC, Line-Locked YC
010
15
PAL, Line-Locked Composite
011
14.32
NTSC, Subcarrier-Locked YC
011
17.73
PAL, Subcarrier-Locked Composite
100
17.73
PAL, Subcarrier-Locked YC
101
13.5
NTSC, Line-Locked Composite
110
12.27
NTSC, Line-Locked Composite
111
14.32
NTSC, Subcarrier-Locked Composite
03
4
CCEN
Chroma coring enable. Enables Chroma Coring when HIGH.
03
3-2
CCOR
Chroma coring threshold. Sets the Chroma Coring threshold.
CCOR
Function
00
1 lsb
01
2 lsb
10
3 lsb
11
4 lsb
03
1
GAUBY
Gaussian filter bypass. The chroma data bypasses the Gaussian LPF when
HIGH.
03
0
GAUSEL
Gaussian LPF select. Selects the Gaussian filter response to be used on the
demodulated chrominance.
GAUSEL
Function
0
Select Gaussian LPF resp. 2
1
Select Gaussian LPF resp. 1
See Figure 22 for filter responses.
14
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Burst Threshold (04)
7
6
5
4
3
2
1
0
BTH
Reg
Bit
Name
Description
04
7-0
BTH
Burst threshold. The 8 bit value to be compared against the demodulated
U and V component data. If over 127 lines occur in a field in which the burst
is below this threshold, then the color is set to chroma black for the next field.
Pedestal (05)
7
6
5
4
3
2
1
0
PED
Reg
Bit
Name
Description
05
7-0
PED
Pedestal level. An 8 bit magnitude subtracted from the luma data to remove
the setup before processing by the output matrix.
Luma Processor Control (06)
7
6
Reserved
5
4
ANEN
ANR
3
2
ANT
1
0
YSEL
NOTCH
Reg
Bit
Name
Description
06
7-6
Reserved
Reserved, set to zero.
06
5
ANEN
Adaptive notch enable. Enables adaptive notch when HIGH.
06
4
ANR
Adaptive notch rounding. Sets adaptive notch rounding point.
ANR
06
3-2
ANT
0
Round to 10 bits
1
Round to 8 bits
Adaptive notch threshold level. Sets the adaptive notch threshold.
ANT
06
1
YSEL
0
REV. 1.0.0 2/4/03
NOTCH
Function
00
Magnitude difference less than 32
01
Magnitude difference less than 24
10
Magnitude difference less than 16
11
Magnitude difference less than 8
Adaptive notch select. Selects adaptive notch filter response.
YSEL
06
Function
Function
0
Adaptive notch response ANF1
1
Adaptive notch response ANF2
Notch enable. Adaptive notch filter ANF3 selected when HIGH and ANEN is
HIGH, non-adaptive notch filter selected when HIGH and ANEN is LOW.
Function may be overridden by XSF (Reg 0E, bits 5-4).
15
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Comb Processor Control (07)
7
6
5
4
3
2
1
0
LS1BY
LS1IN
LS2DLY
SPLIT
BSFBY
BSFSEL
BSFMSB
GRSDLY
Reg
Bit
Name
Description
07
7
LS1BY
Line store 1 bypass. Bypasses linestore 1 when HIGH.
07
6
LS1IN
Line store 1 input. Selects the input of linestore 1:
LS1IN
Function
0
Primary Input
1
Secondary Input
07
5
LS2DLY
Line store 2 delay. LSTORE2 uses STS to store 1H when LOW and uses
VL to store SAV to EAV (or max count) when HIGH.
07
4
SPLIT
Line store 2 delay. Splits data through LSTORE2, 9 bits chroma and 7 bits
luma when HIGH (chroma combs) and 8 bits chroma and 8 bits luma when
LOW (luma comb).
07
3
BSFBY
Bandsplit filter bypass. Bandsplit filter is bypassed when HIGH.
07
2
BSFSEL
Bandsplit filter select. Selects the bandsplit filter to be used:
BSFSEL
Function
0
Select bandsplit filter response 1
1
Select bandsplit filter response 2
07
1
BSFMSB
Inverts msb of bandsplit filter. When HIGH, inverts the msb of the input to
the bandsplit filter.
07
0
GRSDLY
Delays input to GRS decode. When HIGH, delays the input to the GRS
extraction circuit by 1H. Genlock only.
Mid-Sync Level (08)
7
6
5
4
3
2
1
0
MIDS
Reg
Bit
Name
Description
08
7-0
MIDS
Mid sync level. Sets the mid point of syncs for the mixed sync separator, in
the subcarrier locked mode.
16
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Extended DRS (09)
7
6
5
4
3
2
PCKF
Bit
Name
Description
09
7-4
PCKF
Clock rate.
PCKF
3-0
VSTD
Function
0000
13.50 MHz
0001
reserved
0010
reserved
0011
reserved
0100
14.32 MHz
0101
17.73 MHz
0110
reserved
0111
reserved
1000
12.27 MHz
1001
14.75 MHz
1010
15.00 MHz
1011
reserved
1100
reserved
1101
reserved
1110
reserved
1111
reserved
Video Standard. Selects the video standard.
VSTD
REV. 1.0.0 2/4/03
0
VSTD
Reg
09
1
Function
0000
NTSC-M
0001
NTSC-EIAJ
0010
reserved
0011
reserved
0100
reserved
0101
reserved
0110
reserved
0111
reserved
1000
PAL-B, G, H, I
1001
PAL-M
1010
PAL-N (Argentina, Paraguay, Uruguay)
1011
PAL-N (Jamaica)
1100
reserved
1101
reserved
1110
reserved
1111
reserved
17
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Output Control (0A)
7
6
5
4
OP8B
OPLMT
OPLMT
3
MSEN
2
1
0
OPCMSB
YBAL
BUREN
Reg
Bit
Name
Description
0A
7
OP8B
Output rounded to 8 bits. Rounds the outputs to 8 bits when HIGH. The two
lsbs are set to zero.
0A
6-5
OPLMT
Output limit select. Sets the output format and limiters:
OPLMT
0A
4-3
MSEN
Function
00
RGB output format
limited to 4 to 1016
01
YCBCR output format
Y limited to 4 to 1016
CBCR limited to ±504
10
RGB output format
limited to 4 to 1016
11
YCBCR output format
Y limited to 64 to 940
CBCR limited to ±448
Mixed sync enable. Sets composite sync output format:
MSEN
Function
00
No sync, & “super blacks” disabled
01
No sync, & “super blacks” disabled
10
Sync on G/Y output only, & “super blacks” enabled
11
Sync on RGB outputs, & “super blacks” enabled
0A
2
OPCMSB
Chroma output msb invert. Inverts the msb of the CBCR or Chroma output
when HIGH.
0A
1
YBAL
Luma color correction. Setting this bit HIGH forces the chroma to zero
whenever the luma equals or exceeds the luma limit.
0A
0
BUREN
Output burst enable. When HIGH, passes the burst through on the chroma
channel. Sets the burst region to zero when LOW.
Notes:
1. To enable “super blacks” and disable syncs of the output simply set MSEN[1] HIGH and the sync gain to zero.
18
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Output Control (0B)
7
6
5
4
FMT422
CDEC
YUVT
3
2
Reserved
1
0
DRSEN
DRSCK
Reg
Bit
Name
Description
0B
7
FMT422
Enables CBCR output mux. When HIGH, multiplexes the CB and CR data
onto the same data bus. The chroma or multiplexed CBCR output appears on
the B/CB output. The R/CR output is forced low.
0B
6
CDEC
CBCR decimation enable. When HIGH, the CBCR data are decimated to
0:2:2 in the output processor.
0B
5
YUVT
Enables D1 output. When HIGH, enables 4:2:2 multiplexed YCBCR onto the
R/CR data output with TRS words inserted into the output data stream. The Y
data are still available on the G/Y output and multiplexed CBCR is available on
the B/U output.
0B
4-2
Reserved
Reserved, set to zero.
0B
1
DRSEN
DRS output enable. When HIGH, enables the DRS onto the G/Y output.
0B
0
DRSCK
DRS data rate. Sets the DRS output data rate.
REV. 1.0.0 2/4/03
DRSCK
Function
0
Embeds data bytes (8 bits) at PCK
clock rate
1
Embeds data nibbles (4 bits) at
PXCK clock rate
19
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Comb Filter Control (0C)
7
6
ADAPT
5
4
3
YCES
YCSEL
2
1
0
COMB
Reg
Bit
Name
Description
0C
7-6
ADAPT
Adaption mode. Sets the 3-line comb filter adaption mode in NTSC.
0C
0C
5
4
YCES
YCSEL
ADAPT[1:0]
Function
00
Adapts to best of 3 types of line based comb filters in NTSC
only.
01
Adapts to the best of two field or frame based comb filters
in NTSC only.
10
3 line (tap) comb only. Never adapts to a 2 line (tap) filter.
The higher set of comb filter error signals are sent to the
XLUT. NTSC or PAL comb filter.
11
Adapts to best of two 3 line chroma comb filters in PAL only.
YC input error signal control. Error signal control for YC input, luma comb.
YCES
Function
0
LPF and HPF error signal, between (0H & 1H) or (1H & 2H) in
NTSC or between (0H & 2H) in PAL,are sent to XLUT
1
LPF error signal, between (0H & 1H) and (1H & 2H) in NTSC or
between (0H & 2H) in PAL, are sent to XLUT
Luma/chroma comb filter select. Selects luma or chroma comb filter.
YCSEL
0C
3-0
COMB
0
Chroma comb filter
1
Luma comb filter
Comb filter architecture.
COMB
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
20
Function
Function
YC or composite comb filter architectures
PAL or NTSC 3 line comb
NTSC 3 line comb (0H & 1H)
NTSC 3 line comb (1H & 2H)
NTSC 2 line comb (0H & 1H)
NTSC (2 line) field comb
NTSC or PAL field comb
NTSC (2 line) frame comb
NTSC frame comb
D1 comb filter architectures
3 line comb
3 line comb (0H & 1H)
3 line comb (1H & 2H)
3 line comb (0H & 2H)
(2 line) field comb
field or 2 line (0H & 1H) comb
(2 line) frame comb
frame comb
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Comb Filter Control (0D)
7
6
CEST
5
4
3
2
1
0
CESG
YESG
CESTBY
XFEN
FAST
YWBY
Reg
Bit
Name
Description
0D
7-6
CEST
Chroma error signal transform.
0D
5
CESG
CEST
Video Standard
Clock Rate (MHz)
00
PAL/NTSC
4*Fsc & 13.5MHz
01
NTSC
12.27MHz
10
PAL
14.75MHz
11
PAL
15MHz
Chroma error signal gain.
CESG
0D
4
YESG
Function
0
Normal chroma fail signal levels
1
Double the chroma error signal levels
Luma error signal gain.
YESG
Function
0
Normal luma fail signal levels
1
Double the luma error signal levels
0D
3
CESTBY
Chroma error signal bypass. When HIGH, bypasses chroma error signal.
0D
2
XFEN
XLUT filter enable. When HIGH, enables the LPF on the XLUT output.
0D
1
FAST
Adaption speed select. When HIGH, the 3 line comb filter selects between
comb filter architectures on a pixel by pixel basis. When LOW, the selection
is filtered.
0D
0
YWBY
Luma weighting bypass. When HIGH bypasses the luma fail weighting.
REV. 1.0.0 2/4/03
21
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Comb Filter Control (0E)
7
6
XIP
5
4
3
XSF
2
1
YMUX
0
CMUX
Reg
Bit
Name
Description
0E
7-6
XIP
XLUT input select. Selects the comb fail signals presented to the XLUT:
0E
0E
5-4
3-2
XSF
YMUX
XIP[1:0]
Input to XLUT
00
2 bits of phase error (X[7:6]), 3 bits of chroma
(X[5:3]) and luma magnitude error (X[3:0]).
01
4 bits of chroma (X[7:4]) and luma magnitude
error (X[3:0]).
10
3 bits of phase error (X[7:5]), 3 bits of chroma
magnitude error (X[4:2]), and 2 bits of luma
magnitude error (X[1:0]).
11
4 bits of phase error (X[7:4]) and chroma
magnitude error (X[3:0]).
XLUT special function.
XSF
Luma
Chroma
00
Comb
Simple
01
Simple
Comb
10
Flat with notch
Simple
11
Flat with notch
Comb
Y output select. Output selection of luma 4:1 mux
YMUX
0E
1-0
CMUX
Output
00
Comb
01
Flat - Comb
10
Flat
11
Simple
C output select. Output selection of chroma 4:1 mux
CMUX
22
Output
00
Comb
01
Flat - Comb
10
Flat
11
Simple
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Comb Filter Control (0F)
7
6
Reserved
5
4
3
DCES
CAT
2
IPCF
1
0
YCCOMP
SYNC
Reg
Bit
Name
Description
0F
7
Reserved
Reserved, set to zero.
0F
6-5
CAT
Adaption threshold. Fixes threshold at which different comb filters are selected.
0
1
0
1
0
0
1
1
0F
4
DCES
5% of max error
15% of max error
25% of max error
50% of max error
D1 CBCR error signal. When set LOW for D1 chroma comb filters:
a) In 3 line comb filter architectures, the magnitude error between the component
data for that pixel selects the 3 line comb or adapts to a
2 line comb. On a “CB pixel” the error signal selected on pixel (x+4) is sent to
the XLUT with the magnitude difference between “CR pixels” on the same pair
of lines, but from pixel (x+3). Likewise on a “CR pixel” the error signal selected
on pixel (x+5) is sent to the XLUT with the magnitude difference between “CB
pixels” on the same lines but from pixel (x+4).
b) In 2 line comb filters the magnitude differences between the same pair of lines
is always sent to the XLUT, On a “CB pixel” the error from the preceding “CR
pixel” is used and on a “CR pixel” the preceding “CB pixel” would be used.
When set HIGH for D1 chroma filters:
This is used for 3 line comb filter architecture that are inhibited from adapting to 2
line comb filter architectures. The input to the XLUT is the magnitude error in CR
between (0H & 1H) and (1H & 2H) on “CR pixels” and the magnitude error
between (0H & 1H) and (1H & 2H) on “CB pixels”.
0F
3-2
IPCF
Comb filter input select. Selects primary inputs to the comb filter.
IPCF
Function
0
0
1
1
Flat video
LPF output
HPF output
Reserved
0
1
0
1
0F
1
YCCOMP
YC or Composite input select. Selects YC inputs when HIGH and composite
inputs when LOW.
0F
0
SYNC
Sync processor select. The syncs are obtained by a LPF when HIGH and by the
comb filter when LOW.
Sync Pulse Generator (10)
7
6
5
4
3
2
1
0
STS7
STS6
STS5
STS4
STS3
STS2
STS1
STS0
Reg
Bit
Name
Description
10
7-0
STS7-0
Sync to sync 8 lsbs. Bottom 8 bits of the number of pixels between sync
pulses.
REV. 1.0.0 2/4/03
23
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Sync Pulse Generator (11)
7
6
5
4
3
2
1
0
STB
Reg
Bit
Name
Description
11
7-0
STB
Sync to burst. Controls the number of pixels from sync to burst. This signal
starts the burst sample and hold. In SC mode, subtract 25 from the desired
delay to generate this value.
Sync Pulse Generator (12)
7
6
5
4
3
2
1
0
BTV
Reg
Bit
Name
Description
12
7-0
BTV
Burst to video. Controls the number of pixels from STB to the start of active
video.
Sync Pulse Generator (13)
7
6
5
4
3
2
1
0
AV7
AV6
AV5
AV4
AV3
AV2
AV1
AV0
Reg
Bit
Name
Description
13
7-0
AV7-0
Active video line 8 lsbs. Bottom 8 bits of the number of pixels during the
active video line.
Sync Pulse Generator (14)
7
6
Reserved
5
4
3
2
1
0
AV9
AV8
Reserved
STS10
STS9
STS8
Reg
Bit
Name
Description
14
7-6
Reserved
Reserved, set to zero.
14
5-4
AV9-8
Active video line 2 msbs. Two most significant bits of AV.
14
3
Reserved
Reserved, set to zero.
14
2-0
STS10-8
Sync to sync 3 msbs. Three most significant bits of STS.
24
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Sync Pulse Generator (15)
7
6
5
4
Reserved
3
2
VINDO
1
0
VDIV
VDOV
Reg
Bit
Name
Description
15
7
Reserved
Reserved, set to zero.
15
6-2
VINDO
Number of lines in vertical window. The number of lines (0 to 31) after the
last EQ pulse that the decoder passes through the Vertical INterval winDOw.
15
1
VDIV
Action inside VINDO. The vertical data inside the `VINDO' is passed
through a simple decoder when LOW, or is passed unprocessed on the luma
channel with the chroma channel set to zero when HIGH.
15
0
VDOV
Action outside VINDO. The vertical data after the `VINDO' and before the
end of vertical blanking is blanked (YUV = 0) when LOW, or passed through
the simple decoder when HIGH.
Sync Pulse Generator (16)
7
6
Reserved
5
4
3
NFDLY
2
Reg
Bit
Name
Description
16
7-6
Reserved
Reserved, set to zero.
16
5-4
NFDLY
new field detect delay. NTSC frame detect delay:
NFDLY
16
3-2
SPGIP
1
SPGIP
0
MSIP
Function
00
pixel count = 0
01
pixel count = 1
10
pixel count = 2
11
pixel count = 3
SPG input select. Selects the input to the Sync Pulse Generator:
SPGIP
Input
00
External HSYNC and VSYNC
01
Digitized sync (subcarrier mode)
10
TRS words embedded in the D1 data stream
11
TRS words embedded in the D2 data stream
16
1
MSIP
Mixed sync separator input. Set HIGH for external VIDEOB reference or
LOW for output of Low Pass Filter.
16
0
SMO
State Machine Offset. Set HIGH for a 1H offset and LOW for a 0H offset.
REV. 1.0.0 2/4/03
25
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Buffered register set 0 (17) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
SG07
SG06
SG05
SG04
SG03
SG02
SG01
SG00
Reg
Bit
Name
Description
17
7-0
SG07-0
Msync gain, 8 lsbs. Bottom 8 bits of mixed sync scalar
lsb = 1/256
Buffered register set 0 (18) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
YG07
YG06
YG05
YG04
YG03
YG02
YG01
YG00
Reg
Bit
Name
Description
18
7-0
YG07-0
Y gain, 8 lsbs. Bottom 8 bits of the luma gain
lsb = 1/256
Buffered register set 0 (19) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
UG07
UG06
UG05
UG04
UG03
UG02
UG01
UG00
Reg
Bit
Name
Description
19
7-0
UG07-0
U gain, 8 lsbs. Bottom 8 bits of the U gain
lsb = 1/256
Buffered register set 0 (1A) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
VG07
VG06
VG05
VG04
VG03
VG02
VG01
VG00
Reg
Bit
Name
Description
1A
7-0
VG07-0
V gain, 8 lsbs. Bottom 8 bits of the V gain
lsb = 1/256
Buffered register set 0 (1B) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
YG09
YG08
UG010
UG09
UG08
Reserved
VG09
VG08
Reg
Bit
Name
Description
1B
7-6
YG09-8
Y gain, 2 msb. Top 2 bits of the Y gain. msb = 2
1B
5-3
UG010-8
U gain, 3 msbs. Top 3 bits of the U gain. msb = 4
1B
2
Reserved
Reserved, set to zero.
1B
1-0
VG09-8
V gain, 2 msbs. Top 2 bits of the V gain. msb = 2
26
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Buffered register set 0 (1C) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
YOFF07
YOFF06
YOFF05
YOFF04
YOFF03
YOFF02
YOFF01
YOFF00
Reg
Bit
Name
Description
1C
7-0
YOFF07-0
Y offset, 8 lsbs. Bottom 8 bits of luma or RGB offset
Buffered register set 0 (1D) Active when BUFFER pin set LOW.
7
6
5
4
3
Reserved
2
1
0
YOFF08
SG09
SG08
Reg
Bit
Name
Description
1D
7-3
Reserved
Reserved, set to zero.
1D
2
YOFF08
Y offset, msb. msb of YOFF
1D
1-0
SG09-8
Msync gain, 2 msbs. Top 2 bits of mixed sync scalar.
msb = 2
Buffered register set 0 (1E) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
SYSPH06
SYSPH05
SYSPH04
SYSPH03
SYSPH02
SYSPH01
SYSPH00
VAXIS0
Reg
Bit
Name
Description
1E
7-1
SYSPH06-0
7 lsbs of phase offset. Bottom 7 bits of the 15 bit system phase offset
1E
0
VAXIS0
V axis flip. Flips the sign of the V axis when HIGH.
Buffered register set 0 (1F) Active when BUFFER pin set LOW.
7
6
5
4
3
2
1
0
SYSPH014
SYSPH013
SYSPH012
SYSPH011
SYSPH010
SYSPH09
SYSPH08
SYSPH07
Reg
Bit
Name
Description
1F
7-0
SYSPH014-7
8 msbs of phase offset. Top 8 bits of 15 bit system phase offset.
Normalized Subcarrier Frequency (20)
7
6
5
4
FSC3
FSC2
FSC1
FSC0
3
2
1
Reserved
Reg
Bit
Name
Description
20
7-4
FSC3-0
Bottom 4 bits of fsc. Bottom 4 bits of the 28 bit subcarrier SEED
20
3-0
Reserved
Reserved, set to zero.
REV. 1.0.0 2/4/03
0
27
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Normalized Subcarrier Frequency (21)
7
6
5
4
3
2
1
0
FSC11
FSC10
FSC9
FSC8
FSC7
FSC6
FSC5
FSC4
Reg
Bit
Name
Description
21
7-0
FSC11-4
Lower 8 bits of fsc. Lower 8 bits of the 28 bit subcarrier SEED
Normalized Subcarrier Frequency (22)
7
6
5
4
3
2
1
0
FSC19
FSC18
FSC17
FSC16
FSC15
FSC14
FSC13
FSC12
Reg
Bit
Name
Description
22
7-0
FSC19-12
Middle 8 bits of fsc. Middle 8 bits of the 28 bit subcarrier SEED
Normalized Subcarrier Frequency (23)
7
6
5
4
3
2
1
0
FSC27
FSC26
FSC25
FSC24
FSC23
FSC22
FSC21
FSC20
Reg
Bit
Name
Description
23
7-0
FSC27-20
Top 8 bits of fsc. Top 8 bits of the 28 bit subcarrier SEED
28
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Normalized Subcarrier Frequency (24)
7
6
CLMPEN
PFLTEN
5
4
3
2
CLPBY
CLPSEL1-0
1
0
CLPOF2-0
Reg
Bit
Name
Description
24
7
DREFSEL
Decoder Reference Signal Select. When HIGH, enables a negative going
clamp pulse on the DREF pin. The position of the clamp pulse is controlled
by register 24. When LOW the DREF pin is HIGH during the active video
portion of each line and LOW during the horizontal and vertical blanking
intervals.
24
6
PFLTBY
Phase error filter bypass. When HIGH, no filtering is done on the phase
error signals for the comb filter adapter. When LOW, the filter is enabled.
24
5-4
CLPSEL1-0
Internal black level clamp selection.
CLMP[1:0]
Function
00
Clamp disabled, black level set to 240
01
Clamp disabled, black level set to 256
10
Clamp enabled, use Delayed VIDEOB input as
reference
11
Clamp enabled, use LPF as reference
24
3
VCLPEN
Vertical clamp filter enable. When LOW, vertical clamp filter is disabled.
When HIGH, vertical clamp filter is enabled.
24
2-0
BAND2-0
Clamp guard band. When an error value between two consecutive lines
black level is less than the guard band, it does not effect the filtered black
level.
BANDS[2:0]
Function
000
No guard band
001
error value < 2
010
error value < 4
011
error value < 6
100
error value < 8
101
error value < 10
110
error value < 12
111
error value < 15
Normalized Subcarrier Frequency (25)
7
6
5
4
3
2
1
0
CPDLY7-0
Reg
Bit
Name
Description
25
7-0
CPDLY7-0
Clamp pulse delay. Controls the number of clock cycles from hsync before
the 0.5 µSec clamp pulse is output to the AVOUT pin. This option is only
enabled when register 24 bit 7 is set HIGH.
REV. 1.0.0 2/4/03
29
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Output Format Control (26)
7
6
Reserved
Reg
Bit
5
4
3
LDVIO
OPCKS
DPCEN
Name
Description
2
1
0
DPC
26
7-6
Reserved
Reserved, set to zero.
26
5
LDVIO
LDV clock select. LDV is an output when LOW and an input when HIGH
26
4
OPCKS
Output clock select. The output data are clocked by the CLOCK pin when
LOW and by the LDV pin when HIGH.
26
3
DPCEN
DPC enable. When HIGH on the TMC22153A, the Decoder Product Code is
enabled: a value written into DPC determines the decoder product emulated
by the TMC22153A. In all other versions of the decoder, DPC is read-only,
and returns the code of the particular encoder version installed.
26
2-0
DPC
Decoder product code
DPC
Function
000
Reserved
001
TMC22051A
010
TMC22052A
011
TMC22053A
100
Reserved
101
TMC22151A
110
TMC22152A
111
TMC22153A
Read/Write in the TMC22153A only. Read-only in all other devices.
Buffered register set 1 (27) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
SG17
SG16
SG15
SG14
SG13
SG12
SG11
SG10
Reg
Bit
Name
Description
27
7-0
SG17-0
Msync gain, 8 lsbs. Bottom 8 bits of the mixed sync scalar
lsb = 1/256
Buffered register set 1 (28) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
YG17
YG16
YG15
YG14
YG13
YG12
YG11
YG10
Reg
Bit
Name
Description
28
7-0
YG17-0
Y gain, 8 lsbs. Bottom 8 bits of the luma gain
lsb = 1/256
30
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Buffered register set 1 (29) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
UG17
UG16
UG15
UG14
UG13
UG12
UG11
UG10
Reg
Bit
Name
Description
29
7-0
UG17-0
U gain, 8 lsbs. Bottom 8 bits of the U gain
lsb = 1/256
Buffered register set 1 (2A) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
VG17
VG16
VG15
VG14
VG13
VG12
VG11
VG10
Reg
Bit
Name
Description
2A
7-0
VG17-0
V gain, 8 lsbs. Bottom 8 bits of the V gain
lsb = 1/256
Buffered register set 1 (2B) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
YG19
YG18
UG110
UG19
UG18
Reserved
VG19
VG18
Reg
Bit
Name
Description
2B
7-6
YG19-8
Y gain, 2 msbs. Top 2 bits of the Y gain
msb = 2
2B
5-3
UG110-8
U gain, 3 msbs. Top 3 bits of the U gain.
msb = 4
2B
2
Reserved
reserved, set to zero
2B
1-0
VG19-8
V gain, 2 msbs. Top 2 bits of the V gain
msb = 2
Buffered register set 1 (2C) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
YOFF17
YOFF16
YOFF15
YOFF14
YOFF13
YOFF12
YOFF11
YOFF10
Reg
Bit
Name
Description
2C
7-0
YOFF17-0
Y offset, 8 lsbs. Bottom 8 bits of luma or RGB offset
REV. 1.0.0 2/4/03
31
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Buffered register set 1 (2D) Active when BUFFER pin set HIGH.
7
6
5
4
3
Reserved
2
1
0
YOFF18
SG19
SG18
Reg
Bit
Name
Description
2D
7-3
Reserved
Reserved, set to zero.
2D
2
YOFF18
Y offset, msb. msb of YOFF
2D
1-0
SG19,8
Msync gain, 2 msbs. Top 2 bits of mixed sync scalar
msb = 2
Buffered register set 1 (2E) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
SYSPH16
SYSPH15
SYSPH14
SYSPH13
SYSPH12
SYSPH11
SYSPH10
VAXISO
Reg
Bit
Name
Description
2E
7-1
SYSPH16-0
7 lsbs of phase offset. Bottom 7 bits of the 15 bit system phase offset
2E
0
VAXIS1
V axis flip. Flips the sign of the V axis when HIGH.
Buffered register set 1 (2F) Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
SYSPH114
SYSPH113
SYSPH112
SYSPH111
SYSPH110
SYSPH19
SYSPH18
SYSPH17
Reg
Bit
Name
Description
2F
7-0
SYSPH114-7
8 msbs of phase offset. Top 8 bits of 15 bit system phase offset.
32
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Video Measurement (30)
7
6
5
4
3
2
1
0
Reserved
LGF
LGEN
LGEXT
RESERVED
PGG
PGEN
PGEXT
Reg
Bit
Name
Description
30
7
Reserved
Reserved, set to zero.
30
6
LGF
Line grab flag. Set HIGH when the decoder has grabbed a line, and must be
reset LOW before another line can be grabbed.
30
5
LGEN
Line grab enable. When HIGH, the line grabber is used to freeze the
contents of the line store, at the programmed line and field count. The phase
and frequency of the frozen line are also stored from the DRS, and are
continually used to reset the DDS, once per line, until LGF is set LOW. When
LGEN is LOW, the line freeze is disabled, the internal loops operate normally,
and the line grab signal is used only to gate the pixel grab.
30
4
LGEXT
Ext line grab enable. The SET pin is used to produce the line grabber pulse
when HIGH and the internal line decode is used when LGEXT is LOW.
30
3
Reserved
Reserved, set to zero.
30
2
PGG
Pixel grab gate. When HIGH the pixel grab is gated by the field and line grab
signals to enable one pixel per four fields in NTSC and 8 field in PAL to be
grabbed. This function is disabled if PGEN is set LOW.
30
1
PGEN
Pixel grab enable. When HIGH the 10 bit G/Y, B/U, and R/V data, and the
mixed sync and luma data after the comb filter, and the demodulated (B-Y)
and (R-Y) color difference signals are grabbed once every line at the
programmed pixel grab number. When LOW the contents of the pixel grab
registers are held and the pixel grab pulse is ignored.
30
0
PGEXT
Ext pixel grab enable. The SET pin is used to produce the pixel grab pulse
when HIGH and the internal pixel decode is used when PGEXT is LOW.
Video Measurement (31)
7
6
5
4
3
2
1
0
PG7
PG6
PG5
PG4
PG3
PG2
PG1
PG0
Reg
Bit
Name
Description
31
7-0
PG7-0
Pixel grab, 8 lsbs. Bottom 8 bits of the pixel grab.
Video Measurement (32)
7
6
5
4
3
2
1
0
LG7
LG6
LG5
LG4
LG3
LG2
LG1
LG0
Reg
Bit
Name
Description
32
7-0
LG7-0
Line grab, 8 lsbs. Bottom 8 bits of the line grab.
REV. 1.0.0 2/4/03
33
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Video Measurement (33)
7
6
Reserved
5
4
FG
3
2
1
0
LG8
PG10
PG9
PG8
Reg
Bit
Name
Description
33
7
Reserved
Reserved.
33
6-4
FG
Field grab number. Field grab number
33
3
LG8
Msb of line grab. msb of line grab
33
2-0
PG10-8
Pixel grab, 3 msbs. 3 msbs of pixel grab
Registers 34-3C are Read-Only
Register (34)
7
6
5
4
3
2
1
0
GY9
GY8
GY7
GY6
GY5
GY4
GY3
GY2
Reg
Bit
Name
Description
34
7-0
GY9-2
G/Y grab, 8 msbs. Top 8 bits of the "grabbed" G/Y data
Register (35)
7
6
5
4
3
2
1
0
BU9
BU8
BU7
BU6
BU5
BU4
BU3
BU2
Reg
Bit
Name
Description
35
7-0
BU9-2
B/U grab, 8 msbs. Top 8 bits of the "grabbed" B/U data
Register (36)
7
6
5
4
3
2
1
0
RV9
RV8
RV7
RV6
RV5
RV4
RV3
RV2
Reg
Bit
Name
Description
36
7-0
RV9-2
R/V grab, 8 msbs. Top 8 bits of the "grabbed" R/V data
Register (37)
7
6
Reserved
5
4
3
2
1
0
GY1
GY0
BU1
BU0
RV1
RV0
Reg
Bit
Name
Description
37
7-6
Reserved
Reserved.
37
5-4
GY1-0
G/Y grab, 2 lsbs. Bottom two bits of G/Y data
37
3-2
BU1-0
B/U grab, 2 lsbs. Bottom two bits of B/U data
37
1-0
RV1-0
R/V grab, 2 lsbs. Bottom two bits of R/V data
34
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Register (38)
7
6
5
4
3
2
1
0
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Reg
Bit
Name
Description
38
7-0
Y9-2
Luma grab, 8 msbs. Top 8 bits of the "grabbed" luma data after YPROC
Register (39)
7
6
5
4
3
2
1
0
M9
M8
M7
M6
M5
M4
M3
M2
Reg
Bit
Name
Description
39
7-0
M9-2
Msync grab, 8 msbs. Top 8 bits of the "grabbed" mixed sync data after
YPROC
Register (3A)
7
6
5
4
3
2
1
0
U9
U8
U7
U6
U5
U4
U3
U2
Reg
Bit
Name
Description
3A
7-0
U9-2
U grab, 8 msbs. Top 8 bits of the "grabbed" U data
Register (3B)
7
6
5
4
3
2
1
0
V9
V8
V7
V6
V5
V4
V3
V2
Reg
Bit
Name
Description
3B
7-0
V9-2
V grab, 8 msbs. Top 8 bits of the "grabbed" V data
Register (3C)
Reg
7
6
5
4
3
2
1
0
Y1
Y0
M1
M0
U1
U0
V1
V0
Bit
Name
Description
3C
7-6
Y1-0
Luma grab, 2 lsbs. Bottom 2 bits of luma data
3C
5-4
M1-0
Msync grab, 2 lsbs. Bottom 2 bits of mixed sync data
3C
3-2
U1-0
U grab, 2 lsbs. Bottom 2 bits of U data
3C
1-0
V1-0
V grab, 2 lsbs. Bottom 2 bits of V data
REV. 1.0.0 2/4/03
35
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Test Control (3D-3E)
7
6
5
4
3
2
1
0
TEST
Reg
Bit
Name
Description
3D-3E 7-0
TEST
Must be set to zero. Auto increment stops at 3F
Test Control (3F)
7
6
5
4
3
2
1
0
VBIT20
PEDDIS
CCDEN5
CCDEN4
CCDEN3
CCDEN2
CCDEN1
CCDEN0
Reg
Bit
Name
Description
3F
7
VBIT20
VBIT20 enable. When HIGH the V bit within embedded TRS words is
extended through line 20 for NTSC. When LOW, this V bit is HIGH up to line
16 for NTSC. The PAL operation is unaffected by this register bit.
3F
6
PEDDIS
Pedestal disable. When HIGH, pedestal is not removed from lines with
LID = 00 to 06, lines 0 through 16
3F
5
CCDEN5
Closed caption data enable 5. When HIGH, enables NTSC line 21 field 0
or PAL line 22 field 0 to be passed ‘FLAT’, through the decoder, on the
luminance channel and the pedestal removal will be disabled.
3F
4
CCDEN4
Closed caption data enable 4. When HIGH, enables NTSC line 22 field 0
or PAL line 23 field 0 to be passed ‘FLAT’, through the decoder, on the
luminance channel and the pedestal removal will be disabled.
3F
3
CCDEN3
Closed caption data enable 3. When HIGH, enables NTSC line 23 field 0
or PAL line 24 field 0 to be passed ‘FLAT’, through the decoder, on the
luminance channel and the pedestal removal will be disabled.
3F
2
CCDEN2
Closed caption data enable 2. When HIGH, enables NTSC line 283 field 1
or PAL line 334 field 1 to be passed ‘FLAT’, through the decoder, on the
luminance channel and the pedestal removal will be disabled.
3F
1
CCDEN1
Closed caption data enable 1. When HIGH, enables NTSC line 284 field 1
or PAL line 335 field 1 to be passed ‘FLAT’, through the decoder, on the
luminance channel and the pedestal removal will be disabled.
3F
0
CCDEN0
Closed caption data enable 0. When HIGH, enables NTSC line 285 field 1
or PAL line 336 field 1 to be passed ‘FLAT’, through the decoder, on the
luminance channel and the pedestal removal will be disabled.
Status - Read Only (40)
7
6
5
4
3
2
1
0
DDSPH
Reg
Bit
Name
Description
40
7-0
DDSPH
DDS phase, 8 msbs. The top 8 bits of the sine data generated in the internal
DDS.
36
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Status - Read Only (41)
7
6
5
4
3
2
1
0
LINEST
BGST
VACT2
PALODD
VFLY
FGRAB
LGRAB
PGRAB
1
0
Reg
Bit
Name
Description
41
7
LINEST
Pixel count reset. Pixel count reset
41
6
BGST
Start of burst gate. Start of burst gate
41
5
VACT2
Half line flag. Half line flag
41
4
PALODD
PAL Ident. PAL Ident (low on NTSC lines)
41
3
VFLY
Vertical count reset. Vertical count reset
41
2
FGRAB
Field grab. Field grab
41
1
LGRAB
Line grab. Line grab
41
0
PGRAB
Pixel grab. Pixel grab
Status - Read Only (42)
7
6
5
4
FLD
VBLK
HBLK
3
2
LID
Reg
Bit
Name
Description
42
7
FLD
Field flag (F in D1 output). Field flag (F in D1 output)
42
6
VBLK
Vertical blanking (V in D1 output). Vertical blanking (V in D1 output)
42
5
HBLK
Horizontal blanking (H in D1 output). Horizontal blanking (H in D1 output)
42
4-0
LID
Line identification. Line identification
Status - Read Only (43)
7
6
5
4
3
2
YGO
YGU
UBO
UBU
VRO
VRU
Reg
Bit
Name
Description
43
7
YGO
Y/G overflow. Y/G overflow
43
6
YGU
Y/G underflow. Y/G underflow
43
5
UBO
CB/B overflow. CB/B overflow
43
4
UBU
CB/B underflow. CB/B underflow
43
3
VRO
CR/R overflow. CR/R overflow
43
2
VRU
CR/R underflow. CR/R underflow
43
1-0
Reserved
Reserved.
REV. 1.0.0 2/4/03
1
0
Reserved
37
TMC22x5yA
PRODUCT SPECIFICATION
Control Register Definitions (continued)
Status - Read Only (44)
7
6
5
4
3
MONO
2
1
0
FPERR
Reg
Bit
Name
Description
44
7
MONO
Color kill flag. High when burst detected and LOW when monochrome
signal is detected.
44
6-0
FPERR
Frequency/Phase error. Top 7 bits of the modulo two pi frequency or phase
error. Reported once per line.
Status - Read Only (45)
7
6
5
4
3
2
1
0
1
0
DRS
Reg
Bit
Name
Description
45
7-0
DRS
DRS signal. The 8-bit Decoder Reference Signal.
Status - Read Only (46)
7
6
5
4
3
2
PARTID
Reg
Bit
Name
Description
46
7-0
PARTID
Part family ID. Reads back the 8-bit part ID number. Read-only. Returns
CDh.
Status - Read Only (47)
7
6
5
4
3
2
1
0
REVID
Reg
Bit
Name
Description
47
7-0
REVID
Recoder revision number.
38
REVID
TMC22x5y Revision
05
F
06
G
TMC22x5yA Revision
10
A
11
B
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Control Register Definitions (continued)
Status - Read Only (48-4A)
7
6
5
4
3
2
1
0
3
2
1
0
1
0
Reserved
Status - Read Only (4B)
7
6
PKILL
Reg
5
4
CFSTAT
XOP
Bit
Name
Description
4B
7
PKILL
Phase kill from comb fail. Phase kill from comb fail.
4B
6-5
CFSTAT
Comb filter status. Comb filter status.
CFSTAT
4B
4-0
XOP
STATUS
00
3 tap comb
01
3 tap [lower] comb
10
3-tap [upper] comb
11
2 tap comb
XLUT output. XLUT output.
Status - Read Only (4C-FF)
7
6
5
4
3
2
Reserved
Reg
Bit
4C-FF 7-0
REV. 1.0.0 2/4/03
Name
Description
Reserved
Reserved.
39
TMC22x5yA
PRODUCT SPECIFICATION
Decoder Introduction
The complete separation of composite video signals into
pure luminance (luma) and chrominance (chroma) signals is
practically impossible, especially when the input source
contains intraframe motion. Therefore, the luminance (luma)
signal will generally contain some high frequency chrominance, termed cross luma, and the chroma signal will
contains some of the high frequency luma signal, centered
around the subcarrier frequency, termed cross color.
The degree of cross luma and cross color is directly proportional to the filter used for the YC separation, the picture content, and the complexity of any post processing of the
decoded signals.
All composite video decoders perform fundamentally the
same operation. The first stage is to separate the luminance
and chrominance. The second stage is to lock the internally
generated sine and cosine waveforms to the burst on the
decoded chrominance signal, demodulate, and then filter the
chrominance signal to produce the color difference signals.
The last stage either scales the luminance and color difference signals, or converts them into red, green, and blue
component video signals. These three stages are shown in
Figure 3.
–
G
Luminance
Y
Y
Green
–
Red
–
Blue
–
Matrix
YC Filter
R
–
Composite
–
C
–
U
Chrominance
V
B
Demodulation
Burst Locked
Loop
–
sin(wt)
cos(wt+φ)
65-22x5y-44
Figure 3. Fundamental Decoder Block Diagram
YC Separation
The Luma Notch and Chroma Bandpass Technique for
YC Separation
The relationship between the chrominance and luminance
bandwidths is shown for both PAL and NTSC in Figure 4,
wherein the shaded area denotes the part of the composite
video frequency spectrum shared by both the chrominance
and high frequency luminance signals.
The simplest method of separating these chrominance and
luminance signals, is to assume the chroma bandwidth is
limited to a few hundred kilohertz around the subcarrier
frequency. In this case a notch filter designed to remove just
these frequencies from the composite video frequency
spectrum provides the luma signal, while a bandpass filter
PAL
Amplitude
(dB)
NTSC
Chrominance
Subcarrier
Sound Carrier
Center Frequency
0
Amplitude
(dB)
-3
Chrominance
Subcarrier
Sound Carrier
Center Frequency
0
-3
Luminance
Luminance
Chrominance
(& High Frequency
Luminance)
Chrominance
(& High Frequency
Luminance)
-20
-20
1
2
3
4
5
6
Frequency (MHz)
1
2
3
4
4.5
Frequency (MHz)
Figure 4. Comparison of the Frequency Spectrum of NTSC and PAL Composite Video Signals
40
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Notch Filter
Amplitude
(dB)
Bandpass Filter
Amplitude
(dB)
Chrominance
Subcarrier
0
0
-3
-3
Chrominance
Subcarrier
Luminance
Chrominance
(& High Frequency
Luminance)
Chrominance
(& High Frequency
Luminance)
-20
-20
FSC
Frequency
FSC
Frequency
Figure 5. Examples of Notch and Bandpass Filters
centered at the subcarrier frequency produces the chroma
signal. This simple technique works well in pictures containing large flat areas of color, however this is rarely the case.
If, as is generally true, the picture contains high frequency
luma and chroma transitions, for example herring bone suit
jackets, branches of trees, text, etc., cross color and cross
luma artifacts are evident.
The presence of cross color or cross luma is generally
acceptable when viewing the decoded picture on a monitor
from several feet, as would be the case in most homes on
commercial television sets. However, these artifacts become
increasingly difficult to process, or ignore, when the image is
to be compressed or manipulated. In these cases more
sophisticated methods of separating the luma and chroma
signals, such as frame, field, or line based comb filter decoders, are required.
Another important disadvantage of the “luma notch filter and
bandpass chroma” technique is that once a notch filter has
been used on the luminance channel this portion of the luminance frequency spectrum is lost. This effect becomes
increasingly objectionable if the decoder component outputs
are subsequently re-encoded into a composite video signal.
Comb Filter Architectures for YC Separation
A comb filter uses the relationship between the number of
subcarrier cycles per line period, to cancel the chrominance
signal over multiple line periods. This is shown for an NTSC
two line comb filter in Figure 6. In NTSC there a 227.5 subcarrier cycles per line period, therefore the subcarrier can be
canceled by simply adding two consecutive field scan lines.
In PAL(B/I/ etc.) there are 283.7516 subcarrier cycles per
line period, ignoring the 0.0016 cycle advance caused by the
25Hz offset, the PAL subcarrier can be canceled by adding
the first and third line of three consecutive field scan lines.
Due to the 270 degree advance, it is not possible to use information from consecutive field lines without adding a PAL
modifier. A PAL modifier produces a 90 degree phase shift in
the chrominance signal by multiplying the chrominance
signal by a signal at two times the subcarrier frequency that
is phased locked to the subcarrier burst reference in the composite video waveform. In addition the PAL modifier inverts
REV. 1.0.0 2/4/03
the V component of the chrominance signal. This document
refers to line based comb decoders when discussing decoders
that use inputs from sequential scan lines, i.e. lines from the
same field, field based comb decoders when describing
decoders that use inputs from sequential fields, and finally
frame based comb decoders when examining decoders that
use inputs from sequential frames.
+
Delay = 1/T
1/2
Amplitude
1.0
1/2T
1T 3/2T
2T
5/2T
3T 7/2T
4T
9/2T
5T 11/2T 6T
Frequency
Figure 6.
Composite Line-Based Comb Decoders
The phase relationship of the quadrature modulated chrominance signal can also be represented as in Figure 7. The three
line comb based decoder is clearly biased towards 1H which
illustrates the inherent one line delay through a 3 line comb,
while a two line comb based decoder is biased towards 0H.
In the following discussions a flat color represents video of
constant luma and chroma magnitude and phase.
In NTSC, adding two adjacent lines of flat color will cancel
the chroma and leave the luma whereas subtracting two lines
of flat color will cancel the luma and leave the chroma. In a 3
line comb filter the flat color on 0H and 2H is added to provide the flat color average before adding or subtracting from
1H.
In PAL, adding the flat color from 0H and 2H will cancel the
chroma and leave the luma while subtracting the flat color
from 0H and 2H will cancel the luma and leave the chroma.
However, chroma generated in this manner has no simple
41
TMC22x5yA
PRODUCT SPECIFICATION
phase relationship to the chroma on 1H. Therefore normally
0H and 2H are added together to produce the average luma
across 3 lines and this is then subtracted from 1H to produce
the combed chroma.
FIELD LINE no
PAL
1
0
283
I
N
Q
V
M
V
N+1
U
2H
0
M+1
N+2
V
21
1
M+2
N+3
1H
0H
0
M+3
I
N+4
Q
I
Q
I
Q
286
24
V
Q
Figure 7. Chrominance Vector Rotation in PAL and NTSC
I
Q
Q
I
Q
65-22x5y-48
I
Q
I
I
Q
I (FR0H)
Q
Q
I
U
I
I
I (F0H)
Q
23
U
(FR1H) I
I
I
285
V
1
(0H)
FIELD 4
Q
(F1H)
Q
Q
FIELD 3
Q
Q
284
Q
U
0
(1H)
I
22
1
FIELD 2
I
Q
LINE no FIELD 1
NTSC
U
0
0H and FR0H and the two consecutive field lines FR0H and
FR1H are 180 degrees apart. The flat color on FR0H and
FR1H can be added or subtracted to provide the luminance
or chrominance to subtract from 0H.
65-22x5y-49
Figure 8. Chrominance Vector Rotation Over 4
Fields in NTSC
YC Line-Based Comb Filters
Composite Field-Based Comb Filters
The luminance and chrominance signals, are by definition,
already separated for YC inputs. However, if the original
source was composite, there is a distinct possibility that there
is some residual luminance (cross color) in the chrominance
signal and some residual chrominance (cross luma) in the
luminance signal. It is therefore legitimate to treat these
signals as if they were simply the output from bandsplit
filters and process the luma and chroma signals accordingly.
In NTSC field based comb decoders, there is an external
delay of 263 lines, therefore the 2 adjacent picture lines 0H
and F0H and the two consecutive field lines F0H and F1H
are 180 degrees apart. The flat color on F0H and F1H can be
added or subtracted to provide the luminance or chrominance to subtract from 0H.
D1 Line-Based Comb Filters
Composite, PAL Field Comb Filters
A D1 data stream consists of multiplexed Y, CB and CR
component data. If the original source was composite there
maybe luminance (cross color) in CBCR and chrominance
(cross luma) in Y. In the first case any luminance that was
passed through a demodulator along with the chroma to
produce the baseband CBCR color difference signals would
have the same characteristics as chroma. That is to say, the
cross color would advance by 180° every line in NTSC and
every 2 lines in PAL. It is therefore possible to remove this
cross color in a comb filter. In the latter case any chrominance that is still in the Y data can obviously be removed in a
comb filter as well.
In PAL field based comb decoders, there is an external delay
of 312 lines, therefore the 2 adjacent picture lines 0H and F0H
are 180 degrees apart. In fields 5, 6, 7, and 8 the U and V
vectors are 180 degrees advanced from fields 1, 2, 3, and 4.
PAL Field Decoders
LINE no
FIELD 2 FIELD 3 FIELD 4
FIELD 1
V
U
23
U
V
U
336
24
V
U
(0H)
NTSC Frame and Field Based
Decoders
Composite Frame-Based Comb Filters
25
(FR0h)
V
U
U
U
V
U (FR0H)
V
U
V
V
V
U
338
26
V
V
V
337
The original source for the D1 signal could also have been
computer graphics. In this case, the comb filter can be used
to remove the picture flicker and convert the output to RGB.
U
(F0H)
U
U
U
V
V
65-22x5y-50
Figure 9. Chrominance Vector Rotation
Over 4 Fields in PAL
In NTSC the chrominance vectors advance by 180 degrees
every line, therefore after 525 lines the 2 adjacent frame lines
42
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
The TMC22x5yA Comb Filter
Architecture
The TMC22x5yA, when implementing a line based comb
filter, has a core architecture as shown in Figure 10. The concept of the complementary bandsplit filter is also observed in
the complementary comb filter architecture. It is therefore
possible to adapt between the complementary comb filter
and bandsplit filter without throwing away any of the
original composite video frequency spectrum.
The first step in the complementary comb filter is to separate
the high frequency luminance from the chrominance signal.
This combed high frequency luma signal is shown as
YCOMB in Figure 10. The second step is to produce an array
of comb filter error signals that indicate the degree of confidence that the YCOMB signal is just the high frequency luma
and not a combination of high frequency luma and chroma
smeared over the number of lines used in the comb filter. The
signal representing this degree of confidence is termed “K”
in Figure 10. The last step is to provide a complementary
cross fade between the YCOMB signal and the output of the
complementary bandsplit filter, shown as SIMPLE in Figure
10. The FLAT signal is simply a delayed version of the input
to the comb filter, therefore the sum of Output1 and Output2
will always be equal to the FLAT video input.
The TMC22x53A comb filter architecture has three taps.
These taps are three consecutive field lines in a line based
comb, three consecutive picture lines in a field based comb,
or lines that are one frame and one field line apart in the
frame based comb. In addition to these different inputs to the
comb filter, NTSC and PAL video signals comb over different taps in different architectures, as described in the comb
filter introduction.
The total internal pipeline latency is 1H + 40 pixels for 3 line
comb filters, for all other comb filter and simple decoder
architectures the pipeline latency is 40 pixels.
XLUT
–
Output1
SIMPLE
Input
1H
Bandsplit
Filters
COMB
Filter
YCOMB
X
+
Output2
Simple +/- {k * Ycomb}
1H
XLUT
K
Figure 10. TMC22x5yA Line Based Comb Filter Architecture
REV. 1.0.0 2/4/03
43
TMC22x5yA
PRODUCT SPECIFICATION
TMC22x5yA Functional Description
Input Processor
Input
The input processor selects between the two external video
sources on VIDEO A and VIDEO B. If the TRS stripper or
GRS stacker is active, then the user must select the input
with either the GRS (in genlock mode) or with the embedded
TRS words as output VA. If the input data are separate luma
and chroma or Y and CBCR data the input processor must be
programmed to put the chrominance or CBCR onto output
VB and the luminance or Y onto VA.
To ensure that the chrominance data or the CBCR data are in
two’s complement arithmetic format, the register bit MSBI
inverts the msb of the DB input. For composite inputs, the
IPCMSB register bit should be set LOW, as the ABMUX
register bit is used to select the input(s) to the comb filter.
Bandsplit Filter (BSF)
In its simple mode of operation, the TMC22x5yA uses a
complementary bandsplit filter, instead of a notch filter for
the luma and a bandpass for the chroma. The notch and
bandpass filter technique, removes frequency bands from the
composite video spectrum which can never be retrieved.
The complementary bandsplit filter technique, shown in
Figure 12, allows the decoded component video signals to be
re-encoded into a composite video signal with the minimum
of losses to the composite video spectrum.
msb
x
VA
VideoA
–
IP8B
TDEN
Figure 12. Complementary Bandsplit Filter
The complementary bandsplit filter separates the base band
composite video into two bands by passing it through a low
pass filter and subtracting the low pass (luma) data from the
composite video to produce the high pass (chroma) data. As
the base bandwidths and subcarrier frequencies of the different NTSC and PAL video formats are so different, and the
decoder has to be capable of working over a large frequency
range, it is necessary to provide two low pass filters. These
filters are selectable by the BSFSEL register bit and are independent of the video standard. A comparison of the different
data rates to normalized subcarrier frequencies is provided in
Table 2.
The complementary bandsplit low pass frequency response
is shown in Figure 13 and Figure 14.
TBLK
lsb
ICPMSB ABMUX CKSEL
TRS Stripper (D1/D2/D3)
and
GRS Stacker (TMC22071)
DA
Primary Data
to Comb Filter
2:2 MUX
2:2 MUX
VideoB
HPF Output
65-22x5y-53
Input Processor Control Register
IPMUX
LPF Output
LPF
VB
MSB
Invert
DB
Secondary Data
to Comb Filter
65-22x5y-52
Figure 11. Input Processor
44
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
1
0
0
0.40
0.30
0.20
0.00
-70
0.10
-60
Normalized Frequency
Bandsplit Filter 1
-4
65-22x5y-55
65-22x5y-54
-50
-3
-5
-6
0.15
Bandsplit Filter 1
0.10
-40
Bandsplit Filter 2
-2
0.05
-30
-1
0.00
Bandsplit Filter 2
Attenuation (dB)
-20
0.50
Attenuation (dB)
-10
Normalized Frequency
Figure 13. Bandsplit Filter, Full Frequency Response
Figure 14. Bandsplit Filter, Passband Response
Table 2. Normalized Subcarrier Frequency as a Function of Pixel Data Rates
Pixel Rate (MHz)
FSC
(MHz)
Normalized FSC
12.27
3.57954545
0.2917
NTSC square pixel rate
13.50
3.57954545
0.2652
NTSC D1 pixel rate
13.50
4.43361875
0.3284
PAL-I D1 pixel rate
14.32
3.57954545
0.2500
NTSC four times subcarrier (D2/D3)
14.75
4.43361875
0.3006
PAL-I square pixel rate
15.00
4.43361875
0.2956
PAL-I square pixel rate
17.73
4.43361875
0.2500
PAL-I four times subcarrier (D2/D3)
13.5
3.57561149
0.2649
PAL-M D1 pixel rate
13.5
3.58205625
0.2653
PAL-N D1 pixel rate
14.30
3.57561149
0.2500
PAL-M four times subcarrier (D2/D3)
Comb Filter Input
The inputs to the comb filter are selected from either the high
frequency outputs of the bandsplit filters, if using a chroma
comb filter, or the full composite waveforms when implementing a luma comb. The two sets of high and low frequency signals from the bandsplit filters are used for both the
REV. 1.0.0 2/4/03
Comments
luma and chroma SIMPLE signals, and in the generation of
the comb fail signals. These signals are denoted xHL, xHH,
and xHF where L denotes the low frequency portion of the
signal, H the high frequency portion of the signal and F the
full frequency spectrum of the input signal from line x; and
are shown in Figure 15.
45
TMC22x5yA
PRODUCT SPECIFICATION
0HF
Primary
Input
0HL
LPF
BSFSEL
–
2:1
MUX
0HH
1HF
LSTORE1
[9:0]
2:1
MUX
Secondary
Input
1HL
LPF
LS1IN
BSFSEL
LS1BY
–
LSTORE2
2HH
1HH
2HH
+
1HH (lsbs)
1HL (lsbs)
2:1
MUX
2:1
MUX
LSTORE2
2HX
LSTORE2
2HL
1HL
1HH
2HF
2HL
Split
DELAY
VIDEOB
65-22x5y-56
Figure 15. Block Diagram of Comb Filter Input
The primary and secondary inputs are selected within the
input processor. The primary input is normally the undelayed
composite video signal in line, field, and frame based comb
filters or either the luma or chroma channel when processing
YC or D1 signals. The secondary provides the field or frame
delayed composite input for field and frame based comb
filters and the chroma or luma channel when processing YC
or D1 signals.
When implementing a line based comb filter the outputs of
1H bandsplit filter, ie 1HH, 1HL, are delayed through the
second line store, LSTORE2. The number of bits delayed is
dependent upon the type of comb filter being implemented.
For chroma comb filters all the bits of the 1HH signal are
delayed, as this information supplies the outer tap of the
chroma comb filter, while only the upper bits of 1HL are
delayed as this data is used only in the generation of the
46
luma error signals. In the case of luma combs an equal
number of bits of the 1HH and 1HL signals are delayed and
summed together to produce the 2HF signal for the outer tap
of the luma comb filter. The configuration of LSTORE2 is
determined by the SPLIT register bit.
It is important to note that when implementing a field or
frame based comb filter the secondary input must be selected
by setting the LSIN register bit HIGH, and the first line store,
LSTORE1, must be bypassed by setting the LS1BY register
bit HIGH.
For YC and D1 processing the secondary input bypasses the
comb filter completely and provides the VIDEOB signal
input the 3:1 multiplexer used to select the FLAT signal,
see Figure 16.
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Adaptive Comb Filter
The IPCF[1:0] register bits select the inputs to the adaptive
comb filter, this would normally be xHH for chroma combs,
xHF for luma combs, and xHL if the luminance signal was to
be sampled dropped on the output of the TMC22x5yA. The
Gaussian filters in the sample drop mode already limit the
chrominance bandwidth to 1.3MHz allowing a [2:1:1] data
format on the output, with the luminance signal having been
vertically filtered by a fixed 3 line comb filter.
The SIMP selection bit is an internally generated signal
based upon the comb filter selected. If a 3 line chroma, luma,
or D1 comb filter is selected, due to the internal 1H delay
inherent with this type of comb filter, the 1HL and 1HH
signals are selected for the respective luma and chroma
SIMPLE data signals. When any other type of comb filter is
selected 0HL and 0HH are selected.
The DLYF selection bit is also internally generated from the
type of comb filter selected and whether or not the input is in
either the YC or Y & CbCr (ie D1 input) data formats. The
VIDEOB data is always selected when the YCCOMP register
bit is HIGH, ie for YC inputs. The selection of 1HF or 0HF
depends upon the SIMP selection bit only when the
YCCOMP register bit is LOW. Therefore, when YCCOMP is
LOW and 0Hx is selected by SIMP then 0HF is selected for
the FLAT signal, and when 1Hx is selected by SIMP then
1HF is selected for the FLAT signal. This ensures that the
FLAT and SIMPLE data selected for any comb filter is
delayed by the same amount as the data processed through
the comb filter to produce the COMB output.
The final selection is the output required for the combed
luminance and chrominance data. The output selection can
be SIMPLE, COMB, FLAT-COMB, or FLAT. Generally
COMB is selected based upon whether a luma or chroma
comb was selected and the complementary output selects
FLAT-COMB. In the YC and Y & CbCr data modes the FLAT
signal selects the secondary data and SIMPLE or COMB can
be used to select the primary signal. In these modes the
bandsplit filter can be bypassed or used to remove low frequency noise from the chrominance signal if chroma was
selected as the primary signal.
A
SIMP
2:1
MUX
B
4:1
MUX
IPCF[1:0]
C
OHF
OHH
Y Data
3:1
MUX
D
OHL
YMUX[1:0]
IPCF[1:0]
1HF
1HH
3:1
MUX
1HL
Adaptive
Comb
Filter
A: Comb
B: Simple
C: Flat - Comb
D: Flat
IPCF[1:0]
2HF
2HH
3:1
MUX
CMUX[1:0]
2HL
A
SIMP
2:1
MUX
B
4:1
MUX
DLYF
3:1
MUX
–
C Data
C
D
VideoB
65-22x5y-57
Figure 16. Signal Flow Around the Adaptive Comb Filter.
REV. 1.0.0 2/4/03
47
TMC22x5yA
PRODUCT SPECIFICATION
The comb filter architecture performs chrominance or luminance comb filtering on PAL or NTSC video signals, by
implementing one of sixteen independent chroma and luma
comb filter algorithms. The highest level of the adaptive
comb filter configuration is determined by the STA[3:0]
register bits as shown in Table 3.
Table 3. Comb Filter Architecture
STA[3:0]
Comb Filter Description
0
YC or Composite, PAL or NTSC, 3 line
comb
1
YC or Composite, NTSC, 3 line comb (0H
& 1H)
2
YC or Composite, NTSC, 3 line comb (1H
& 2H)
3
YC or Composite, NTSC, 2 line comb (0H
& 1H)
4
YC or Composite, NTSC, (2 line) field
comb
5
YC or Composite, NTSC or PAL, field
comb
6
YC or Composite, NTSC, (2 line) frame
comb
7
YC or Composite, NTSC, frame comb
8
D1, Y or CBCR, 3 line comb
9
D1, Y or CBCR, 3 line comb (0H & 1H)
10
D1, Y or CBCR, 3 line comb (1H & 2H)
11
D1, Y or CBCR, 3 line comb (0H & 2H)
12
D1, Y or CBCR, (2 line) field comb
13
D1, Y or CBCR, field or 2 line comb
(0H & 1H)
14
D1, Y or CBCR, (2 line) frame comb
15
D1, Y or CBCR, Frame
The COMB signal can be produced in two ways. The first
method uses the comb fail detection circuits to select one of
several comb filter architectures. These comb filter architectures weight the three lines by varying degrees depending
upon the degree of picture correlation between the inputs to
the comb filter. The simple example in Table 4 shows how
this process works, in which upper denotes error comparisons between the two lines stores and lower denotes error
comparisons between the input and the first line store. The
0H, 1H, and 2H terms used in the mathematical description
of the comb filter selection refer to the position with respect
to the internal line stores. The 0H term is the undelayed
input, 1H is the output of line store 1, and 2H is the output of
line store 2.
In this example a 3 line comb is implemented when in the
flat areas of blue or yellow. However, when a difference
between the inputs is detected the 3 line comb filter adapts to
the 2 line comb filter whose inputs have the smallest difference. This illustrated on line n+4, at which time the comb
filter adapts to inputs from 1H (blue) and 2H (blue) and
ignores the 0H (yellow) inputs. In cases where there is a
difference between all inputs to the comb filter, a 3 line comb
filter is selected and the highest set of comb fail signals are
sent to the XLUT input logic.
This technique would work well if pictures only contained
vertical transitions, which is obviously not the case. Therefore the weighting of these comb filter taps, (0H, 1H, and
2H), are rarely just the simple ratios shown in Table 4. It is
worth noting that comb filters that use an even number of
lines in the comb filter architecture produce chrominance
and luminance signals that are vertically offset by one picture line, i.e. in the middle of the even number of lines used
in the comb filter input. While comb filters that use an odd
number of lines, in the comb filter architecture, the chrominance and luminance produced is referenced to the center,
i.e. the middle line, of the comb filter. This approach can
consequentially cause aliasing in decoding composite video
signals containing high frequency diagonal transitions. The
FAST register bit, when set LOW, filters the comb filter
selection to decrease the sensitivity of the adaption algorithm. The second method completely disables the adaption
between different comb filters, by setting the ADAPT[1:0]
register bits accordingly, see Table 5.
Table 4. Simple Example of an Adaptive Comb Filter Architecture
Error signals
Line
no.
48
Input col- upper
or
luma
upper
sat.
upper
hue
lower
luma
lower
sat.
lower
hue
Comb filter selection
n+6
blue
x
x
x
x
x
x
unknown without line n+7
n+5
blue
0
0
0
0
0
0
[0H/4] + [1H/2] + [2H/4]
n+4
blue
0
0
0
>0
0
180
n+3
yellow
>0
0
180
0
0
0
[0H/2] + [1H/2] + [0]
n+2
yellow
0
0
0
0
0
0
[0H/4] + [1H/2] + [2H/4]
n+1
yellow
0
0
0
>0
>0
>0
[0] + [1H/2] + [2H/2]
n
black
x
x
x
x
x
x
[0] + [1H/2] + [2H/2]
unknown without line n-1
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
In either of these methods, the “K” signal can be used to cross
fade between the YCOMB and the SIMPLE bandsplit signals.
The resulting comb filter equation can be expressed as:
Combed Luma = Simple + (K * Combed High
Frequency Luma)
Combed Chroma = Simple - (K * Combed High
Frequency Luma)
In the case of the chroma comb, the weighted combed high
frequency luma is subtracted from the SIMPLE high pass filter output to produce the combed chroma signal, and for
luma comb filters the weighted combed high frequency luma
is added to the SIMPLE low pass filter output to provide the
combed luminance signal.
Comb Fails
The inputs to the comb filter are monitored to detect discontinuities that would cause the comb filter operation to fail.
Whenever a significant failure is predicted, the comb filter
architecture is modified and an error signal proportional to
the discontinuity is produced. For flat areas of color, it is a
relatively simple to produce an error signal that switches
between the outputs of the comb filter and the simple band
split filter without visibly softening the picture horizontally
or vertically. However, as horizontal frequencies increase
during vertical transitions, so the decision for switching
between the comb and simple bandsplit decoder becomes
more complex.
A line based comb filter can separate the luma and chroma
signals from line repetitive composite video signals, with no
loss of luma or chroma bandwidth. However, if there is a vertical transition, i.e. a change from one scan line to the next,
as shown for a NTSC two line comb in Figure 17, a comb
fail occurs. The comb fail shown in Figure 17, clearly illustrates the resulting vertical smearing of the luma and chroma
signals.
In addition to the smearing, the resulting phase of the
chrominance signal with respect to the burst can cause hue
TMC22x5yA
errors in the demodulated picture. In this example, the
chrominance signal would be demodulated with a 180
degree phase error. Unlike the “simple” decoder technique
any errors in the comb filter decoding produce components
that if re-encoded will never reproduce the original composite video waveform. It is therefore imperative that the number and magnitude of comb fails be kept to its absolute
minimum. This is not possible with non-adaptive comb filter
architectures, and all vertical and diagonal transitions in the
picture will cause irreversible picture degradation. For this
reason, all the TMC22x5yA comb filter decoders implement
an adaptive comb filter architecture.
To aid in this decision making process, comprehensive comb
fail signals are generated and fed to a user-programmable
lookup table (XLUT). The output of the lookup table provides the control for the cross fade between the comb and
simple bandsplit decoder.
Comb Fail Detection
The traditional approach of using the low frequency data to
look for vertical luma transitions, and rectifying the high
frequency data to estimate vertical transitions in the chroma
provides adequate comb fail detection. However, chroma
signals that are equal in magnitude but 180 degrees apart in
phase, which can also have a small difference in luma level,
for example green and magenta, can produce undetected
comb fails in the comb filter output.
To overcome problems with simpler comb fail measurement
techniques, the TMC22x5yA generates an array of patented
comb fail and comb filter control signals. To produce these
signals each input to the comb filter is passed through a simple bandsplit decoder. This provides a luma signal from the
low frequency portion of the comb filter input, and the hue
(phase) and saturation (magnitude) from the high frequency
portion of the comb filter input. These signals are compared
and the differences in luma, hue, and saturation are used to
determine the type of comb filter used to generate the
YCOMB signal and to provide the cross fade control signal
“K”. The “K” signal can be weighted within the XLUT
lookup table, allowing the user to tailor the comb
filter response to their system requirements.
65-22x5y-58
Figure 17. Example of a Comb Fail Using a NSTC Two Line Comb Filter
REV. 1.0.0 2/4/03
49
TMC22x5yA
PRODUCT SPECIFICATION
Generation of the Comb Fail Signals
Luma Error Signals
The signals from the 3 low pass filters, 0HL, 1HL, and 2HL
are subtracted from one another to produce an error signal
proportional to the luma comb fail. The resulting signals
(0HL - 1HL), produces LYE, and either (1HL - 2HL) in
NTSC or (0HL - 2HL) in PAL produces UYE. The LYE and
UYE luma error signals are rectified if negative. In cases
where the luminance component is constant, the error will be
zero. Where the luminance goes from black to white over 2
lines, the error signal will go to its maximum value.
The luma error signals can be doubled to facilitate inputs
with low picture levels by setting the YESG register bit
HIGH. The resulting signal is clipped to ensure no overflow
occurs
provide the phase and magnitude of the in-phase and quadrature components of the high frequency data. These components are compared to determine the difference in phase and
magnitude between 0H & 1H in all configurations, LME and
LPE, and between 1H & 2H in NTSC or 0H & 2H in PAL,
UME and UPE. The magnitude error signals can be doubled
to facilitate inputs with low picture levels by setting the
CESG register bit HIGH. The doubled magnitude error
signals are limited to ensure no overflow occurs.
The algorithm used to separate the quadrature components
depends upon the relationship between the normalized subcarrier frequency and the number of pixels per line. This
algorithm is preset for either a NTSC/M or PAL/I subcarrier
frequency and a pixel data rate of 13.5MHz. It is therefore
necessary to compensate for other pixel data rates by selecting the appropriate default using the CEST[1:0] register bits.
Picture Correlation
Hue and Saturation Error Signals
In the past, comb decoders have relied upon comparing the
difference in chroma magnitude between two lines to determine a comb fail. In fact, this chroma signal is normally the
output of the high-pass or band-pass filter, and therefore contains all the high frequency luminance information as well.
As this signal was never demodulated, the sign bit was
immaterial and was used only to rectify the chroma signal.
This allowed chroma signals which where equal in magnitude but opposite in phase, and high frequency luminance
signals, to fool the comb fail circuit.
The TMC22x5yA uses a new, innovative approach to overcome this problem. To detect comb failures in the highfrequency portion of the video signal the outputs from the
three high-pass filters, 0HH, 1HH, and 2HH, are passed
through simple demodulators. The outputs from which
OHL
The degree of picture correlation depends upon the differences between the UYE, UME, and UPE upper error signals
and the LYE, LME, and LPE lower error signals, and is measured as a percentage of full scale error. In flat fields of color
you would have 0% error in picture correlation, however in
sharp vertical transitions say between yellow and blue you
would have large % errors between UYE and LYE and
between UPE and LPE, while there would be 0% error
between UME and LME.
Adapting the Comb Filter
In NTSC it is possible to switch from a 3 line comb to a 2
line comb, and then to a simple decoder output. The 3 line
comb to 2 line comb switch can be disabled, forcing the 3
line comb to switch directly to simple. The switching
between these two comb architectures is independent of the
Luma
Comparison
1HL
2HL
YESG
OHH
1HH
Chroma
Demodulation
&
Rectangular
to Polar
Conversion
2HH
UYE
LYE
YWBY
Hue
Comparison
UPE
Saturation
Comparison
UME
CESG
CSETBY
LPE
LME
65-22x57-59
CEST[1:0]
Figure 18. Generation of Upper and Lower Comb Fail Signals
50
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
ADAPT[1:0]
FAST
YCSEL
UYE
2:1
MUX
LYE
CFSEL[3:0]
Filter
UPE
LPE
Comb
Fail
Logic
YERR
PERR
UME
MERR
LME
STA[3:0]
CAT[1:0]
65-22x5y-60
Figure 19. Comb Filter Selection
mix signal, K. For 3-line Y/C comb filters, an external 1H
delay is required in the uncombed channel to compensate for
the comb filter delay.
This principle is equally true for NTSC frame and field based
comb decoders. The feature is not available for any of the
PAL comb filter architectures.
The Comb filter Adaption Threshold register bits CAT[1:0]
determine if 5%, 15%, 25%, or 50% errors in picture correlation is required to adapt the NTSC comb filter. In NTSC, due
to the 180 degree advance in subcarrier phase per line, it is
possible to switch between the 3 line comb and the choice of
either the upper two line comb or the lower two line comb. If
this switching occurs on a pixel by pixel basis the picture
will contain vertical alias components. This artifact can be
reduced by either setting the FAST register bit LOW, which
filters the comb filter selection, and/ or setting the CAT[1:0]
register bits to a higher percentage threshold.
The comb filter adaption is further controlled by the
ADAPT[1:0] register bit selection, when the COMB[3:0]
register bits select a 3 line comb. These bits control if the
comb filter adapts from a 3 line comb to the best of the upper
or lower 2 line combs, from a 3 line comb to just the lower 2
line comb, performs a fixed 3 line comb, or implements a
best of two 3 line combs in PAL. If the COMB[3:0] register
bits select one of the 2 line comb filters, the ADAPT[1:0]
register bits are ignored, and no adaption is implemented.
The CFSEL[1:0] signal, shown in Figure 19, controls which
comb filter is selected on a pixel by pixel basis, and can be
externally monitored by reading CFSTAT[1:0] in register
4Bh.
REV. 1.0.0 2/4/03
Table 5. Adaption Modes
ADAPT[1:0]
Function
00
Adapts to the best of 3 types of line
based comb filters in NTSC only.
01
3 line (tap) comb always adapts to
lower 2 line (tap) comb, when the 3 line
(tap) comb fails. Normally used with
NTSC field and frame based comb
filters.
10
3 line (tap) comb only. Never adapts to
a 2 line(tap) filter. The higher set of
comb filter error signals are sent to the
XLUT. NTSC or PAL comb filter.
11
Adapts to best of two 3 line comb filters
in PAL only.
XLUT
The comb fail signals control both the comb filter adaption
and the cross fade between the adaptive comb filter output
YCOMB and the SIMPLE bandsplit signal. Which of the fail
signals is fed to the XLUT is determined by which comb
filter is selected in NTSC. When a 3 line comb filter is
selected, the larger set of error signals are sent to the XLUT,
when a upper 2 line comb is selected UYE, UME, and UPE
error signals are selected, and when a lower two line comb
filter is selected the LYE, LME, and LPE error signals are
selected.
51
TMC22x5yA
PRODUCT SPECIFICATION
XFEN
YERR
XLUT
Input
Select
PERR
X[7:0]
2:1
MUX
XLUT
K[4:0]
Filter
MERR
65-22x5y-61
XIP[1:0]
Figure 20. XLUT Input Selection
For PAL comb filters the LYE, LME, and LPE errors signals
are always selected by default. In this way the error signals
into the XLUT always represent the comb filter being implemented. The resolution of the error signals selected is controlled by the XIP[1:0] register bits as shown in Table 6:
XLUT Input Selection. The position of these error signals on
the XLUT input address X[7:0] is also shown.
Table 6. XLUT Input Selection
Table 7. XLUT Output Function. (cont.)
XLUT
OUTPUT
16
:
K
16 - 50% Bandsplit, 50% Comb
:
29
29
30
30
31
32 - 100% Comb
XIP[1:0]
Function
00
2 bits of phase error (X[7:6]), 3 bits of
chroma (X[5:3]) and luma magnitude error
(X[3:0]).
The special function assigned to K = 0 is programmed into
the XSF[1:0] register bits, as shown in Table 8.
01
4 bits of chroma (X[7:4]) and luma
magnitude error (X[3:0]).
Table 8. XLUT Special Function Definitions
10
3 bits of phase error (X[7:5]), 3 bits of
chroma magnitude error (X[4:2]), and 2
bits of luma magnitude error (X[1:0]).
11
4 bits of phase error (X[7:4]) and chroma
magnitude error (X[3:0]).
The selected comb fail signals are translated by the userprogrammed configuration within the 256*5 XLUT into the
mix signal (K) which controls the 30 levels of cross-fade
between the weighted comb filter and the band split filters.
The 1 to 31 mix signal is modified on the input to the crossfade to produce a 0 to 32 control signal, as shown in Table 7.
Table 7. XLUT Output Function.
XLUT
OUTPUT
52
K
0
Special function (e.g. luma comb and HPF
on chroma)
1
0 - 100% Bandsplit
2
2
3
3
:
:
KIP1-0
XLUT special function selection
Y
C
00
comb
simple
01
simple
comb
10
flat with notch
simple
11
flat with notch
comb
The “Flat with notch” selection passes the FLAT input
through onto the luminance channel and selects the notch
filter, centered at 0.25 of the normalized clock frequency.
This mode is therefore only useful with inputs at 4*Fsc or in
cases when a notch at 0.25 of the normalized clock
frequency is adequate for application.
The XLUT output, is fed through a bypassable low-pass
filter KLPF to avoid switching between comb and simple
decoders on a pixel by pixel basis. When the special function
is selected (K = 0) the input to the KLPF is held and the filter
is automatically bypassed. The output of the XLUT can be
externally monitored by reading XOP[4:0] in register 4Bh.
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
.
U Data
Gaussian
LPF
–
Chrominance
sin(wt)
V Data
Gaussian
LPF
65-22x5y-62
Burst
Locked Loop
cos(wt+φ)
Figure 21. Block Diagram of Digital Burst Locked Loop
Digital Burst Locked Loop
The digital burst locked loop provides sine and cosine signals
which are phase locked to the incoming burst signal. These
sine and cosine signals are used to demodulate the chrominance data, producing the U and V color-difference signals.
The U data are phase-referenced to sin(wt) and the V data to
cos(wt). The demodulated signal is passed through a low pass
filter to remove signals at twice the subcarrier frequency.
The magnitude of the U and V data within the demodulated
burst signal provides the error signal which, after filtering, is
used to adjust the frequency and/or phase of the subcarrier
DDS. The output of the subcarrier DDS is translated into sine
and cosine signals in ROM-based lookup tables.
The PALODD signal is low on lines without the 180 degree
phase advance in the modulated V signal, termed NTSC
lines, and high for lines with the 180 degree phase advance,
termed PAL lines. This signal is used in the burst locked loop
to advance the phase of the cosine table on PAL lines. PALODD is always low for NTSC.
Color Kill Counter
The demodulated U and V components are compared to a
programmable burst level threshold. If both the U and V data
fall below this threshold, a color kill flag is set high. The
color kill counter is incremented once per line if the color
kill flag is high. If the count reaches 127 within one field, the
color kill circuit becomes active during the next field group.
When this occurs, the input video will be passed unaltered
on the luminance channel and the color difference signals
will be set to chroma black.
The color kill signal remains active until a field with less
than 127 lines without burst is encountered, at which time,
during the next vertical blanking period, the decoder is reset.
The operation of the color kill logic can be monitored externally by reading the MONO register bit in register 44h. The
MONO bit is HIGH for composite and YC video signals and
LOW for monochrome signals.
Frame Bit
NTSC
The middle bit (frame bit) of the field count is determined,
by the phase of the subcarrier on a given pixel and on a given
line. The signal used to determine this is NFDET (New Field
DETect), and occurs when the line count is zero and the pixel
count is one of four programmable pixel positions, zero, one,
two, or three.
PAL
The frame bit in PAL is detected through the Bruch blanking
sequence. The error signal control circuit generates a color
kill flag whenever a line is detected without a burst. It is
therefore possible to compare this signal with specific line
idents to determine the field sequence in both PAL-I and
PAL-M. A set of specific patterns determine the correct
phase of FID1; if any of these patterns is detected then FID1
is forced to a known state and then flywheels until the next
fixed pattern is detected.
Table 9. PAL-B,G,H,I Bruch Blanking Sequence
Internal
line #
Burst
present
Internal
frame #
Internal field #
5
No
0 or 2
0 or 4
309
No
0 or 2
0 or 4
6
Yes
0 or 2
1 or 5
309
No
0 or 2
1 or 5
5
Yes
1 or 3
2 or 6
309
Yes
1 or 3
2 or 6
6
No
1 or 3
3 or 7
309
Yes
1 or 3
3 or 7
The frame bit is low for frames 0 and 2 and high for frames 1
and 3.
Field Flag, FLD
The FLD signal is the lsb of the field count FID2-0 and is
LOW for fields where the first vertical sync occurs in the first
half of the line and is HIGH for fields when it occurs in the
second half of the line. This signal is synchronized with the
frame and color frame flags in the FID generator.
REV. 1.0.0 2/4/03
53
TMC22x5yA
PRODUCT SPECIFICATION
Table 10. PAL-M Bruch Blanking Sequence
Internal
line #
Burst
present
Internal
frame #
Internal field #
7
No
0 or 2
0 or 4
258
Yes
0 or 2
0 or 4
0
259
Yes
1 or 3
3 or 7
65-22x5y-63
3 or 7
-70
Normalized Frequency
Figure 22. Gaussian Low Pass Filters
The frame bit is low for frames 0 and 2 and high for frames 1
and 3.
PAL Color Frame Bit
One of two programmable 16 bit system phase offsets can be
added to the subcarrier oscillator between SAV and EAV.
The selection is made by the BUFFER pin. This feature
allows the user to change the picture hue on known frames
without affecting the burst locked loop.
System Monitoring of the Burst Loop Error
The burst loop error signal is stored once per line in an 8 bit
register that can be accessed over the microprocessor port.
This allows the user to check for non-mathematical PAL inputs and to the change the decoder architecture from framebased to line-based or simple decoder depending on this information.
Demodulation Low Pass Filter
There are two different demodulation low pass filters that
can be selected under software. For PAL inputs with normalized subcarrier frequencies greater than 0.3 of the sampling
frequency, it is recommended you use “demodulator filter 2”
to stop aliasing of the second harmonic of the demodulation
chrominance signal and the baseband color difference signals. Gaussian filters are used for both demodulation filters
as they have no negative coefficients and therefore have no
undershoots or overshoots which could cause in-band
ringing.
54
-2
Demodulator Filter 1
-4
-6
Demodulator Filter 2
-8
-10
0.00
Hue Control
0
Attenuation (dB)
The PAL color frame bit is the msb of the field count, FID2.
In NTSC this is always low, as NTSC has only a 4 field sequence. For both PAL-I and PAL-M inputs, the PAL color
frame bit is determined in the same way the frame bit is determined in NTSC, by using the phase of the subcarrier on a
given pixel and on a given line.
0.50
1 or 3
65-22x5y-64
Yes
0.16
7
-60
0.40
2 or 6
0.14
1 or 3
0.12
No
0.30
258
0.10
2 or 6
0.20
1 or 3
0.08
Yes
Demodulator Filter 2
-50
0.06
7
-40
0.10
1 or 5
0.04
1 or 5
0 or 2
Demodulator Filter 1
-30
0.02
0 or 2
No
-20
0.00
No
Attenuation (dB)
7
259
-10
Normalized Frequency
Figure 23. Gaussian LPF Passband Detail
Bypassing the Chrominance Demodulator
The demodulation of the chrominance signal needs to be
bypassed when the decoder is processing CBCR component
data or when a YC output is required. The bypass operation
is controlled by the DMODBY register bit.
Bypassing the Demodulation Low Pass Filter
The demodulation low pass filter needs to be bypassed when
processing CBCR component data or when a YC output is
required. The CBCR data can also be passed through the
Gaussian filter if the bandwidth needs to be reduced. The
bypass operation is controlled by the GAUBY register bit.
Chrominance Coring
Chrominance coring, when active, sets the lsbs of the
chroma channel (below a programmable threshold) to zero.
VMCR5 Operation
When VMCR5 is HIGH, the decoder will grab one line of
video in LSTORE1. This effectively removes the comb filter
from the decoding process, and the comb filter output is
forced to simple mode.
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Output Processor
Mixed Sync
+
X
SGx[9:0]
–
Y Data
VIDEOB
LPF
256
240
Adaptive Luma
Notch Filter
–
PED[7:0]
B/Cb Data
Fixed (B-Y)
Gain Stage
R/Cr Data
X
UGx[10:0]
V Data
Output
Formatter
X
X
X
G/Y Data
YOFF[8:0]
ANT[1:0] YSEL ANEN YGx[9:0]
Clamp
Circuit
CLMP[1:0] VCLPEN
U Data
+
X
Fixed (R-Y)
Gain Stage
65-22x5y-65
VGx[10:0]
Figure 24. Output Processor Block Diagram
Clamp Circuit
A clamp pulse generated by the Burst Gate signal is used to
grab either a sample of the low-pass-filtered luma during the
video back porch, the signal on VIDEOB, or one of two
internally generated levels. The selection is made by the
CLMP[1:0] register bits.
Table 11. Blanking Level Selection
CLMP[1:0]
Blanking Selection
00
Internal 240 level
01
Internal 256 level
10
External VIDEOB Input
11
Internal LPF Output
The blanking level is subtracted from the decoded luma.
If the sign is negative, the result is assumed to be mixed sync
and is passed through a delay and into the sync gain stage
within the output matrix. If the sign is positive, the result is
assumed to be pure luma (blanking to peak white) and is fed
to the pedestal removal circuit.
Pedestal Removal
The 8 bit programmable pedestal is subtracted from the pure
luma signal. The negative super black signals are clipped to
zero when register 0Ah bit 4 is set LOW, or the super black
signals are passed through the luma scalar when register 0Ah
bit 4 is HIGH.
Clamp Generator
The TMC22x5yA has the unique option to output a negative
going clamp pulse that is 0.5 µsec wide. This pulse can be
output on the AVOUT pin by placing a HIGH on register 24
bit 7. The pulse’s position relative to HSYNC can be varied
by register 25. This value is the number of PCK clock cycles
after an HSYNC that the pulse will be output to the pin. The
REV. 1.0.0 2/4/03
clamp pulse can be used to control where an analog clamp
circuit grabs the analog reference to establish the correct
voltage level into the A/D. Usually the clamp pulse is generated on the back porch or duing the sync tip of a video line.
Adaptive Notch Filter
The PAL line-locked comb decoder can never provide
perfect subcarrier cancellation due to the 25Hz offset in the
subcarrier frequency. This 25Hz offset causes residual and
phase modified subcarrier to be left on the luminance signal
which can produce a visible dot crawl on flat areas of color.
However, for all comb filter structures, the quality of the
comb depends on the quality of the sampling clock, as line to
line clock jitter will also cause small phase changes between
the inputs to the comb filter. It is therefore possible that
NTSC comb decoders may also require some coring of the
luma output. To meet the wide range of sample frequencies
that the decoder must deal with two separate coring filters
are selectable.
The luma signal from the pedestal stripper is compared
against the preceding pixel to detect the magnitude change
between pixels. This magnitude difference will be almost
zero for flat areas of picture, and large for high frequency
changes in the picture. The magnitude difference is compared to one of four programmable thresholds. The programmable threshold is selected by the ANT1-0 register bits as
shown in Table 12.
Table 12. Adaptive Notch Threshold Control
ANT1-0
Magnitude difference
00
less than 16
01
less than 12
10
less than 8
11
less than 4
55
TMC22x5yA
PRODUCT SPECIFICATION
If either of the error signals indicates that the magnitude
difference is above the programmed threshold, or if ANEN is
LOW, the adaptive notch filter is bypassed. The output of the
adaptive notch filter is rounded to 8 or 10 bits, or the luma
data that bypasses the coring filter is truncated to 8 or 10 bits
depending upon the CORO register bit.
0
Programmable U Scalar
The U scalar (UGx) provides the weighting required to
produce (B-Y) or CB from the demodulated U signal.
hence
(B-Y) = UGx * U
where UGx = gain / 0.493, and
CB = UGx * U
-20
Adaptive Notch
Filter 1
Adaptive Notch
Filter 32
-30
where UGx = (gain * 448) / Umax
-40
Adaptive Notch
Filter 2
-60
0.40
0.30
0.20
0.10
0.00
-70
65-22x5y-09
UGx has a scaling range of 0 to (2047/256).
-50
0.50
Attenuation (dB)
-10
Programmable V Scalar
The V scalar (VGx) provides the weighting required to
produce (R-Y) or CR from the demodulated V signal.
hence
Normalized Frequency
(R-Y) = VGx * V
Figure 25. Adaptive Notch Filters
where VGx = gain / 0.877, and
Luma Notch Filter
The simple luma notch filter is centered at 0.25 of normalized frequency, it therefore intended for use only in the subcarrier mode (4 * fSC) and for limited use with 13.5MHz
NTSC as the subcarrier sits at 0.265 of normalized frequency. The notch filter is enabled by setting the NOTCH
register bit HIGH.
where VGx = (gain * 448) / Vmax
VGx has a scaling range of 0 to (1023/256).
Programmable Y Scalar
The Y scalar (YGx) provides the scaling for the luminance
signal if the output is YCBCR, or controls the magnitude of
the RGB output along with the U scalar and V scalar. It is not
possible to control the magnitude of the RGB signals independently.
0
-10
-20
-30
YGx has a scaling range of 0 to (1023/256).
-40
65-22x5y-67
-50
-60
0.40
0.30
0.20
0.10
0.00
-70
0.50
Attenuation (dB)
CR = VGx * V
Normalized Frequency
Figure 26. Luminance Notch Filter
Matrix
The magnitude of the decoded luminance and color difference signals will vary, not only with the standard, but also
with the input mode. For this reason the output matrix
contains programmable multipliers, and not just fixed
scaling factors. The following sub sections explain the different scalar in the output matrix. The gain term in the Y, mixed
sync, U and V scalar is the same - only the weighting makes
them different. The scalar are capable of independently
providing 6dB of gain if required.
Programmable MS Scalar
The sync scalar (SGx) provides the scaling for the sync
signal if the output requires sync on RGB. The programmed
sync scaling factor is used during the horizontal and vertical
burst blanking periods. During the active lines, the luma
scaling factor is used to allow scaling of “super blacks” etc.,
which will be passed down the mixed sync path because they
fall below the clamp level.
SGx has a scaling range of 0 to (1023/256).
Fixed (B-Y) and (R-Y) Scalars
These two scalars are zero when the output is YCBCR and
provide the (B-Y) and (R-Y) weighting when the output is
RGB. These are fixed scaling factors and are derived from
the following equations.
(G-Y) = - [(0.299/0.587) * (R-Y)]
- [(0.114/0.587) * (B-Y)]
or
(G-Y) = - [(1043/2048) * (R-Y)]
- [(398/2048) * (B-Y)]
56
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Y Offset
The 8 bit Y offset adds any offset required in the Y or RGB
data outputs. For example 64 (16) for the 64 (16) to 940
(235) 10 bit (8 bit) 601 outputs. When the output is YCBCR
this offset is applied to the luminance data only. The Y offset
also provides the blanking level for RGB
outputs with syncs.
Decoder Output
CCIR 601 Spec
Color
Y
CB
CR
Y
CB
CR
Red
325
-150
447
326
-151
448
Blue
163
448
-73
164
448
-72
Black
64
0
0
64
0
0
PAL digital composite input and RGB (0-1023) outputs:
Matrix Limiters
The different limiters are listed below, 10 bit data is
assumed.
Color
Y
U
V
White
572
0
0
Table 13. Matrix Limiters
Yellow
507
-250
57
Comments
Cyan
401
84
-352
00
RGB output format, limited from 0 to 1023
Green
336
-165
-295
01
YCBCR output format, Y limited from 0 to
1023 and CBCR limited to +/- 511.
Magenta
236
165
295
Red
171
-84
352
10
RGB output format, limited from 64 to 940
Blue
65
250
-57
11
YCBCR output format, Y limited from 64 to
940 and CBCR limited to +/- 448
Black
0
0
0
LMT1-0
The nominal scaling factors are simply:
Examples of Output Matrix Operation
YGx = 1023/572 = 1 + (202/256)
UGx = (1023/572)*(1/0.492) = 3 + (163/256)
VGx = (1023/572)*(1/0.877) = 2 + (10/256)
YOFF= 0
PED = 0
From the SMPTE-170M specification:
Color
Y
U
V
White
584
0
0
Yellow
523
-236
54
Color
G
R
B
Cyan
423
79
-332
White
1023
1023
1023
Green
361
-156
-278
Yellow
1023
1023
0
Magenta
267
156
278
Cyan
1023
0
1023
Red
205
-79
332
Green
1023
0
1
Blue
105
236
-54
Magenta
0
1023
1022
Black
44
0
0
Red
0
1023
1
Blue
0
0
1023
Black
0
0
0
YCBCR data ranges are:
Y data range is 64 to 940 (876)
CBCR data ranges are 64 to 960 (+/- 448)
It is also possible with the architecture supplied to use the
limiters on the output of the matrix to clip the output video
deliberately by using a slightly larger gain than is required.
The Y_Offset can achieve the same by setting its value to be
one lsb less than the minimum clip level.
Matrix programming:
YGx = (876 / 540) = 1 + (159/256)
UGx = (448 / 236) = 1 + (230/256)
VGx = (448 / 332) = 1 + (89/256)
YOFF = 64
PED = 44
Color
Buffer Registers
Decoder Output
CCIR 601 Spec
Y
CR
Y
CB
CB
CR
White
939
0
0
940
0
0
Yellow
841
-448
73
840
-448
72
Cyan
678
150
-447
678
151
-448
Green
578
-296
-376
578
-296
-375
Magenta
426
296
376
426
296
375
REV. 1.0.0 2/4/03
The BUFFER pin allows the user to externally switch
between two sets of internal registers that have the same
function. This register buffering allows the matrix gain,
picture hue, and luma offset to be changed at a known time
relative to the input data.
Registers 17 to 1D are selected when the BUFFER pin is
LOW and registers 27 to 2D are selected when the BUFFER
pin is HIGH. If the msb of the decoder product code DPC2 is
LOW, an 8 bit decoder has been selected and the bottom 2
bits of registers 17 to 1A and 27 to 2A are forced to zero.
57
TMC22x5yA
PRODUCT SPECIFICATION
Simple Luma Color Correction
If the YBAL register bit is set HIGH, and the luma data
reaches or exceeds the luma limits, there should be no CBCR
or UV data at that time; therefore the color data are set to
ZERO. If YBAL is set LOW then the CBCR/UV data are
unaffected by the luma data.
CBCR MSB Inversion
CBSEL, to produce the multiplexed CBCR data stream at the
PCK clock rate. If the input was initially D1 then the
dropped samples will be the interpolated samples produced
by the chroma interpolation filter. If however the CBCR data
are simply weighted UV data then the sample dropped
demodulated color difference signals (UV) will alias around
0.25 of the normalized sample frequency.
Multiplexed YCBCR Output (TRS Words
Inserted)
The msb of the CBCR data can be inverted by setting the
MSBO register bit HIGH. As this would affect the chroma
blanking level, this circuit appears at the output of the
MATRIX circuit.
Output Rounding
For compatibility with 8 bit systems, the output of the matrix
can be rounded to 8 bits by setting the RND8 register bit
HIGH.
Output Formats
RGB Outputs
The RGB data are simply passed through to the decoder output. When the DRSEN register bit is HIGH the DRS data are
inserted into the green data path only.
YUV Outputs
The YUV data are simply passed through to the decoder output. When the DRSEN register bit is HIGH the DRS data are
inserted into the luminance data path only.
YCBCR Outputs
The YCBCR data can be output in 3 ways, depending upon
the CDEC, F422, and YUVT register bits. These output
modes are summarized in .
When CDEC is HIGH and F422 is HIGH, the G/Y output is
set to 64 and the B/U output is set to 512 between the EAV
TRS data word and the first preamble word of the SAV TRS,
i.e. during the digital horizontal blanking period. When
YUVT is HIGH, R/V is set to 512, 64, 512, 64, etc., starting
after the EAV TRS data word and finishing before the SAV
preamble.
Decimating CBCR Data
Whenever the CDEC register bit is set HIGH the B/U and
R/V data are simply sample dropped, with respect to
When both the CDEC and YUVT register bits are HIGH the
Y, CB, and CR component data are multiplexed into a single
27MHz (PXCK) data stream with embedded TRS words.
The TRS words are generated based on the HSYNC or
VSYNC pulses provided to the decoder, and the internally
derived horizontal blanking (HBLK), vertical blanking
(VBLK), and the field flag (FLD). This mode of operation is
only available if a line locked PXCK clock, at 27MHz, is
provided. The TRS words will be generated with respect to
the HSYNC\ signal as per the ANSI/SMPTE 125M-1992
and CCIR 656 specifications.
YC Outputs
The YC data are passed through to the decoder output. When
the DRSEN register bit is HIGH the DRS data are inserted
into the luminance data path only. The luminance appears on
G/Y, chrominance is on B/U and the R/V output is set to
zero, by setting the V_scalar to zero.
The LDV Clock
The decoder can accept clocks at either the pixel clock rate
(PCK) or at twice the pixel clock rate (PXCK). In the cases
where the clock provided is PXCK, for example the genlock
mode, the output data still needs to be at the PCK clock rate.
To aid in the design of external circuitry a LDV clock is provided if the LDVIO register bit is LOW, if LDVIO is HIGH
then the LDV pin becomes an input for an external clock.
If an external LDV clock is employed the user must ensure
that the rising edge of the external LDV meets the specified
setup and hold times relative to the input CLOCK pin. The
selection of which clock to use on the decoder output is set
by the OPSEL register bit. When OPSEL is set LOW the
output is clocked at the same rate as the clock on the
CLOCK pin, and when OPSEL is set HIGH the output is
clocked by the internal or external clock on the LDV pin.
Table 14. Output Format
58
CDEC
YUVT
F422
G/Y
B/U
R/V
Comments
0
x
x
G or Y
B or CB
R or CR
[4:4:4] data
1
0
0
Y
CB
CR
[4:2:2] data
1
0
1
Y
CBCR
0
[4:2:2] data
1
1
x
Y
CBCR
D1 data
[4:2:2] data & D1 output
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Sync Pulse Generator
HBLK (Horizontal Blanking Period)*
The vertical and horizontal references to the decoder can be
from external VSYNC and HSYNC pulses, decoded from
TRS and TRS-ID words, or from the internal sync separator
which extracts the sync information from the digitized input
video.
The sync pulse generator (SPG) provides all the clock and
enable pulses required to synchronize the decoder operation
to the incoming video signal. These pulses are described
below, along with the microprocessor data required to
control them.
Internal Field and Line Numbering Scheme
The internal line numbering of the digital decoder differs
from the standard video line numbering as shown in the
following tables. The internal line numbers for a 3 line comb
advance the numbering by 1 line with respect to the input,
but are identical with respect to the internally one line
delayed decoded video.
Table 15. NTSC Field and Line Numbering
Standard
Field #
Standard
Line #
Internal
Field #
Internal Line
#
1&3
1-3
1&3
260 - 262
1&3
4 - 263
0&2
0 - 259
2&4
264 - 265
0&2
260 - 261
2&4
266 - 525
1&3
0 - 259
Table 16. PAL B,G,H,I Field and Line Numbering
Standard
Field #
Standard
Line #
Internal
Field #
Internal Line
#
1&5
1 - 312
0&4
0 - 311
2&6
313 - 625
1&5
0 - 312
3&7
626 - 937
2&6
0 - 311
4&8
938 - 1250
3&7
0 - 312
Table 17. PAL M Field and Line Numbering
Standard
Field #
Standard
Line #
Internal
Field #
Internal Line
#
1&5
1 - 262
0&2
0 - 261
2&6
263 - 525
1&3
0 - 262
3&7
1 - 262
0&2
0 - 261
4&8
263 - 525
1&3
0 - 262
The horizontal blanking period is LOW between the start of
SAV and the end of EAV. This signal is used in several
places:
a) To clear the SYSPH offset when LOW, this is required
for correct operation of the subcarrier phase locked loop,
b) To aid in the comb filter management,
c) To remove the burst envelope on the demodulated UV
data,
d) To remove the syncs on the BLUE and RED outputs.
BBLK (Vertical Burst Blanking Period)
The vertical burst blanking blanks the lines with no burst
from the burst phase locked loop. This signal is decoded from
the line ident, LID4-0, and is modified by the video standard
and the field count.
MBLK (Mixed Blanking)
This signal is used in the matrix to switch between the
sync scalar and the luma scalar. The MBLK signal is active
whenever HBLK is active or becomes active when VBLK
becomes active. MBLK is also active in PAL on line 310
when both VACT1 and FLD are HIGH and in NTSC and
PAL M on line 259 when VACT2 is HIGH and FLD is LOW.
FLD*
The FLD is LOW for field 1 and HIGH for field 2.
LID4-0*
The line ID signals are used in the vertical comb filter
management to control the comb filter on the leading and
trailing lines of active video around the vertical blanking
period, to start and stop the VINDO operation, and in generating the vertical blanking and burst blanking periods.
VACT2*
VACT2 is HIGH during the second half of all active lines.
GRABF*
The GRABF signal goes HIGH when the internal field count
is equal to the programmed field number for the GRAB
operation. f a pixel grab is being, this signal is held HIGH to
not inhibit the GRABS signal on each line.
GRABL*
The GRABL signal goes HIGH when the internal line count
is equal to the programmed line number for the GRAB
operation. If a pixel grab is being performed, this signal is
held HIGH to not inhibit the GRABS signal on each line.
GRABP*
The GRABP signal goes HIGH when the internal pixel count
is equal to the programmed pixel number for the GRAB
operation.
*
HSTBG (Burst gate)
DVSYNC and DHSYNC (Output Pins)
The burst gate starts the 16 clock period average of the
demodulated burst envelope. The position of the burst gate is
programmed into a register as the number of clock periods
from the falling edge of sync to the burst envelope.
The DVSYNC and DHSYNC signals are active when GCR2
is LOW. When GCR2 is HIGH these signals are three stated.
Three line comb based decoders have an inherent line delay,
therefore the input VSYNC and HSYNC signals can not be
just delayed by a few registers and output as DVSYNC and
DHSYNC: they need to be delayed by one complete line. In
all other comb filter configurations the DVSYNC and
*
Signal is available over the microprocessor data bus.
REV. 1.0.0 2/4/03
59
TMC22x5yA
PRODUCT SPECIFICATION
DHSYNC are referenced to the input data (0HFLAT) and not
the output of the LSTORE1, i.e. 1HFLAT.
The duration of the DVSYNC signal is fixed to one line and
the duration of the DHSYNC signal is 64 clock periods.
Both these signals are generated by the internal horizontal
and vertical state machines.
The falling edge of these signals relative to the data matches
the requirements of the TMC22x91 family of digital encoders.
Table 19. Vertical Burst Blanking Period
Internal field no
Internal line no
0,2
0-5
NTSC
259 - 261
1,3
0-6
260 - 262
PAL
0&4
0-5
309 - 311
AVOUT Active Video (Output Pin)
1&5
The decoder produces an active video signal starting 4 PCK
before the programmed start of active video and ending 4
PCK after the programmed end of active video. This signal is
used in both the video mixer (TMC22x8x) family and the
digital encoder (TMC22x9x) family. The end points of this
signal are flagged by the internally generated SAV and EAV
signals.
**
309 - 312
2&6
0&4
1&5
2&6
0-5
0-6
260 - 262
PAL
0, 2, 4, & 6
0 - 21
310 & 311
1, 3, 5, & 7
PAL-M
0, 2, 4, & 6
1, 3, 5, & 7
3&7
260 - 262
LID4-0 List of Line Idents
The line numbers required to produce all the decoder control
signals are summarized in
Table 20. Table of Line Idents, LID[4:0]
Line no:
LID4-0
311 & 312
0
00
0-5
1-4
01
260 & 261
5
02
0-6
6
03
260 & 262
7
04
8
05
The vertical burst blanking blanks the lines with no burst
from the burst phase locked loop. This signal is controlled by
the video standard and the field count. The burst blanking
signal is active low.
Signal is available over the microprocessor data bus.
60
0-6
0 - 22
BBLK (Vertical Burst Blanking Period)
**
0-6
258 & 261
260 & 261
1,3
0-7
259 - 262
Internal line no
0,2
0-7
259 - 261
Table 18. Vertical Blanking Period
NTSC
0-6
310 - 312
The vertical blanking period conforms to the CCIR 656
specification for D1 component data streams. This signal is
decoded from the line ident, LID4-0, and is active low.
Internal field no
0-4
310 & 311
3&7
PAL-M
VBLK (Vertical Blanking Period)
0-5
9 - 16
06
17
07
18
08
19 - 21
09
22
0A
23
0B
24
0C
25 - 257
0D
258
0E
259
0F
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
STS: The number of pixels between sync pulses
Table 20. Table of Line Idents, LID[4:0] (cont.)
Line no:
LID4-0
260 & 261
10
262
11
STB: The number of pixels between the nominal mid point
of sync and the start of the 16 pixel burst gate. This value is
modified depending upon the mode of operation.
263 - 307
12
Table 21. Timing Offsets
308
13
Standard
309
14
310
15
311
312
Mode
Offset required
x
Genlock
-8
x
Line locked
-8
16
x
Subcarrier
-22
17
PAL
D2 mode
-12
NTSC
D2 mode
-8
x
D1 mode
+12
Timing Parameters
Subcarrier Programming
BTV: The number of pixels between the start of the 16 pixel
burst gate and the nominal start of active video.
The color subcarrier is produced by an internal 28 bit Direct
Digital Synthesizer (DDS) which is phase locked to the burst
signal of the digitized video input. The nominal frequency is
programmed into the DDS as follows:
AV: The number of active pixels in the active video line.
The difference between the sum of STB+BTV+AV subtracted from STS provides the nominal front porch.
FREQ = (number of subcarrier cycles per line / number of
pixels per line) * 2^28
Horizontal and Vertical Timing Parameters
An example would be NTSC subcarrier mode
When external horizontal and vertical syncs are provided the
timing shown in Figure 28 is required to synchronize the
internal state machines to beginning of a field (3, 5, or 7).
For field 2 (4, 6, or 8) the falling edge of VSYNC must occur
at least 2 clock periods but not more than (H-2) clock periods
after the falling edge of HSYNC, where H is the total number of pixels in an active video line.
FREQ = (227.5 / 910) * 2^28 = 4000000 hex
Horizontal Timing
The horizontal video line is broken down into four horizontal
timing parameters.
STB
BTV
AV
STS
65-22x5y-68
Figure 27. Horizontal Timing
REV. 1.0.0 2/4/03
61
TMC22x5yA
PRODUCT SPECIFICATION
CLOCK
tHP
tSP
HSYNC
VSYNC
65-22x5y-12
Figure 28. External HSYNC and VSYNC Timing for Field 1 (3, 5, or 7)
Vertical Blanking
256
257
UVV
17
18
UVV
UVV
FIELDS 1 AND 3
•••
258
259
260
0
1
2
3
4
5
6
EE
EE
EE
SS
SS
SS
EE
EE
EB
UBB
UVV
15
16
UBB
UBB
HSYNC
VSYNC
FLD
258
UVV
259
UVE
FIELDS 2 AND 4
260
261
0
1
2
3
4
5
6
7
EE
EE
ES
SS
SS
SE
EE
EE
EB
UBB
•••
17
18
19
UVV
UVV
UVV
16
UBB
HSYNC
VSYNC
FLD
65-22x5y-69
Figure 29. NTSC Vertical Interval
62
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
310
309
UVV
-VE
308
309
TMC22x5yA
FIELDS 1 AND 5
311
312
0
1
2
3
4
EE
EE
SS
SS
SE
EE
EE
5
-BB
6
UBB
•••
21
•••
UBB
22
23
24
25
UVV
UVV
UVV
UVV
23
24
HSYNC
VSYNC
FLD
UVV
-VV
FIELDS 2 AND 6
310
311
0
1
2
3
4
5
6
7
•••
21
22
EE
EE
ES
SS
SS
EE
EE
EB
UBB
UBB
•••
UBB
UBB
UVV
UVV
22
23
24
25
UVV
UVV
UVV
UVV
23
24
UVV
UVV
HSYNC
VSYNC
FLD
309
310
UVV
-VE
308
309
FIELDS 3 AND 7
311
312
0
1
2
3
4
EE
EE
SS
SS
SE
EE
EE
5
UBB
•••
6
UBB
•••
21
UBB
HSYNC
VSYNC
FLD
UVV
UVV
FIELDS 4 AND 8
310
311
0
1
2
3
4
5
6
7
•••
21
22
EE
EE
ES
SS
SS
EE
EE
EB
-BB
UBB
•••
UBB
UBB
HSYNC
VSYNC
FLD
65-22x5y-70
Figure 30. PAL-B,G,H,I,N Vertical Interval
REV. 1.0.0 2/4/03
63
TMC22x5yA
PRODUCT SPECIFICATION
258
259
UVV
FIELDS 1 AND 5
UVV
17
260
261
262
0
1
2
3
4
5
6
7
8
•••
16
EE
EE
EE
SS
SS
SS
EE
EE
EE
-BB
-BB
UBB
•••
UBB
UVV
HSYNC
VSYNC
FLD
259
258
UVV
FIELDS 2 AND 6
-VE
260
261
0
1
2
3
4
5
6
7
8
•••
16
EE
EE
ES
SS
SS
SE
EE
EE
EB
-BB
UBB
•••
UBB
17
18
UVV
UVV
HSYNC
VSYNC
FLD
258
259
UVV
FIELDS 3 AND 7
-VV
17
260
261
262
0
1
2
3
4
5
6
7
8
•••
16
EE
EE
EE
SS
SS
SS
EE
EE
EE
-BB
UBB
UBB
•••
UBB
UVV
HSYNC
VSYNC
FLD
257
UVV
258
-VV
259
-VE
FIELDS 3 AND 7
260
261
0
1
2
3
4
5
6
7
8
•••
16
EE
EE
ES
SS
SS
SE
EE
EE
EB
UBB
UBB
•••
UBB
17
18
UVV
UVV
HSYNC
VSYNC
FLD
65-22x5y-71
Figure 31. PAL-M Vertical Interval
64
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
VINDO Operation
Video Measurement
The VINDO circuit uses the line idents on LID4-0, and the
blanking signals to control the comb filter output and the
blanking of the YUV data in the output matrix during the
vertical blanking period.
The TMC22x5yA supports a comprehensive set of video
measurement techniques to aid the user in setting up the
gain, phase, etc. of the decoder and in tracking down system
errors.
The vertical window VINDO starts on the first line after the
last equalizing pulse, at LID4-0 = 02. The VINDO stays
HIGH from this line until the VINDO count = VINDO4-0, or
the VBLK signal goes HIGH, at which time the VINDO goes
LOW. While the VINDO is HIGH the decoder operation is
controlled by VDIV, and during the time the VINDO and
VBLK are LOW the decoder operation is controlled by
VDOV.
Pixel Grab
The pixel grab allows the user to grab one pixel every line,
or one pixel out of the four field sequence in NTSC or the 8
field sequence in PAL, under software control. The SET pin
can also be used to produce the pixel grab pulse if SET2-0 =
110 and PGEXT is set HIGH.
The 10 bit G/Y, B/U, R/V outputs are stored in one set of
four 8 bit registers in the FORMAT block, while the 10 bit
luma and mixed sync data and the 10 bit demodulated U and
V color difference signals are stored in a set of five 8 bit
registers in the GRAB circuit block. The pixel grab signal,
PIXEL, whether internally or externally generated, is internally delayed to ensure that the all the grabbed data are from
the same pixel relative to the line sync pulse. The PIXEL
signal is equal to PGRAB or the logical AND of PGRAB
with FGRAB and LGRAB, and is controlled by the LPGEN,
PGEN, and PGEXT register bits.
Table 22. PAL VINDO operation
LID4-0
VINDO
VDIV
VDOV
Y
C
00 - 01
x
x
x
normal
normal
02 - 0A
1
0
x
simple
simple
02 - 0A
1
1
x
flat
black
02 - 0A
0
x
0
black
black
02 - 0A
0
x
1
simple
black
0B - 17
x
x
x
normal
normal
The luma and mixed sync signals are multiplexed on the
YMS data bus and the U and V signals are multiplexed on
the UV data bus, at the PXCK clock rate. The pixel grab
signal accommodates for this when grabbing these
components.
NTSC VINDO operation
LID4-0
VINDO
VDIV
VDOV
Y
C
00 - 02
x
x
x
normal
normal
03 - 06
1
0
x
simple
simple
03 - 06
1
1
x
flat
black
03 - 06
0
x
0
black
black
03 - 06
0
x
1
simple
black
07 - 17
x
x
x
normal
normal
An example of the pixel grab feature, is grabbing a pixel in
the center of the burst period allowing the user to check the
burst height by reading the magnitude of the demodulated U
and V components. This allows the user to compensate for
any chrominance gain errors in the output matrix.
Y
Y Data
Video A
Video B
Luma and
Chroma
Separation
dT
C Data
Luma
Proc
LPF
YMS
MS
G/Y
U
Chroma
Demodulation
UV
LPF
Output
Matrix
Output
Formatter
and Buffer
B/U
V
R/V
U Data
Grab
register 3A/3C
Pixel
V Data
Grab
register 3B/3C
G/Y
Grab
register 34/37
Y Data
Grab
register 38/3C
B/U
Grab
register 35/37
MS Data
Grab
register 39/3C
RV
Grab
register 36/37
dT
65-22x5y-72
Figure 32. Pixel Grab Locations
REV. 1.0.0 2/4/03
65
TMC22x5yA
PRODUCT SPECIFICATION
Table 23. Pixel Grab Control
LGEXT PGEN PGEXT LGEN
GRABS signal
0
0
x
x
GRABS = 0
0
1
0
0
GRABS =
PGRAB
0
1
0
1
GRABS = FGRAB
& LGRAB &
PGRAB
0
1
1
x
GRABS = NOT
(SET pin)
1
x
0
x
GRABS =
PGRAB
1
x
1
x
GRABS = NOT
(SET pin)
If a single pixel every 4 fields in NTSC and 8 fields in PAL is
required to be grabbed, PGG and PGEN in register 30h
should be set HIGH. The pixel grab signal is the logical
AND of the GRABP, GRABL, and GRABF signals. GRABP
goes HIGH whenever the pixel count equals the programmed
pixel grab number, GRABL goes HIGH for one line whenever the line count equals the programmed line number,
and the GRABF goes HIGH for a field whenever the field
number equals the programmed field count.
If the same pixel on every line is required to be grabbed, then
PGG should be set LOW, which internally forces GRABL
and GRABF to be forced HIGH enabling the pixel grab
whenever GRABP goes HIGH.
The SET pin can be used to provide an external grab signal
when PGEXT is set HIGH in register 30h and the SET
function in register 00h, SET[2:0] is programmed to 110
(binary). In this mode the falling edge on the SET pin
triggers the pixel grab.
The GRABP, GRABL, and GRABF signals are available on
bits 0,1, and 2 respectively of the read only register 41. An
example of the pixel grab feature, would be grabbing a pixel
in the center of the burst period allowing the user to check
the burst height by reading the magnitude of the demodulated U and V components. This would then allow the user to
compensate for any chrominance gain errors in the output
matrix.
The pixel grab value is delayed by 29 pixels from the pixel
count. This is the delay for all the pixel grab registers. Figure
33 shows this delay relative to GHSYNC. This means that if
29 is placed in the PG value, the actual pixel grabbed is
pixel 0.
The top two bits of the PG value provide the quadrant and
the bottom 9 bits provide the offset within that quadrant.
The integer part of STS/4 gives the maximum count for each
quadrant while the fractional result (bottom two bits)
provides the 0,1,2, or 3 count offset for the last quadrant.
For pixels value <= 4*Int(STS/4)
PG[10:9] = quadrant number
PG[8:0] = max quadrant count - Int(STS/4) + pixel offset
For pixels value > 4*Int(STS/4)
The quadrant is always number 3, ie PG[10:9] = 11 while the
pixel in excess of 4*Int(STS/4) is added to 1536.
Pixel STS-1
STS-1
Pixel Count
0
Pixel 0
GHSYNC
1
0
STS-1
Pixel Grab
0
Pixel Grab
value 0
29 pixels
Pixel Grab
value 28
Figure 33. Relationship Between Pixel Count and Pixel Grab Value
66
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
Examples:
NTSC std with STS programmed to 858.
Base pixels per quadrant = Int(858/4) = 214
Pixel 0:
1. Pixel 0 <= 4*Int(858/4)
2. Required pixel 0 < 214 therefore quadrant = 0,
[PG[10:9] = 00]
3. PG[10:0] = 511 - 214 + (0+[0*214]) = 297
Pixel 56:
1. Pixel 56 <= 4*Int(858/4)
2. Required pixel 56 < 214 therefore quadrant = 0
[PG[10:9] = 00]
3. PG[10:0] = 511 - 214 + (56-[0*214]) = 353
Pixel 250:
1. Pixel 250 <= 4*Int(858/4)
2. Required pixel 250 > 214 therefore quadrant =/= 0
3. Required pixel 250 < 428 therefore quadrant = 1,
[PG[10:9] = 01]
4. PG[10:0] = 1023 - 214 + (250-[1*214]) = 845
Pixel 800:
1. Pixel 800 <= 4*Int(858/4)
2. Required pixel 800 > 214 therefore quadrant =/= 0
3. Required pixel 800 > 428 therefore quadrant =/= 1
4. Required pixel 800 > 642 therefore quadrant =/= 2
5. Required pixel 800 < 858 therefore quadrant = 3,
[PG[10:9] = 11]
6. PG[10:0]= 2047 - 214 + (800-[3*214]) = 1991
Pixel 856:
1. Pixel <= 4*Int(858/4)
2. Required pixel 856 > 214 therefore quadrant =/= 0
3. Required pixel 856 > 428 therefore quadrant =/= 1
4. Required pixel 856 > 642 therefore quadrant =/= 2
5. Required pixel 856 < 858 therefore quadrant = 3,
[PG[10:9] = 11]
6. PG[10:>0] = 2047 - 214 + (856-[3*214]) = 2047
Pixel 857:
1. Pixel 857 > 4*Int(858/4)
2. Therefore quadrant = 3, [PG[10:9] = 11]
3. PG[10:0] = 1536 + (857-[4*214]) = 1537
Composite Line Grab
The composite line grab is only available in the 3 line comb
based decoders (TMC22053A and TMC22153A), and
allows the user to grab any line from the 4 field sequence in
NTSC or 8 field sequence in PAL when LGEN is set HIGH.
When the LGEN register bit is set HIGH the decoder automatically switches to operate as a “simple” bandsplit
decoder. The SET pin can also be used to produce the line
grab pulse if SET2-0 = 110 and LGEXT is set HIGH.
Once the line grab has been activated the subcarrier oscillator is frozen with the SEED and phase from the beginning of
the line, and the composite video in the 1H line store is
frozen by disabling the write signals in LSTORE1. The read
REV. 1.0.0 2/4/03
TMC22x5yA
cycle for the frozen line store is still clocked by PCK. The
subcarrier DDS and the internal read only registers will be
updated once per clock period as normal, but will reload the
DRS SEED and PHASE values at the beginning of each line.
The G/Y, B/U, and R/V outputs will remain active, and the
DHSYNC and DVSYNC signals will remained locked to the
input or flywheel if the input has been removed.
The pixel grab function can be used in conjunction with the
frozen line to examine individual pixels inside the decoder.
Parallel Microprocessor Interface
The parallel microprocessor interface, active when SER is
HIGH, employs a 12-line interface, with an 8-bit data bus
and one address bit: two addresses are required for device
programming and pointer-register management. Address bit
0 selects between reading/writing the register addresses and
reading/writing register data. When writing, the address is
presented along with a LOW on the R/W pin during the falling edge of CS Eight bits of data are presented on D7-0 during the subsequent rising edge of CS. One additional falling
edge of CS is needed to move input data to its assigned
working registers.
In read mode, the address is accompanied by a HIGH on the
R/W pin during a falling edge of CS. The data output pins go
to a low-impedance state tDOZ after CS falls. Valid data are
present on D7-0 tDOM after the falling edge of CS. Because
this port operates asynchronously with the pixel timing,
there is an uncertainty in this data valid output delay of one
PXCK period. This uncertainty does not apply to tDOZ.
Writing data to specific control registers of the TMC22x5yA
requires that the 8-bit address of the control register of interest be written. This control register address is the base
address for subsequent write operations. The base address
autoincrements by one for each byte of data written after the
data byte intended for the base address. If more bytes are
transferred than there are available addresses, the address
will not increment and remain at its maximum value of 3Fh.
Table 24. Parallel Port Control
A1-0 R/W
Action
00
0
Load D7-0 into Control Register pointer
(block 00)
00
1
Read Control Register pointer on
D7-0
01
0
Load D7-0 into addressed XLUT
Location pointer (block 01)
01
1
Read addressed XLUT Location pointer
on D7-0.
10
0
Write D7-0 to addressed Control
Register
10
1
Read addressed Control Register on
D7-0
11
0
Write D7-0 to addressed XLUT Location
11
1
Read addressed XLUT Location on D7-0
67
TMC22x5yA
PRODUCT SPECIFICATION
tPWLCS
tPWHCS
CS
tSA
tHA
R/W
ADR
tSD
tHD
D7-0
65-22x5y-16
Figure 33. Microprocessor Parallel Port – Write Timing
tPWLCS
tPWHCS
CS
tSA
tHA
R/W
ADR
tDOM
tHOM
D7-0
65-22x5y-17
tDOZ
Figure 34. Microprocessor Parallel Port – Read Timing
Serial Control Port (R-Bus)
There are six components to serial bus operation:
In addition to the 12-wire parallel port, a 2-wire serial
control interface is provided, and active when SER is LOW.
Either port alone can control the entire chip. Up to eight
TMC22x5yA devices may be connected to the 2-wire serial
interface with each device having a unique address.
•
•
•
•
•
•
The 2-wire interface comprises a clock (SCL) and a bi-directional data (SDA) pin. The Decoder acts as a slave for receiving and transmitting data over the serial interface. When the
serial interface is not active, the logic levels on SCL and
SDA are pulled HIGH by external pull-up resistors.
Data received or transmitted on the SDA line must be stable
for the duration of the positive-going SCL pulse. Data on
SDA must change only when SCL is LOW. If SDA changes
state while SCL is HIGH, the serial interface interprets that
action as a start or stop sequence.
68
Start signal
Slave address byte
Block Pointer
Base register address byte
Data byte to read or write
Stop signal
When the serial interface is inactive (SCL and SDA are
HIGH) communications are initiated by sending a start signal. The start signal is a HIGH-to-LOW transition on SDA
while SCL is HIGH. This signal alerts all slaved devices that
a data transfer sequence is coming.
The first eight bits of data transferred after a start signal comprise a seven bit slave address (the first seven bits) and a single R/W bit (the eighth bit). The R/W bit indicates the
direction of data transfer, read from or write to the slave
device. If the transmitted slave address matches the address
of the device (set by the state of the SA2-0 input pins in Table
20), the TMC22x5yA acknowledges by bringing SDA LOW
on the 9th SCL pulse. If the addresses do not match, the
TMC22x5yA does not acknowledge.
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Table 25. Serial Port Addresses
bit 7
bit 6
bit 5
bit 4
A6
(MSB)
A5
A4
A3
bit 3
bit 2
bit 1
A2
A1
A0
(SA2) (SA1) (SA0)
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
1
0
1
0
1
0
1
1
0
1
1
1
0
1
1
1
0
0
1
0
1
1
1
0
1
1
0
1
1
1
1
0
1
0
1
1
1
1
1
Data Transfer via Serial Interface
For each byte of data read or written, the MSB is the first bit;
that is, bit 7 of the 8-bit sequence.
If the TMC22x5yA does not acknowledge the master device
during a write sequence, the SDA remains HIGH so the master can generate a stop signal. If the master device does not
acknowledge the TMC22x5yA during a read sequence, the
Decoder interprets this as “end of data.” The SDA remains
HIGH so the master can generate a stop signal.
Writing data to specific control registers of the TMC22x5yA
requires that the 8-bit address of the control register of interest be written after the slave address has been established.
This control register address is the base address for subsequent write operations. The base address autoincrements by
one for each byte of data written after the data byte intended
for the base address. If more bytes are transferred than there
are available addresses, the address will not increment and
remain at its maximum value of 3Fh. Any base address
higher than 3Fh will not produce an ACKnowledge signal.
Data are read from the control registers of the TMC22x5yA
in a similar manner. Reading requires two data transfer
operations:
The base address must be written with the R/W\ bit of the
slave address byte LOW to set up a sequential read
operation.
Reading (the R/W bit of the slave address byte HIGH)
begins at the previously established base address. The
address of the read register autoincrements after each byte is
transferred.
To terminate a write sequence to the TMC22x5yA, a stop
signal must be sent. A stop signal comprises a LOW-toHIGH transition of SDA while SCL is HIGH. To terminate a
read sequence simply do not acknowledge (NOACK) the last
byte received and the TMC22x5yA will terminate the
sequence.
A repeated start signal occurs when the master device driving the serial interface generates a start signal without first
generating a stop signal to terminate the current communication. This is used to change the mode of communication
(read, write) between the slave and master without releasing
the serial interface lines.
Serial Interface Read/Write Examples
Write to one control register
•
•
•
•
•
•
Start signal
Slave Address byte (R/W bit = LOW)
Block Pointer (00)
Base Address byte
Data byte to base address
Stop signal
Write to four consecutive XLUT locations
•
•
•
•
•
•
•
•
•
Start signal
Slave Address byte (R/W bit = LOW)
Block Pointer (01)
Base Address byte
Data byte to base address
Data byte to (base address + 1)
Data byte to (base address + 2)
Data byte to (base address + 3)
Stop signal
Read from one XLUT location
• Start signal
• Slave Address byte (R/W bit = LOW)
SDA
tBUFF
tSTAH
tDHO
tDSU
tSTASU
tSTOSU
tDAL
SCL
tBAH
65-22x5y-18
Figure 35. Serial Port Read/Write Timing
REV. 1.0.0 2/4/03
69
TMC22x5yA
•
•
•
•
•
•
•
PRODUCT SPECIFICATION
•
•
•
•
•
•
•
•
•
Block Pointer (01)
Base Address byte
Stop signal
Start signal
Slave Address byte (R/W bit = HIGH)
Data byte from base address
Stop signal
Read from four consecutive control registers
Base Address byte
Stop signal
Start signal
Slave Address byte (R/W bit = HIGH)
Data byte from base address
Data byte from (base address + 1)
Data byte from (base address + 2)
Data byte from (base address + 3)
Stop signal
• Start signal
• Slave Address byte (R/W bit = LOW)
• Block Pointer (00)
(MSB)
SDA
Bit 7
(LSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ACK
SCL
65-22x5y-19
Figure 36. Serial Interface – Typical Byte Transfer
SDA
A6
A5
A4
A3
A2
SA2
SA1
SA0
ACK
SCL
65-22x5y-19A
Figure 37. Serial Interface – Chip Address
*Note:
To read from the XLUT, the initial read must be a dummy read. This means, for example, to read back XLUT location 0x02, read
back location 0x01, then read back 0x02 and ignore the information read back from the 0x01 location. This only needs to be done
once in a sequence. To read back the entire XLUT, set the pointer to 0xFF and ignore the data read from this register. The pointer
will then auto-increment to 0x00 allowing the next 256 locations read to be valid.
70
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Equivalent Circuits and Threshold Levels
VDD
VDD
p
p
Digital
Input
Digital
Output
n
n
27011B
27014B
GND
GND
Figure 38. Equivalent Digital Input Circuit
Figure 39. Equivalent Digital Output
tDIS
SET or RESET
tENA
0.5V
2.0V
0.8V
Three-State
Outputs
0.5V
65-22x5y-76
Figure 40. Threshold Levels for Three-state
REV. 1.0.0 2/4/03
71
TMC22x5yA
PRODUCT SPECIFICATION
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter
Min.
Max.
Unit
Power Supply voltage
-0.5
+7.0
V
-0.5
VDD+0.5
V
-20.0
+20.0
mA
Applied voltage 2
-0.5
VDD+0.5
V
Forced current 3, 4
-3.0
+6.0
mA
Digital Inputs
Applied Voltage
Forced current
3, 4
Digital Outputs
Short circuit duration (single output in HIGH state to ground)
1 second
Analog Output Short circuit duration (all outputs to ground)
infinite
Temperature
110
°C
junction
140
°C
Lead, soldering (10 seconds)
300
°C
Vapor Phase soldering (1 minute)
220
°C
Storage
150
°C
Operating, ambient
-20
Notes:
1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating
conditions. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed
only if Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
tPWHCK
tPWLCK
PXCK
tSP2
tHP2
HSYNC
CVBS
PIXEL 0
PIXEL 1
tSPI
PIXEL 2
tHPI
Internal
PCK
tCLH
LDV
65-22x5y-77
Figure 41. Input Timing Parameters
72
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Operating Conditions
Parameter
VDD
Power Supply Voltage
VIH
Input Voltage, Logic HIGH
TTL Compatible Inputs
Nom.
Max.
Units
4.75
5.0
5.25
V
VDD
V
2.0
Serial Port (SDA and SCL)
VIL
Min.
V
0.7*VDD
Input Voltage, Logic LOW
TTL Compatible Inputs
GND
0.8
V
Serial Port (SDA and SCL)
GND
0.3*VDD
V
IOH
Output Current, Logic HIGH
-2.0
mA
IOL
Output Current, Logic LOW
4.0
mA
TA
Ambient Temperature, Still Air
0
70
°C
10
18
MHz
20
36
MHz
Pixel Interface (input)
fCLK
Pixel Rate (CKSEL = 0)
Master Clock Rate = 2X pixel rate (CKSEL =
1)1
tPWHCK
CLOCK pulse width, HIGH
8
ns
tPWLCK
CLOCK pulse width, LOW
13
ns
tSP
Pixel Data Input Setup Time
8
ns
tHP
Pixel Data Input Hold Time
2
ns
tSP
HSYNC, VSYNC, and BUFFER setup time
5
ns
tHP
HSYNC, VSYNC, and BUFFER hold time
6
ns
Notes:
1. Tested at fCLK = 30MHz
To aid in the understanding of the timing relationship between the PXCK and LDV clock, when the LDV signal is used as the
TMC22x5yA output clock, the following block diagram of the TMC22x5yA output stage is provided.
Data In
PXCK
D
Q
Ck
D
Q
G/Y, B/U, and R/V
Output Data
Ck
2:1
mux
LDV
65-22x5y-78
Figure 42. Functional Block Diagram of the TMC22x5yA G/Y, B/U, and R/V Output Stage
REV. 1.0.0 2/4/03
73
TMC22x5yA
PRODUCT SPECIFICATION
Operating Conditions (continued)
Parameter
Min.
Nom.
Max.
Units
4
15
18
ns
4
15
18
ns
4
15
18
ns
Pixel Interface (output)
tPOD CLOCK to DHSYNC and DVYSNC, AVOUT, and FID[2:0] Propagation
Time
tPOD CLOCK to data, Propagation Time
tPOD Int. or Ext. LDV to data, Propagation Time
tHOD Clock to DHSYNC and DVSYNC, AVOUT, and FID[2:0] Hold Time
2.5
ns
tHOD Clock to Data, Hold Time
2.5
ns
tHOD Int. or Ext. LDV to Data, Hold Time
2.5
ns
tENA
Enable to Low Z on Output Data
23
30
ns
tDIS
Disable to High Z on Output Data
23
30
ns
tCLH
tCLH
CLOCK to LDV (i/p) signal HIGH
0
ns
10
14
ns
9
CLOCK to LDV (o/p) signal HIGH
PXCK
tPOD
tPOD
DHSYNC
G/Y, B/U
RV Data
PIXEL 0
PIXEL 1
PIXEL 2
TMC22x5y
Internal PCK
tCLH
LDV
65-22x5y-79
Figure 43. Output Timing Parameters
74
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Operating Conditions (continued)
Parameter
Min.
Nom.
Max.
Units
Parallel Microprocessor Interface
tPWLCS
CS Pulse Width, LOW
2
Pixels
tPWHCS
CS Pulse Width, HIGH
3
Pixels
tSA
Address Setup Time
8
ns
tHA
Address Hold Time
2
ns
tSD
Data Setup Time (write)
8
ns
tHD
Data Hold Time (write)
2
ns
Serial Microprocessor Interface
tDAL
SCL Pulse Width , LOW
1.0
µs
tDAH
SCL Pulse Width, HIGH
0.48
µs
tSTAH
Hold Time for START or Repeated START
0.48
µs
tSTASU
Setup Time for START or Repeated START
0.48
µs
tSTOSU
Setup time for STOP
0.48
µs
tBUFF
Bus Free Time Betweeen a STOP and a START condition
1.0
µs
tDSU
Data Setup Time
80
ns
Electrical Characteristics
Parameter
IDD
Power Supply
Conditions
Current1
Min.
VDD = Max, fPXCK = 27MHz
Typ.
Max.
225
Units
275
mA
IDDQ Power Supply Current, Disabled
VDD = Max
50
mA
IIH
Input Current, HIGH
VDD = Max, VIN = VDD
±10
µA
IIL
Input Current, LOW
VDD = Max, VIN = 0V
±10
µA
IOZH
Hi-Z Output Leakage Current,
Output HIGH
VDD = Max, VIN = VDD
±10
µA
IOZL
Hi-Z Output Leakage Current,
Output LOW
VDD = Max, VIN = 0V
±10
µA
IOS
Short-Circuit Current
-80
mA
-20
etc2.,
VOH
Output Voltage, HIGH
G/Y9-0,
VOL
Output Voltage, LOW
G/Y9-0, etc2., IOL = MAX
IOH = MAX
2.4
0.4
V
V
SDA, IOL = 3mA
0.4
V
SDA, IOL = 6mA
0.6
V
10
pF
CI
Digital Input Capacitance
4
CO
Digital Output Capacitance
10
pF
Notes:
1. Typical IDD with VDD = NOM and TA = NOM, Maximum IDD with VDD = 5.25V and TA = 70°C
2. G/Y[9:0], B/Y[9:0], R/V[9:0] , DVSYNC, DHSYNC, LDV, AVOUT, FID[2:0]
REV. 1.0.0 2/4/03
75
TMC22x5yA
PRODUCT SPECIFICATION
Switching Characteristics
Parameter
Conditions
Min.
Typ.
Max.
Units
tDOZ
Output Delay, CS to low-Z
9
ns
tHOM
Output Hold Time, CS to high-Z
10
ns
tDOM
Output Delay, CS to Data Valid
30
40
ns
Note:
Timing reference points are at the 50% level, digital output load <40pF.
System Performance Characteristics
Parameter
RES
76
Video Processing Resolution
Conditions
Min.
Typ.
Max.
Units
TMC2205xA
8
bits
TMC2215xA
10
bits
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Programming Examples
Standard:
Mode:
Input Format:
Output Format:
Decoder:
NTSC-M
Line-Locked
13.5 Composite
RGB (0-1023) Sync on Green
Adaptive 3-Line Chroma Comb Filter
Register Map:
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
D8
01
00
A1
20
28
00
10
40
00
12
00
00
04
24
09
1
5A
56
2E
D2
23
00
00
2C
1B
90
13
49
F0
01
00
00
2
40
F8
E0
43
00
00
07
00
00
00
00
00
00
00
00
00
3
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
Standard:
Mode:
Input Format:
Output Format:
Decoder:
NTSC
Line-Locked
NTSC Composite
D1 Component
3 Line Adaptive Chroma Comb
Register Map:
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
C0
01
00
A1
20
28
00
10
40
00
34
74
80
04
64
08
1
5A
56
2E
D2
23
72
00
00
95
0E
51
49
40
00
00
00
2
40
F8
E0
43
24
25
07
00
00
00
00
00
00
00
00
00
3
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
REV. 1.0.0 2/4/03
77
TMC22x5yA
PRODUCT SPECIFICATION
Programming Examples (continued)
Standard:
Mode:
Input Format:
Output Format:
Decoder:
NTSC
Line-Locked
13.5 MHz Composite Video
YUV
Adaptive 3-Line Comb
Register Map:
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
D8
01
00
A1
20
28
00
10
40
00
34
00
80
04
64
08
1
5A
56
2E
D2
23
3C
00
2C
1B
90
13
49
F0
01
00
00
2
40
F8
E0
43
24
25
07
00
00
00
00
00
00
00
00
00
3
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
Standard:
Mode:
Input Format:
Output Format:
Decoder:
PAL
Line-Locked
Composite
YUV
Adaptive 3-Line Comb
Register Map:
78
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
DB
01
00
24
08
00
24
15
40
08
36
00
C0
04
54
09
1
60
53
32
CE
23
01
00
00
00
3E
03
49
00
05
00
00
2
90
15
13
54
24
25
07
00
00
00
00
00
00
00
00
00
3
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Programming Examples (continued)
Standard:
Mode:
Input Format:
Output Format:
PAL
Line-Locked
PAL-YC
Y, Cb, Cr (D1 Out)
Decoder:
Register Map:
No Comb
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
D3
07
00
00
20
00
00
0C
40
08
24
60
03
00
0B
0A
1
60
53
44
D2
23
00
00
00
88
BF
3C
49
40
00
00
00
2
90
15
13
54
00
00
00
00
00
00
00
00
00
00
00
00
3
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
Standard:
NTSC-M
Mode:
D1 Mode
Input Format:
Output Format:
Decoder:
D1, CBYCR [Y] multiplexed data w/embedded TRS words
D1 Output
2 Line Chroma comb of CBCR data
Register Map:
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
C0
1F
37
E3
20
00
00
0C
40
40
34
60
09
04
F8
02
1
5A
47
35
D2
23
00
0A
00
00
00
00
49
40
00
00
00
2
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
3
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
REV. 1.0.0 2/4/03
79
TMC22x5yA
PRODUCT SPECIFICATION
Programming Examples (continued)
Standard:
NTSC-M
Mode:
D1 Mode
Input Format:
Output Format:
Decoder:
D1, CBYCR [Y] Multiplexed Data w/TRS
YCBCR, Output DHSync + DVSync
Simple Transcoder
Register Map:
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
C0
1F
37
E3
20
00
00
0C
40
40
34
00
09
04
0A
02
1
5A
47
35
D2
23
00
0A
00
00
00
00
49
40
00
00
00
2
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
3
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
Standard:
NTSC-M
Mode:
D1 Mode
Input Format:
Output Format:
Decoder:
YCBCR
D1, CBYCR [Y] Multiplexed Data with TRS
Simple Transcoder
Register Map:
80
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
C0
0F
07
A3
20
00
00
0C
40
00
34
60
09
04
0A
02
1
5A
47
35
D2
23
00
00
00
00
00
00
49
40
00
00
00
2
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
3
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Programming Worksheet
Standard:
Mode:
Input Format:
Output Format:
Decoder:
Register Map:
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
xx
xx
xx
xx
xx
xx
xx
xx
xx
0
1
2
The DRS appears on the
output at the
rate.
Demodulation Filter
0
-10
-10
65-22x5y-41
-60
-10
Normalized Frequency
0.40
0.30
0.20
0.10
0.00
-70
-40
-50
65-22x5y-43
Adaptive Notch
Filter 2
-60
-30
-60
-70
0.30
-50
65-22x5y-42
-40
-20
0.10
Adaptive Notch
Filter 1
Adaptive Notch
Filter 3
0.00
-20
Attenuation (dB)
0
-10
0.50
Attenuation (dB)
Non-Adaptive Notch Filter
0
REV. 1.0.0 2/4/03
0.50
Normalized Frequency
Adaptive Notch Filter
-30
0.50
Normalized Frequency
0.40
-70
0.00
0.40
0.30
0.10
0.00
-70
0.20
-60
Demodulator Filter 2
-50
0.40
65-22x5y-40
-50
-40
0.30
Bandsplit Filter 1
Demodulator Filter 1
-30
0.20
-40
-20
0.20
Bandsplit Filter 2
-30
0.10
-20
Attenuation (dB)
0
0.50
Attenuation (dB)
Bandsplit Filter
Normalized Frequency
81
TMC22x5yA
PRODUCT SPECIFICATION
Notes
82
REV. 1.0.0 2/4/03
PRODUCT SPECIFICATION
TMC22x5yA
Mechanical Dimensions – 100 Lead MQFP Package
Inches
Symbol
Notes:
Millimeters
Notes
Min.
Max.
Min.
Max.
A
A1
A2
B
C
D
D1
E
—
.010
.100
.009
.005
.904
.783
.667
.134
—
.120
.015
.009
.923
.791
.687
—
.25
2.55
.23
.13
22.95
19.90
16.95
3.40
—
3.05
.38
.23
23.45
20.10
17.45
E1
e
L
N
ND
NE
.547
.555
.0256 BSC
.025
.037
100
30
20
α
ccc
0°
—
7°
.004
2. Controlling dimension is millimeters.
3. Dimension "B" does not include dambar protrusion. Allowable
dambar protrusion shall be .08mm (.003in.) maximum in excess of
the "B" dimension. Dambar cannot be located on the lower radius
or the foot.
3, 5
5
4. "L" is the length of terminal for soldering to a substrate.
5. "B" & "C" includes lead finish thickness.
13.90
14.10
.65 BSC
.65
.95
100
30
20
0°
—
1. All dimensions and tolerances conform to ANSI Y14.5M-1982.
4
7°
.10
D
.20 (.008) Min.
0° Min.
.13 (.30)
R
.005 (.012)
D1
Datum Plane
B
C
E1
α
.13 (.005) R Min.
E
L
e
0.063" Ref (1.60mm)
Lead Detail
See Lead Detail
Base Plane
A A2
B
A1
REV. 1.0.0 2/4/03
Seating Plane
-CLead Coplanarity
ccc C
83
TMC22x5yA
PRODUCT SPECIFICATION
Ordering Information
Product Number
Temperature
Range
Decoding
Resolution
Package
Package Marking
TMC22051AKHC
0°C to 70°C
Simple
8 bit
100-Lead MQFP
22051AKHC
TMC22052AKHC
0°C to 70°C
2-Line Comb
8 bit
100-Lead MQFP
22052AKHC
TMC22053AKHC
0°C to 70°C
3-Line Comb
8 bit
100-Lead MQFP
22053AKHC
TMC22151AKHC
0°C to 70°C
Simple
10 bit
100-Lead MQFP
22151AKHC
TMC22152AKHC
0°C to 70°C
2-Line Comb
10 bit
100-Lead MQFP
22152AKHC
TMC22153AKHC
0°C to 70°C
3-Line Comb
10 bit
100-Lead MQFP
22153AKHC
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
2/4/03 0.0m 001
Stock#DS7022x5yA
 2003 Fairchild Semiconductor Corporation