AD ADV7343BSTZ

Multiformat Video Encoder
Six, 11-Bit, 297 MHz DACs
ADV7342/ADV7343
FEATURES
EIA/CEA-861B compliance support
Programmable features
Luma and chroma filter responses
Vertical blanking interval (VBI)
Subcarrier frequency (FSC) and phase
Luma delay
Copy generation management system (CGMS)
Closed captioning and wide screen signaling (WSS)
Integrated subcarrier locking to external video source
Complete on-chip video timing generator
On-chip test pattern generation
On-board voltage reference (optional external input)
Serial MPU interface with dual I2C® and SPI® compatibility
3.3 V analog operation
1.8 V digital operation
3.3 V I/O operation
Temperature range: −40°C to +85°C
74.25 MHz 20-/30-bit high definition input support
Compliant with SMPTE 274M (1080i), 296M (720p),
and 240M (1035i)
6, 11-bit, 297 MHz video DACs
16× (216 MHz) DAC oversampling for SD
8× (216 MHz) DAC oversampling for ED
4× (297 MHz) DAC oversampling for HD
37 mA maximum DAC output current
NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support
NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz)
Multiformat video input support
4:2:2 YCrCb (SD, ED, and HD)
4:4:4 YCrCb (ED and HD)
4:4:4 RGB (SD, ED, and HD)
Multiformat video output support
Composite (CVBS) and S-Video (Y/C)
Component YPrPb (SD, ED, and HD)
Component RGB (SD, ED, and HD)
Macrovision® Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant
Simultaneous SD and ED/HD operation
APPLICATIONS
DVD recorders and players
High definition Blu-ray DVD players
HD-DVD players
FUNCTIONAL BLOCK DIAGRAM
GND_IO
VDD (2)
VBI DATA SERVICE
INSERTION
SCL/ SDA/ ALSB/
MOSI SCLK SPI_SS
SFL/
MISO
MPU PORT
SUBCARRIER FREQUENCY
LOCK (SFL)
AGND
ADV7342/ADV7343
10-BIT
SD
VIDEO
DATA
4:2:2 TO 4:4:4
HD DDR
DEINTERLEAVE
R
G/B
20-BIT
ED/HD
VIDEO
DATA
RGB/YCrCb
TO
YUV
MATRIX
RGB
ASYNC
BYPASS
DEINTERLEAVE
POWER
MANAGEMENT
CONTROL
PROGRAMMABLE
LUMINANCE
FILTER
ADD
BURST
PROGRAMMABLE
CHROMINANCE
FILTER
SIN/COS DDS
BLOCK
16×
FILTER
16×
FILTER
RGB
YCbCr
ED/HD INPUT
ADD
SYNC
PROGRAMMABLE
HDTV FILTERS
HDTV
TEST
PATTERN
GENERATOR
YCbCr
TO
RGB MATRIX
SHARPNESS AND
ADAPTIVE FILTER
CONTROL
4×
FILTER
16x/4x OVERSAMPLING
DAC PLL
VIDEO TIMING GENERATOR
P_HSYNC P_VSYNC P_BLANK S_HSYNC S_VSYNC
CLKIN (2) PVDD
MULTIPLEXER
VDD_IO
YUV
TO
YCrCb/
RGB
VAA
11-BIT
DAC 1
DAC 1
11-BIT
DAC 2
DAC 2
11-BIT
DAC 3
DAC 3
11-BIT
DAC 4
DAC 4
11-BIT
DAC 5
DAC 5
11-BIT
DAC 6
DAC 6
REFERENCE
AND CABLE
DETECT
PGND EXT_LF (2) VREF
COMP (2)
RSET (2)
06399-001
DGND (2)
Figure 1.
Protected by U.S. Patent Numbers 5,343,196 and 5,442,355 and other intellectual property rights.
Protected by U.S. Patent Numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
ADV7342/ADV7343
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
SD Subcarrier Frequency Lock, Subcarrier Phase Reset, and
Timing Reset ............................................................................... 49
Functional Block Diagram .............................................................. 1
SD VCR FF/RW Sync ................................................................ 50
Revision History ............................................................................... 3
Vertical Blanking Interval ......................................................... 50
Detailed Features .............................................................................. 4
SD Subcarrier Frequency Registers.......................................... 50
General Description ......................................................................... 4
SD Noninterlaced Mode............................................................ 51
Specifications..................................................................................... 5
SD Square Pixel Mode ............................................................... 51
Power Supply and Voltage Specifications.................................. 5
Filters............................................................................................ 52
Voltage Reference Specifications ................................................ 5
ED/HD Test Pattern Color Controls ....................................... 53
Input Clock Specifications .......................................................... 5
Color Space Conversion Matrix ............................................... 53
Analog Output Specifications..................................................... 6
SD Luma and Color Control..................................................... 54
Digital Input/Output Specifications........................................... 6
SD Hue Adjust Control.............................................................. 55
Digital Timing Specifications ..................................................... 7
SD Brightness Detect ................................................................. 55
MPU Port Timing Specifications ............................................... 8
SD Brightness Control............................................................... 55
Power Specifications .................................................................... 8
SD Input Standard Auto Detection.......................................... 55
Video Performance Specifications ............................................. 9
Double Buffering ........................................................................ 56
Timing Diagrams............................................................................ 10
Programmable DAC Gain Control .......................................... 56
Absolute Maximum Ratings.......................................................... 17
Gamma Correction .................................................................... 56
Thermal Resistance .................................................................... 17
ED/HD Sharpness Filter and Adaptive Filter Controls......... 58
ESD Caution................................................................................ 17
ED/HD Sharpness Filter and Adaptive Filter Application
Examples...................................................................................... 59
Pin Configuration and Function Descriptions........................... 18
Typical Performance Characteristics ........................................... 20
MPU Port Description................................................................... 25
SD Digital Noise Reduction...................................................... 60
SD Active Video Edge Control ................................................. 61
I2C Operation.............................................................................. 25
External Horizontal and Vertical
Synchronization Control ........................................................... 63
SPI Operation.............................................................................. 26
Low Power Mode........................................................................ 64
Register Map Access....................................................................... 27
Cable Detection .......................................................................... 64
Register Programming............................................................... 27
DAC Auto Power-Down............................................................ 64
Subaddress Register (SR7 to SR0) ............................................ 27
Pixel and Control Port Readback............................................. 64
Input Configuration ....................................................................... 44
Reset Mechanism........................................................................ 64
Standard Definition Only.......................................................... 44
Printed Circuit Board Layout and Design .................................. 65
Enhanced Definition/High Definition Only .......................... 45
DAC Configurations.................................................................. 65
Simultaneous Standard Definition and Enhanced
Definition/High Definition....................................................... 45
Voltage Reference ....................................................................... 65
Enhanced Definition Only (at 54 MHz) ................................. 46
Output Configuration .................................................................... 47
Features ............................................................................................ 48
Output Oversampling ................................................................ 48
ED/HD Nonstandard Timing Mode........................................ 48
ED/HD Timing Reset ................................................................ 49
Video Output Buffer and Optional Output Filter.................. 65
Printed Circuit Board (PCB) Layout ....................................... 66
Typical Application Circuit....................................................... 68
Appendix 1—Copy Generation Management System .............. 69
SD CGMS .................................................................................... 69
ED CGMS.................................................................................... 69
HD CGMS................................................................................... 69
CGMS CRC Functionality ........................................................ 69
Rev. 0 | Page 2 of 88
ADV7342/ADV7343
Appendix 2—SD Wide Screen Signaling .....................................72
SD YPrPb Output Levels—SMPTE/EBU N10........................81
Appendix 3—SD Closed Captioning............................................73
ED/HD YPrPb Output Levels ...................................................82
Appendix 4—Internal Test Pattern Generation ..........................74
SD/ED/HD RGB Output Levels................................................83
SD Test Patterns...........................................................................74
SD Output Plots ..........................................................................84
ED/HD Test Patterns ..................................................................74
Appendix 8—Video Standards ......................................................85
Appendix 5—SD Timing................................................................75
Outline Dimensions........................................................................87
Appendix 6—HD Timing ..............................................................80
Ordering Guide ...........................................................................87
Appendix 7—Video Output Levels...............................................81
REVISION HISTORY
10/06—Revision 0: Initial Version
Rev. 0 | Page 3 of 88
ADV7342/ADV7343
DETAILED FEATURES
High definition (HD) programmable features
(720p/1080i/1035i)
4× oversampling (297 MHz)
Internal test pattern generator
Fully programmable YCrCb to RGB matrix
Gamma correction
Programmable adaptive filter control
Programmable sharpness filter control
CGMS (720p/1080i) and CGMS Type B (720p/1080i)
Undershoot limiter
Dual data rate (DDR) input support
EIA/CEA-861B compliance support
Enhanced definition(ED) programmable features
(525p/625p)
8× oversampling (216 MHz output)
Internal test pattern generator
Color and black bar, hatch, flat field/frame
Individual Y and PrPb output delay
Gamma correction
Programmable adaptive filter control
Fully programmable YCrCb to RGB matrix
Undershoot limiter
Macrovision Rev 1.2 (525p/625p)
CGMS (525p/625p) and CGMS Type B (525p)
Dual data rate (DDR) input support
EIA/CEA-861B compliance support
Standard definition (SD) programmable features
16× oversampling (216 MHz)
Internal test pattern generator
Color and black bar
Controlled edge rates for start and end of active video
Individual Y and PrPb output delay
Undershoot limiter
Gamma correction
Digital noise reduction (DNR)
Multiple chroma and luma filters
Luma-SSAF™ filter with programmable gain/attenuation
PrPb SSAF™
Separate pedestal control on component and
composite/S-Video output
VCR FF/RW sync mode
Macrovision Rev 7.1.L1
Copy generation management system (CGMS)
Wide screen signaling
Closed captioning
EIA/CEA-861B compliance support
GENERAL DESCRIPTION
The ADV7342/ADV7343 are high speed, digital-to-analog
video encoders in a 64-lead LQFP package. Six high speed, 3.3
V, 11-bit video DACs provide support for composite (CVBS), SVideo (Y/C), and component (YPrPb/RGB) analog outputs in
either standard definition (SD), enhanced definition (ED), or
high definition (HD) video formats.
The ADV7342/ADV7343 each have a 24-bit pixel input port
that can be configured in a variety of ways. SD video formats
are supported over a SDR interface and ED/HD video formats
are supported over SDR and DDR interfaces. Pixel data can be
supplied in either the YCrCb or RGB color spaces.
The parts also support embedded EAV/SAV timing codes,
external video synchronization signals, and I2C and SPI
communication protocols.
In addition, simultaneous SD and ED/HD input and output are
supported. 216 MHz (SD and ED) and 297 MHz (HD)
oversampling ensures that external output filtering is not
required, while full-drive DACs ensure that external output
buffering is not required.
Cable detection and DAC auto power-down features keep
power consumption to a minimum.
Table 1 lists the video standards directly supported by the
ADV7342/ADV7343.
Table 1. Standards Directly Supported by the
ADV7342/ADV7343 1
Resolution
720 × 240
720 × 288
720 × 480
I/P 2
P
P
I
Frame
Rate (Hz)
59.94
50
29.97
Clock Input
(MHz)
27
27
27
720 × 576
I
25
27
720 × 480
I
29.97
24.54
720 × 576
I
25
29.5
720 × 483
720 × 483
720 × 483
720 × 576
720 × 483
720 × 576
1920 × 1035
1920 × 1035
1280 × 720
P
P
P
P
P
P
I
I
P
27
27
27
27
27
27
74.25
74.1758
74.25
1280 × 720
P
74.1758
SMPTE 296M
1920 × 1080
1920 × 1080
1920 × 1080
1920 × 1080
1920 × 1080
I
I
P
P
P
59.94
59.94
59.94
50
59.94
50
30
29.97
60, 50, 30,
25, 24
23.97,
59.94, 29.97
30, 25
29.97
30, 25, 24
23.98, 29.97
24
ITU-R
BT.601/656
ITU-R
BT.601/656
NTSC Square
Pixel
PAL Square
Pixel
SMPTE 293M
BTA T-1004
ITU-R BT.1358
ITU-R BT.1358
ITU-R BT.1362
ITU-R BT.1362
SMPTE 240M
SMPTE 240M
SMPTE 296M
74.25
74.1758
74.25
74.1758
74.25
SMPTE 274M
SMPTE 274M
SMPTE 274M
SMPTE 274M
ITU-R BT.709-5
1
2
Standard
Other standards are supported in the ED/HD nonstandard timing mode.
I = interlaced, P = progressive.
Rev. 0 | Page 4 of 88
ADV7342/ADV7343
SPECIFICATIONS
POWER SUPPLY AND VOLTAGE SPECIFICATIONS
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 2.
Parameter
SUPPLY VOLTAGES
VDD
VDD_IO
PVDD
VAA
POWER SUPPLY REJECTION RATIO
Conditions
Min
Typ
Max
Unit
1.71
2.97
1.71
2.6
1.8
3.3
1.8
3.3
0.002
1.89
3.63
1.89
3.465
V
V
V
V
%/%
Min
1.186
1.15
Typ
1.248
1.235
±10
Max
1.31
1.31
Unit
V
V
μA
VOLTAGE REFERENCE SPECIFICATIONS
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 3.
Parameter
Internal Reference Range, VREF
External Reference Range, VREF
External VREF Current 1
1
Conditions
External current required to overdrive internal VREF.
INPUT CLOCK SPECIFICATIONS
VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 2.97 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 4.
Parameter
fCLKIN_A
fCLKIN_A
fCLKIN_A
fCLKIN_B
fCLKIN_B
CLKIN_A High Time, t9
CLKIN_A Low Time, t10
CLKIN_B High Time, t9
CLKIN_B Low Time, t10
CLKIN_A Peak-to-Peak Jitter Tolerance
CLKIN_B Peak-to-Peak Jitter Tolerance
1
Conditions 1
SD/ED
ED (at 54 MHz)
HD
ED
HD
Min
Typ
27
54
74.25
27
74.25
40
40
40
40
2
2
SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition.
Rev. 0 | Page 5 of 88
Max
Unit
MHz
MHz
MHz
MHz
MHz
% of one clock cycle
% of one clock cycle
% of one clock cycle
% of one clock cycle
±ns
±ns
ADV7342/ADV7343
ANALOG OUTPUT SPECIFICATIONS
VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 2.97 V to 3.63 V. VREF = 1.235 V (driven externally).
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 5.
Parameter
Full-Drive Output Current (Full-Scale) 1
Low Drive Output Current (Full-Scale) 2
DAC-to-DAC Matching
Output Compliance, VOC
Output Capacitance, COUT
Analog Output Delay 3
DAC Analog Output Skew
Conditions
RSET = 510 Ω, RL = 37.5 Ω
RSET = 4.12 kΩ, RL = 300 Ω
DAC 1 to DAC 6
Min
33
4.1
Typ
34.6
4.3
1.0
0
DAC 1, DAC 2, DAC 3
DAC 4, DAC 5, DAC 6
DAC 1, DAC 2, DAC 3
DAC 4, DAC 5, DAC 6
DAC 1, DAC 2, DAC 3
DAC 4, DAC 5, DAC 6
Max
37
4.5
1.4
10
6
8
6
2
1
1
Applicable to full-drive capable DACs only, that is, DAC 1, DAC 2, DAC 3.
Applicable to all DACs.
3
Output delay measured from the 50% point of the rising edge of the input clock to the 50% point of the DAC output full-scale transition.
2
DIGITAL INPUT/OUTPUT SPECIFICATIONS
VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 2.97 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 6.
Parameter
Input High Voltage, VIH
Input Low Voltage, VIL
Input Leakage Current, IIN
Input Capacitance, CIN
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current
Three-State Output Capacitance
Conditions
Min
2.0
Typ
Max
0.8
±10
VIN = VDD_IO
4
ISOURCE = 400 μA
ISINK = 3.2 mA
VIN = 0.4 V, 2.4 V
2.4
0.4
±1.0
4
Rev. 0 | Page 6 of 88
Unit
V
V
μA
pF
V
V
μA
pF
Unit
mA
mA
%
V
pF
pF
ns
ns
ns
ns
ADV7342/ADV7343
DIGITAL TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 2.97 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 7.
Parameter
VIDEO DATA AND VIDEO CONTROL PORT 2, 3
Data Setup Time, t11 4
Data Hold Time, t124
Control Setup Time, t114
Control Hold Time, t124
Digital Output Access Time, t134
Digital Output Hold Time, t144
PIPELINE DELAY 5
SD1
CVBS/YC Outputs (2×)
CVBS/YC Outputs (16×)
Component Outputs (2×)
Component Outputs (16×)
ED1
Component Outputs (1×)
Component Outputs (8×)
HD1
Component Outputs (1×)
Component Outputs (4×)
Conditions 1
Min
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz)
SD
ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz)
2.1
2.3
2.3
1.7
1.0
1.1
1.1
1.0
2.1
2.3
1.7
1.0
1.1
1.0
Typ
Max
12
10
4.0
3.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SD oversampling disabled
SD oversampling enabled
SD oversampling disabled
SD oversampling enabled
68
67
78
84
clock cycles
clock cycles
clock cycles
clock cycles
ED oversampling disabled
ED oversampling enabled
41
46
clock cycles
clock cycles
HD oversampling disabled
HD oversampling enabled
40
44
clock cycles
clock cycles
1
SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.
Video data: C[7:0], Y[7:0], and S[7:0].
3
Video control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, and S_VSYNC.
4
Guaranteed by characterization.
5
Guaranteed by design.
2
Rev. 0 | Page 7 of 88
ADV7342/ADV7343
MPU PORT TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 2.97 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 8.
Parameter
MPU PORT, I2C MODE 1
SCL Frequency
SCL High Pulse Width, t1
SCL Low Pulse Width, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDA, SCL Rise Time, t6
SDA, SCL Fall Time, t7
Setup Time (Stop Condition), t8
MPU PORT, SPI MODE1
SCLK Frequency
SPI_SS to SCLK Setup Time, t1
SCLK High Pulse Width, t2
SCLK Low Pulse Width, t3
Data Access Time after SCLK Falling Edge, t4
Data Setup Time prior to SCLK Rising Edge, t5
Data Hold Time after SCLK Rising Edge, t6
SPI_SS to SCLK Hold Time, t7
SPI_SS to MISO High Impedance, t8
1
Conditions
See Figure 19
Min
Typ
0
0.6
1.3
0.6
0.6
100
Max
Unit
400
kHz
μs
μs
μs
μs
ns
ns
ns
μs
300
300
0.6
See Figure 20
0
20
50
50
10
40
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Typ
Max
35
20
0
0
Guaranteed by characterization.
POWER SPECIFICATIONS
VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, VDD_IO = 3.3 V, TA = +25°C.
Table 9.
Parameter
NORMAL POWER MODE 1, 2
IDD 3
IDD_IO
IAA
IPLL
Conditions
Min
SD only (16× oversampling)
ED only (8× oversampling) 4
HD only (4× oversampling)4
SD (16× oversampling) and ED (8× oversampling)
SD (16× oversampling) and HD (4× oversampling)
3 DACs enabled (ED/HD only)
6 DACs enabled (SD only and simultaneous modes )
SD only, ED only or HD only modes
Simultaneous modes
SLEEP MODE
IDD
IAA
IDD_IO
IPLL
1
90
65
91
95
122
1
124
140
5
10
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
5
0.3
0.2
0.1
μA
μA
μA
μA
RSET1 = 510 Ω (DAC 1, DAC 2, and DAC 3 operating in full-drive mode). RSET2 = 4.12 kΩ (DAC 4, DAC 5, and DAC 6 operating in low drive mode).
75% color bar test pattern applied to pixel data pins.
3
IDD is the continuous current required to drive the digital core.
4
Applicable to both single data rate (SDR) and dual data rate (DDR) input modes.
2
Rev. 0 | Page 8 of 88
Unit
ADV7342/ADV7343
VIDEO PERFORMANCE SPECIFICATIONS
VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, VDD_IO = 3.3 V, TA = 25°C, VREF driven externally.
Table 10.
Parameter
STATIC PERFORMANCE
Resolution
Integral Nonlinearity
Differential Nonlinearity 1 +ve
Differential Nonlinearity1 −ve
STANDARD DEFINTION (SD) MODE
Luminance Nonlinearity
Differential Gain
Differential Phase
Signal-to-Noise Ratio (SNR)
Conditions
Typ
Max
Unit
RSET1 = 510 kΩ, RL1 = 37.5 Ω
RSET2 = 4.12 kΩ, RL2 = 300 Ω
RSET1 = 510 kΩ, RL1 = 37.5 Ω
RSET2 = 4.12 kΩ, RL2 = 300 Ω
RSET1 = 510 kΩ, RL1 = 37.5 Ω
RSET2 = 4.12 kΩ, RL2 = 300 Ω
11
0.4
0.5
0.15
0.5
0.25
0.2
Bits
LSBs
LSBs
LSBs
LSBs
LSBs
LSBs
NTSC
NTSC
Luma ramp
Flat field full bandwidth
0.5
0.5
0.6
58
75
±%
%
Degrees
dB
dB
12.5
5.8
MHz
MHz
30
13.75
MHz
MHz
ENHANCED DEFINITION (ED) MODE
Luma Bandwidth
Chroma Bandwidth
HIGH DEFINITION (HD) MODE
Luma Bandwidth
Chroma Bandwidth
1
Min
Differential nonlinearity (DNL) measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal
step value. For −ve DNL, the actual step value lies below the ideal step value.
Rev. 0 | Page 9 of 88
ADV7342/ADV7343
TIMING DIAGRAMS
•
•
The following abbreviations are used in Figure 2 to Figure 13:
t9 = Clock high time
t10 = Clock low time
t11 = Data setup time
t12 = Data hold time
In addition, refer to Table 31 for the ADV7342/ADV7343 input
configuration.
CLKIN_A
t9
CONTROL
INPUTS
t12
t10
S_HSYNC,
S_VSYNC
S7 TO S0/
Y7 TO Y0*
IN SLAVE MODE
Y0
Cb0
Y1
Cr0
Y2
Cb2
t11
Cr2
t13
CONTROL
OUTPUTS
IN MASTER/SLAVE MODE
06399-002
t14
*SELECTED BY SUBADDRESS 0x01, BIT 7.
Figure 2. SD Only, 8-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 000)
CLKIN_A
t9
CONTROL
INPUTS
t10
t12
S_HSYNC,
S_VSYNC
IN SLAVE MODE
S7 TO S0/
Y7 TO Y0*
Y0
Y7 TO Y0/
C7 TO C0*
Cb0
Y1
Y2
Y3
Cr0
Cb2
Cr2
t11
t13
CONTROL
OUTPUTS
IN MASTER/SLAVE MODE
06399-003
t14
*SELECTED BY SUBADDRESS 0x01, BIT 7.
Figure 3. SD Only, 16-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 000)
CLKIN_A
t9
CONTROL
INPUTS
t12
t10
S_HSYNC,
S_VSYNC
Y7 TO Y0
G0
C7 TO C0
B0
G1
G2
B1
B2
R1
R2
t11
S7 TO S0
R0
CONTROL
OUTPUTS
t14
t13
Figure 4. SD Only, 24-Bit, 4:4:4 RGB Pixel Input Mode (Input Mode 000)
Rev. 0 | Page 10 of 88
06399-004
•
•
•
•
t13 = Control output access time
t14 = Control output hold time
ADV7342/ADV7343
CLKIN_A
t9
CONTROL
INPUTS
t12
t10
P_HSYNC,
P_VSYNC,
P_BLANK
Y7 TO Y0
Y0
Y1
Y2
Y3
Y4
Y5
C7 TO C0
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
t11
t13
06399-005
CONTROL
OUTPUTS
t14
Figure 5. ED/HD-SDR Only, 16-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 001)
CLKIN_A
t9
CONTROL
INPUTS
t12
t10
P_HSYNC,
P_VSYNC,
P_BLANK
Y7 TO Y0
Y0
Y1
Y2
Y3
Y4
Y5
C7 TO C0
Cb0
Cb1
Cb2
Cb3
Cb4
Cb5
Cr2
Cr3
Cr4
Cr5
t11
S7 TO S0
Cr0
Cr1
CONTROL
OUTPUTS
06399-006
t14
t13
Figure 6. ED/HD-SDR Only, 24-Bit, 4:4:4 YCrCb Pixel Input Mode (Input Mode 001)
CLKIN_A
t9
P_HSYNC,
P_VSYNC,
P_BLANK
Y7 TO Y0
G0
G1
G2
G3
G4
G5
C7 TO C0
B0
B1
B2
B3
B4
B5
R2
R3
R4
R5
t11
S7 TO S0
R0
R1
CONTROL
OUTPUTS
t14
t13
Figure 7. ED/HD-SDR Only, 24-Bit, 4:4:4 RGB Pixel Input Mode (Input Mode 001)
Rev. 0 | Page 11 of 88
06399-007
CONTROL
INPUTS
t12
t10
ADV7342/ADV7343
CLKIN_A*
t9
CONTROL
INPUTS
t10
P_HSYNC,
P_VSYNC,
P_BLANK
Y7 TO Y0
Cb0
t11
Y0
Cr0
Cb2
Y1
t12
Y2
Cr2
t12
t11
t13
CONTROL
OUTPUTS
06399-008
t14
*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED
USING SUBADDRESS 0x01, BITS 1 AND 2.
Figure 8. ED/HD-DDR Only, 8-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Pixel Input Mode (Input Mode 010)
CLKIN_A*
t9
Y7 TO Y0
3FF
t11
t10
00
00
XY
t12
Cb0
Y0
Cr0
Y1
t12
t11
t13
CONTROL
OUTPUTS
06399-009
t14
*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED
USING SUBADDRESS 0x01, BITS 1 AND 2.
Figure 9. ED/HD-DDR Only, 8-Bit, 4:2:2 YCrCb (EAV/SAV) Pixel Input Mode (Input Mode 010)
CLKIN_B
t9
CONTROL
INPUTS
t12
t10
P_HSYNC,
P_VSYNC,
P_BLANK
Y7 TO Y0
Y0
Y1
Y2
Y3
Y4
Y5
Y6
C7 TO C0
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
Cb6
Cb2
Y2
Cr2
ED/HD INPUT
t11
CLKIN_A
t9
t10
t12
S_HSYNC,
S_VSYNC
S7 TO S0
SD INPUT
Cb0
Y0
Cr0
Y1
t11
Figure 10. SD and ED/HD-SDR, 16-Bit, 4:2:2 ED/HD and 8-Bit, SD Pixel Input Mode (Input Mode 011)
Rev. 0 | Page 12 of 88
06399-010
CONTROL
INPUTS
ADV7342/ADV7343
CLKIN_B
CONTROL
INPUTS
t9
P_HSYNC,
P_VSYNC,
P_BLANK
t10
EH/HD INPUT
Y0
Cb0
Y7 TO Y0
t11
Cr0
Y1
t12
Cb2
Y2
Cr2
t12
t11
CLKIN_A
t9
CONTROL
INPUTS
t12
t10
S_HSYNC,
S_VSYNC
SD INPUT
Cb0
Cr0
Y0
Y1
Cb2
Y2
Cr2
06399-011
S7 TO S0
t11
Figure 11. SD and ED/HD-DDR, 8-Bit, 4:2:2 ED/HD and 8-Bit, SD Pixel Input Mode (Input Mode 100)
CLKIN_A
CONTROL
INPUTS
t9
P_HSYNC,
P_VSYNC,
P_BLANK
t10
Cb0
Y7 TO Y0
Y0
Cr0
Y1
t12
t11
Cb2
Cr2
Y2
t13
t14
06399-012
CONTROL
OUTPUTS
Figure 12. ED Only (at 54 MHz), 8-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Pixel Input Mode (Input Mode 111)
CLKIN_A
t9
Y7 TO Y0
t11
3FF
t12
t10
00
00
XY
Cb0
Y0
Cr0
Y1
t13
t14
06399-013
CONTROL
OUTPUTS
Figure 13. ED Only (at 54 MHz), 8-Bit, 4:2:2 YCrCb (EAV/SAV) Pixel Input Mode (Input Mode 111)
Rev. 0 | Page 13 of 88
ADV7342/ADV7343
Y OUTPUT
c
P_HSYNC
P_VSYNC
a
P_BLANK
Y7 TO Y0
Y0
Y1
Y2
Y3
C7 TO C0
Cb0
Cr0
Cb2
Cr2
b
a AND b AS PER RELEVANT STANDARD.
06399-014
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
Figure 14. ED-SDR, 16-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Y OUTPUT
c
P_HSYNC
P_VSYNC
a
P_BLANK
Cb0
Y7 TO Y0
Y0
Cr0
Y1
b
a = 32 CLOCK CYCLES FOR 525p
a = 24 CLOCK CYCLES FOR 625p
AS RECOMMENDED BY STANDARD
b(MIN) = 244 CLOCK CYCLES FOR 525p
b(MIN) = 264 CLOCK CYCLES FOR 625p
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
Figure 15. ED-DDR, 8-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Rev. 0 | Page 14 of 88
06399-015
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
ADV7342/ADV7343
Y OUTPUT
c
P_HSYNC
P_VSYNC
a
P_BLANK
Y7 TO Y0
Y0
Y1
Y2
Y3
C7 TO C0
Cb0
Cr0
Cb2
Cr2
b
a AND b AS PER RELEVANT STANDARD.
06399-016
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
Figure 16. HD-SDR, 16-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Y OUTPUT
c
P_HSYNC
P_VSYNC
a
P_BLANK
Cb0
Y7 TO Y0
Y0
Cr0
Y1
b
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
Figure 17. HD-DDR, 8-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Rev. 0 | Page 15 of 88
06399-017
a AND b AS PER RELEVANT STANDARD.
ADV7342/ADV7343
S_HSYNC
S_VSYNC
Cb
Cr
Y
PAL = 264 CLOCK CYCLES
NTSC = 244 CLOCK CYCLES
*SELECTED BY SUBADDRESS 0x01, BIT 7.
Y
06399-018
Y7 TO Y0*
Figure 18. SD Input Timing Diagram (Timing Mode 1)
t5
t3
t3
SDA
t6
t1
t2
t7
t4
06399-019
SCL
t8
2
Figure 19. MPU Port Timing Diagram (I C Mode)
SPI_SS
t2
t1
t7
t3
SCLK
t6
X
D7
D6
D5
D4
D3
D2
D1
D0
MISO
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D6
D5
D4
D3
D2
D1
D0
t4
D7
t8
Figure 20. MPU Port Timing Diagram (SPI Mode)
Rev. 0 | Page 16 of 88
06399-020
t5
MOSI
ADV7342/ADV7343
ABSOLUTE MAXIMUM RATINGS
Table 11.
Parameter1
VAA to AGND
VDD to DGND
PVDD to PGND
VDD_IO to GND_IO
VAA to VDD
VDD to PVDD
VDD_IO to VDD
AGND to DGND
AGND to PGND
AGND to GND_IO
DGND to PGND
DGND to GND_IO
PGND to GND_IO
Digital Input Voltage to GND_IO
Analog Outputs to AGND
Storage Temperature Range (TS)
Junction Temperature (TJ)
Lead Temperature (Soldering, 10 sec)
1
Rating
−0.3 V to +3.9 V
−0.3 V to +2.3 V
−0.3 V to +2.3 V
−0.3 V to +3.9 V
−0.3 V to +2.2 V
−0.3 V to +0.3 V
−0.3 V to +2.2 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to VDD_IO + 0.3 V
−0.3 V to VAA
−65°C to +150°C
150°C
260°C
Analog output short circuit to any power supply or common can be of an
indefinite duration.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
The ADV7342/ADV7343 are high performance integrated
circuits with an ESD rating of <1 kV, and it is ESD sensitive.
Proper precautions should be taken for handling and assembly.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 12. Thermal Resistance1
Package Type
64-Lead LQFP
1
θJA
47
θJC
11
Unit
°C/W
Values are based on a JEDEC 4 layer test board.
The ADV7342/ADV7343 are Pb-free products. The lead finish is
100% pure Sn electroplate. The devices are RoHS compliant,
suitable for Pb-free applications up to 255°C (±5°C) IR reflow
(JEDEC STD-20).
They are backward-compatible with conventional SnPb
soldering processes. The electroplated Sn coating can be
soldered with Sn/Pb solder paste at conventional reflow
temperatures of 220°C to 235°C.
ESD CAUTION
Rev. 0 | Page 17 of 88
ADV7342/ADV7343
64 63 62 61 60 59 58
VDD_IO
1
TEST0
2
TEST1
S_VSYNC
S_HSYNC
TEST4
TEST5
S0
S1
S2
VDD
DGND
S3
S4
S5
S6
S7
CLKIN_B
GND_IO
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
57 56 55 54 53 52 51 50 49
48
SFL/MISO
47
RSET1
3
46
VREF
Y0
4
45
COMP1
Y1
5
44
DAC 1
Y2
6
43
DAC 2
Y3
7
42
DAC 3
Y4
8
41
VAA
Y5
9
40
AGND
VDD 10
39
DAC 4
DGND 11
38
DAC 5
Y6 12
37
DAC 6
Y7 13
36
RSET2
TEST2 14
35
COMP2
TEST3 15
34
PVDD
C0 16
33
EXT_LF1
PIN 1
ADV7342/ADV7343
TOP VIEW
(Not to Scale)
06399-021
PGND
EXT_LF2
CLKIN_A
C7
C6
C5
C4
C3
P_BLANK
P_VSYNC
P_HSYNC
SCL/MOSI
SDA/SCLK
ALSB/SPI_SS
C2
C1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 21. Pin Configuration
Table 13. Pin Function Descriptions
Mnemonic
Y7 to Y0
Input/
Output
I
Description
8-Bit Pixel Port. Y0 is the LSB. Refer to Table 31 for input modes.
C7 to C0
I
8-Bit Pixel Port. C0 is the LSB. Refer to Table 31 for input modes.
S7 to S0
I
8-Bit Pixel Port. S0 is the LSB. Refer to Table 31 for input modes.
TEST5 to
TEST0
CLKIN_A
CLKIN_B
I
Unused. These pins should be connected to DGND.
I
I
50
S_HSYNC
I/O
49
S_VSYNC
I/O
22
P_HSYNC
I
23
P_VSYNC
I
24
48
P_BLANK
SFL/MISO
I
I/O
47
RSET1
I
Pixel Clock Input for HD Only (74.25 MHz), ED 1 Only (27 MHz or 54 MHz) or SD Only (27 MHz).
Pixel Clock Input for Dual Modes Only. Requires a 27 MHz reference clock for ED operation or a
74.25 MHz reference clock for HD operation.
SD Horizontal Synchronization Signal. This pin can also be configured to output an SD, ED, or HD
horizontal synchronization signal. See the External Horizontal and Vertical Synchronization
Control section.
SD Vertical Synchronization Signal. This pin can also be configured to output an SD, ED, or HD
vertical synchronization signal. See the External Horizontal and Vertical Synchronization Control
section.
ED/HD Horizontal Synchronization Signal. See the External Horizontal and Vertical
Synchronization Control section.
ED/HD Vertical Synchronization Signal. See the External Horizontal and Vertical Synchronization
Control section.
ED/HD Blanking Signal. See the External Horizontal and Vertical Synchronization Control section.
Multifunctional Pin: Subcarrier Frequency Lock (SFL) Input/SPI Data Output. The SFL input is
used to drive the color subcarrier DDS system, timing reset, or subcarrier reset.
This pin is used to control the amplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For full-drive
operation (for example, into a 37.5 Ω load), a 510 Ω resistor must be connected from RSET1 to
AGND. For low drive operation (for example, into a 300 Ω load), a 4.12 kΩ resistor must be
connected from RSET1 to AGND.
Pin No.
13, 12,
9 to 4
29 to 25,
18 to 16
62 to 58,
55 to 53
52, 51, 15,
14, 3, 2
30
63
Rev. 0 | Page 18 of 88
ADV7342/ADV7343
Input/
Output
I
Pin No.
36
Mnemonic
RSET2
45, 35
21
20
19
46
41
10, 56
COMP1,
COMP2
DAC 1, DAC 2,
DAC 3
DAC 4, DAC 5,
DAC 6
SCL/MOSI
SDA/SCLK
ALSB/SPI_SS
VREF
VAA
VDD
1
34
VDD_IO
PVDD
P
P
33
31
32
40
11, 57
64
EXT_LF1
EXT_LF2
PGND
AGND
DGND
GND_IO
I
I
G
G
G
G
44, 43, 42
39, 38, 37
1
2
O
Description
This pin is used to control the amplitudes of the DAC 4, DAC 5, and DAC 6 outputs. A 4.12 kΩ
resistor must be connected from RSET2 to AGND.
Compensation Pins. Connect a 2.2 nF capacitor from both COMP pins to VAA.
O
DAC Outputs. Full and low drive capable DACs.
O
DAC Outputs. Low drive only capable DACs.
I
I/O
I
Multifunctional Pin: I2C Clock Input/SPI Data Input.
Multifunctional Pin: I2C Data Input/Output. Also, SPI clock input.
Multifunctional Pin: This signal sets up the LSB 2 of the MPU I2C address. Also, SPI slave select.
Optional External Voltage Reference Input for DACs or Voltage Reference Output.
Analog Power Supply (3.3 V).
Digital Power Supply (1.8 V). For dual-supply configurations, VDD can be connected to other 1.8 V
supplies through a ferrite bead or suitable filtering.
Input/Output Digital Power Supply (3.3 V).
PLL Power Supply (1.8 V). For dual-supply configurations, PVDD can be connected to other 1.8 V
supplies through a ferrite bead or suitable filtering.
External Loop Filter for On-Chip PLL 1.
External Loop Filter for On-Chip PLL 2.
PLL Ground Pin.
Analog Ground Pin.
Digital Ground Pin.
Input/Output Supply Ground Pin.
P
P
ED = enhanced definition = 525p and 625p.
LSB = least significant bit. In the ADV7342, setting the LSB to 0 sets the I2C address to 0xD4. Setting it to 1 sets the I2C address to 0xD6. In the ADV7343, setting the
LSB to 0 sets the I2C address to 0x54. Setting it to 1 sets the I2C address to 0x56.
Rev. 0 | Page 19 of 88
ADV7342/ADV7343
TYPICAL PERFORMANCE CHARACTERISTICS
ED Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4
Y RESPONSE IN ED 8× OVERSAMPLING MODE
1.0
0
0.5
–10
0
–0.5
–40
–50
–1.5
–60
–2.0
–70
–2.5
0
20
40
60
80 100 120 140
FREQUENCY (MHz)
160
180
200
–3.0
06399-022
–80
Figure 22. ED 8× Oversampling, PrPb Filter (Linear) Response
0
2
4
6
8
FREQUENCY (MHz)
10
12
Figure 25. ED 8× Oversampling, Y Filter Response (Focus on Pass Band)
ED Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4
HD Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4
10
0
0
–10
–10
–20
–20
–30
–30
GAIN (dB)
GAIN (dB)
–1.0
06399-025
–30
GAIN (dB)
GAIN (dB)
–20
–40
–40
–50
–60
–50
–70
–60
–80
–70
20
40
60
80 100 120 140
FREQUENCY (MHz)
160
180
200
–100
Figure 23. ED 8× Oversampling, PrPb Filter (SSAF) Response
0
18.5
37.0
55.5
74.0
92.5
FREQUENCY (MHz)
111.0
129.5
148.0
06399-026
0
06399-023
–80
–90
Figure 26. HD 4× Oversampling, PrPb (SSAF) Filter Response (4:2:2 Input)
HD Pr/Pb RESPONSE. 4:4:4 INPUT MODE
Y RESPONSE IN ED 8× OVERSAMPLING MODE
0
0
–10
–10
–20
–30
GAIN (dB)
–30
–40
–50
–40
–50
–60
–70
–60
–80
–70
0
20
40
60
80 100 120 140
FREQUENCY (MHz)
160
180
Figure 24. ED 8× Oversampling, Y Filter Response
200
–100
10 20 30 40 50 60 70 80 90 100 110 120 130 140
FREQUENCY (MHz)
06399-027
–80
–90
06399-024
GAIN (dB)
–20
Figure 27. HD 4× Oversampling, PrPb (SSAF) Filter Response (4:4:4 Input)
Rev. 0 | Page 20 of 88
ADV7342/ADV7343
Y RESPONSE IN HD 4× OVERSAMPLING MODE
10
0
0
–10
–10
MAGNITUDE (dB)
–20
GAIN (dB)
–30
–40
–50
–60
–20
–30
–40
–50
–70
–80
–60
0
18.5
37.0
55.5
74.0
92.5
FREQUENCY (MHz)
111.0
129.5
148.0
–70
06399-028
–100
0
Figure 28. HD 4× Oversampling, Y Filter Response
2
4
6
8
FREQUENCY (MHz)
10
12
06399-031
–90
Figure 31. SD PAL, Luma Low-Pass Filter Response
Y PASS BAND IN HD 4x OVERSAMPLING MODE
3.0
1.5
0
0
–10
–3.0
MAGNITUDE (dB)
–4.5
–6.0
–7.5
–20
–30
–40
–50
–9.0
–10.5
FREQUENCY (MHz)
06399-029
–60
–12.0
27.750 30.063 32.375 34.688 37.000 39.312 41.625 43.937 46.250
–70
0
2
4
6
8
FREQUENCY (MHz)
10
12
06399-032
GAIN (dB)
–1.5
Figure 29. HD 4× Oversampling, Y Filter Response (Focus on Pass Band)
Figure 32. SD NTSC, Luma Notch Filter Response
0
0
–10
MAGNITUDE (dB)
–30
–40
–50
–20
–30
–40
–50
–60
0
2
4
6
8
FREQUENCY (MHz)
10
12
Figure 30. SD NTSC, Luma Low-Pass Filter Response
–70
0
2
4
6
8
FREQUENCY (MHz)
10
Figure 33. SD PAL, Luma Notch Filter Response
Rev. 0 | Page 21 of 88
12
06399-033
–60
–70
06399-030
MAGNITUDE (dB)
–10
–20
ADV7342/ADV7343
Y RESPONSE IN SD OVERSAMPLING MODE
5
0
4
–10
MAGNITUDE (dB)
GAIN (dB)
–20
–30
–40
–50
3
2
1
–60
0
0
20
40
60
80 100 120 140
FREQUENCY (MHz)
160
180
–1
06399-034
–80
200
0
Figure 34. SD, 16× Oversampling, Y Filter Response
2
1
3
4
FREQUENCY (MHz)
5
6
7
06399-037
–70
Figure 37. SD Luma SSAF Filter, Programmable Gain
1
0
0
–20
MAGNITUDE (dB)
MAGNITUDE (dB)
–10
–30
–40
–1
–2
–3
–50
0
2
4
6
8
FREQUENCY (MHz)
10
12
–5
06399-035
–70
2
1
3
4
FREQUENCY (MHz)
5
6
7
Figure 38. SD Luma SSAF Filter, Programmable Attenuation
Figure 35. SD Luma SSAF Filter Response up to 12 MHz
0
4
–10
0
–20
MAGNITUDE (dB)
2
–2
–4
–6
–30
–40
–50
–8
–12
0
1
2
3
4
FREQUENCY (MHz)
5
6
7
–70
0
2
4
6
8
FREQUENCY (MHz)
10
Figure 39. SD Luma CIF Low-Pass Filter Response
Figure 36. SD Luma SSAF Filter, Programmable Responses
Rev. 0 | Page 22 of 88
12
06399-039
–60
–10
06399-036
MAGNITUDE (dB)
0
06399-038
–4
–60
0
–10
–10
–20
–20
–30
–40
–50
–60
–60
4
6
8
FREQUENCY (MHz)
10
12
–70
–10
–10
–20
–20
MAGNITUDE (dB)
0
–30
–40
–60
–60
6
8
FREQUENCY (MHz)
10
12
–70
06399-041
4
6
8
FREQUENCY (MHz)
10
0
2
4
8
6
FREQUENCY (MHz)
10
Figure 44. SD Chroma 1.0 MHz Low-Pass Filter Response
0
0
–10
–10
–20
–20
MAGNITUDE (dB)
Figure 41. SD Chroma 3.0 MHz Low-Pass Filter Response
–30
–40
–40
–60
–60
2
4
6
8
FREQUENCY (MHz)
10
12
06399-042
–50
0
–70
0
2
4
6
8
FREQUENCY (MHz)
10
Figure 45. SD Chroma 0.65 MHz Low-Pass Filter Response
Figure 42. SD Chroma 2.0 MHz Low-Pass Filter Response
Rev. 0 | Page 23 of 88
12
–30
–50
–70
12
–40
–50
2
4
–30
–50
0
2
Figure 43. SD Chroma 1.3 MHz Low-Pass Filter Response
0
–70
0
06399-044
2
12
06399-045
0
Figure 40. SD Luma QCIF Low-Pass Filter Response
MAGNITUDE (dB)
–40
–50
–70
MAGNITUDE (dB)
–30
06399-043
MAGNITUDE (dB)
0
06399-040
MAGNITUDE (dB)
ADV7342/ADV7343
0
–10
–10
–20
–20
–30
–40
–30
–40
–50
–50
–60
–60
–70
0
2
4
6
8
FREQUENCY (MHz)
10
12
Figure 46. SD Chroma CIF Low-Pass Filter Response
–70
0
2
4
6
8
FREQUENCY (MHz)
10
Figure 47. SD Chroma QCIF Low-Pass Filter Response
Rev. 0 | Page 24 of 88
12
06399-047
MAGNITUDE (dB)
0
06399-046
MAGNITUDE (dB)
ADV7342/ADV7343
ADV7342/ADV7343
MPU PORT DESCRIPTION
Devices such as a microprocessor can communicate with the
ADV7342/ADV7343 through one of the following protocols:
•
•
2-wire serial (I2C-compatible) bus
4-wire serial (SPI-compatible) bus
After power-up or reset, the MPU port is configured for I2C
operation. SPI operation can be invoked at any time by
following the procedure outlined in the SPI Operation section.
I2C OPERATION
The ADV7342/ADV7343 support a 2-wire serial (I2C-compatible)
microprocessor bus driving multiple peripherals. This port
operates in an open-drain configuration. Two inputs, serial data
(SDA) and serial clock (SCL), carry information between any
device connected to the bus and the ADV7342/ADV7343. Each
slave device is recognized by a unique address. The ADV7342/
ADV7343 have four possible slave addresses for both read and
write operations. These are unique addresses for each device
and are illustrated in Figure 48. The LSB either sets a read or
write operation. Logic 1 corresponds to a read operation, while
Logic 0 corresponds to a write operation. A1 is controlled by
setting the ALSB/SPI_SS pin of the ADV7342/ADV7343 to
Logic 0 or Logic 1.
1
1
0
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB/SPI_SS
0
1
WRITE
READ
06399-048
READ/WRITE
CONTROL
Figure 48. ADV7342 Slave Address = 0xD4 or 0xD6
line low during the ninth clock pulse. This is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition
occurs when the device monitors the SDA and SCL lines
waiting for the start condition and the correct transmitted
address. The R/W bit determines the direction of the data.
Logic 0 on the LSB of the first byte means that the master writes
information to the peripheral. Logic 1 on the LSB of the first byte
means that the master reads information from the peripheral.
The ADV7342/ADV7343 act as a standard slave device on the
bus. The data on the SDA pin is eight bits long, supporting the
7-bit addresses plus the R/W bit. It interprets the first byte as
the device address and the second byte as the starting
subaddress. There is a subaddress auto-increment facility. This
allows data to be written to or read from registers in ascending
subaddress sequence starting at any valid subaddress. A data
transfer is always terminated by a stop condition. The user can
also access any unique subaddress register on a one-by-one
basis without updating all the registers.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCL high period, the
user should issue only a start condition, a stop condition, or a
stop condition followed by a start condition. If an invalid
subaddress is issued by the user, the ADV7342/ADV7343 do
not issue an acknowledge and do return to the idle condition. If
the user utilizes the auto-increment method of addressing the
encoder and exceeds the highest subaddress, the following
actions are taken:
•
To control the various devices on the bus, use the following
protocol. The master initiates a data transfer by establishing
a start condition, defined by a high-to-low transition on SDA
while SCL remains high. This indicates that an address/data
stream follows. All peripherals respond to the start condition
and shift the next eight bits (7-bit address + R/W bit). The bits
are transferred from MSB down to LSB. The peripheral that
recognizes the transmitted address responds by pulling the data
•
Rev. 0 | Page 25 of 88
In read mode, the highest subaddress register contents are
output until the master device issues a no acknowledge.
This indicates the end of a read. A no acknowledge
condition occurs when the SDA line is not pulled low on
the ninth pulse.
In write mode, the data for the invalid byte is not loaded
into any subaddress register, a no acknowledge is issued by
the ADV7342/ADV7343, and the parts return to the idle
condition.
ADV7342/ADV7343
Figure 49 shows an example of data transfer for a write sequence and the start and stop conditions. Figure 50 shows bus write and read
sequences.
SCL
S
9
1–7
8
START ADDR R/W ACK
9
1–7
8
SUBADDRESS ACK
1–7
DATA
8
9
ACK
P
STOP
06399-049
SDA
Figure 49. I2C Data Transfer
S
SLAVE ADDR
A(S)
SUBADDR
A(S)
DATA
S
SLAVE ADDR
S = START BIT
P = STOP BIT
A(S)
A(S) P
LSB = 1
LSB = 0
READ
SEQUENCE
DATA
A(S)
SUBADDR
A(S) S SLAVE ADDR
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S)
DATA
A(M)
A (S) = NO-ACKNOWLEDGE BY SLAVE
A (M) = NO-ACKNOWLEDGE BY MASTER
DATA
A(M) P
06399-050
WRITE
SEQUENCE
Figure 50. I2C Read and Write Sequence
SPI OPERATION
The ADV7342/ADV7343 support a 4-wire serial (SPI-compatible)
bus connecting multiple peripherals. Two inputs, master out
slave in (MOSI) and serial clock (SCLK), and one output,
master in slave out (MISO), carry information between a
master SPI peripheral on the bus and the ADV7342/ADV7343.
Each slave device on the bus has a slave select pin that is
connected to the master SPI peripheral by a unique slave select
line. As such, slave device addressing is not required.
To invoke SPI operation, a master SPI peripheral (for example,
a microprocessor) should issue three low pulses on the ADV7342/
ADV7343 ALSB/SPI_SS pin. When the encoder detects the
third rising edge on the ALSB/SPI_SS pin, it automatically
switches to SPI communication mode. The ADV7342/ADV7343
remain in SPI communication mode until a reset or powerdown occurs.
To control the ADV7342/ADV7343, use the following protocol
for both read and write transactions. First, the master initiates a
data transfer by driving and holding the ADV7342/ADV7343
ALSB/SPI_SS pin low. On the first SCLK rising edge after
ALSB/SPI_SS has been driven low, the write command, defined
as 0xD4, is written to the ADV7342/ADV7343 over the MOSI
line. The second byte written to the MOSI line is interpreted as
the starting subaddress. Data on the MOSI line is written MSB
first and clocked on the rising edge of SCLK.
There is a subaddress auto-increment facility. This allows data
to be written to or read from registers in ascending subaddress
sequence starting at any valid subaddress. The user can also
access any unique subaddress register on a one-by-one basis.
In a write data transfer, 8-bit data bytes are written to the
ADV7342/ADV7343, MSB first, on the MOSI line immediately
after the starting subaddress. The data bytes are clocked into the
ADV7342/ADV7343 on the rising edge of SCLK. When all data
bytes have been written, the master completes the transfer by
driving and holding the ALSB/SPI_SS pin high.
In a read data transfer, after the subaddress has been clocked in
on the MOSI line, the ALSB/SPI_SS pin is driven and held high
for at least one clock cycle. Then, the ALSB/SPI_SS pin is driven
and held low again. On the first SCLK rising edge after
ALSB/SPI_SS has been driven low, the read command, defined
as 0xD5, is written, MSB first, to the ADV7342/ADV7343 over
the MOSI line. Subsequently, 8-bit data bytes are read from the
ADV7342/ADV7343, MSB first, on the MISO line. The data
bytes are clocked out of the ADV7342/ADV7343 on the falling
edge of SCLK. When all data bytes have been read, the master
completes the transfer by driving and holding the ALSB/SPI_SS
pin high.
Rev. 0 | Page 26 of 88
ADV7342/ADV7343
REGISTER MAP ACCESS
A microprocessor can read from or write to all registers of the
ADV7342/ADV7343 via the MPU port, except for registers that
are specified as read-only or write-only registers.
The subaddress register determines which register the next
read or write operation accesses. All communication through
the MPU port starts with an access to the subaddress register.
A read/write operation is then performed from/to the target
address, which increments to the next address until the
transaction is complete.
REGISTER PROGRAMMING
Table 14 to Table 28 describe the functionality of each register.
All registers can be read from as well as written to, unless
otherwise stated.
SUBADDRESS REGISTER (SR7 TO SR0)
The subaddress register is an 8-bit write-only register. After the
MPU port is accessed and a read/write operation is selected, the
subaddress is set up. The subaddress register determines to or
from which register the operation takes place.
Table 14. Register 0x00
SR7 to
SR0
0x00
Register
Power
Mode
Register
Bit Description
Sleep Mode. With this control enabled, the current consumption is
reduced to μA level. All DACs and the internal PLL circuit are
disabled. I2C registers can be read from and written to in sleep mode.
7
6
Bit Number
5 4 3 2
0
1
DAC 3: Power on/off.
0
1
DAC 2: Power on/off.
0
1
DAC 1: Power on/off.
0
1
DAC 6: Power on/off.
0
1
DAC 5: Power on/off.
0
1
0
1
Rev. 0 | Page 27 of 88
0
0
1
PLL and Oversampling Control. This control allows the internal PLL
circuit to be powered down and the oversampling to be switched off.
DAC 4: Power on/off.
1
Register
Setting
Sleep
mode off.
Sleep
mode on.
PLL on.
PLL off.
DAC 3 off.
DAC 3 on.
DAC 2 off.
DAC 2 on.
DAC 1 off.
DAC 1 on.
DAC 6 off.
DAC 6 on.
DAC 5 off.
DAC 5 on.
DAC 4 off.
DAC 4 on.
Reset
Value
0x12
ADV7342/ADV7343
Table 15. Register 0x01 to Register 0x09
SR7 to
SR0
0x01
Register
Mode Select
Register
Bit Description
Reserved.
DDR Clock Edge Alignment.
Note: Only used for ED 1 and
HD DDR modes.
7
Reserved.
Input Mode.
Note: See Reg. 0x30, Bits[7:3]
for ED/HD format selection.
Y/C/S Bus Swap.
0x02
Mode
Register 0
6
Bit Number
5 4 3 2
1
0
0
0
1
1
1
0
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
SD Sync Output Enable.
0x06
0x07
0x08
0x09
1
2
0
1
0
1
0 must be written to these bits.
Disabled.
Enabled.
Disable manual CSC matrix adjust.
Enable manual CSC matrix adjust.
No sync.
Sync on all RGB outputs.
RGB component outputs.
YPrPb component outputs.
No sync output.
Output SD syncs on S_HSYNC and
S_VSYNC pins.
0x20
No sync output.
Output ED/HD syncs on S_HSYNC and
S_VSYNC pins.
ED/HD CSC
Matrix 0
ED/HD CSC
Matrix 1
ED/HD CSC
Matrix 2
ED/HD CSC
Matrix 3
ED/HD CSC
Matrix 4
ED/HD CSC
Matrix 5
ED/HD CSC
Matrix 6
0
0
1
RGB/YPrPb Output Select.
0x05
SD input only.
ED/HD-SDR input only.
ED/HD-DDR input only.
SD and ED/HD-SDR.
SD and ED/HD-DDR.
Reserved.
Reserved.
ED only (at 54 MHz).
Allows data to be applied to data ports in
various configurations (SD feature only).
0
1
Sync on RGB.
0x04
Reset
Value
0x00
Chroma clocked in on rising clock edge;
luma clocked in on falling clock edge.
Reserved.
Reserved.
Luma clocked in on rising clock edge;
chroma clocked in on falling clock edge.
0
1
0
1
0
1
0
1
Manual CSC Matrix Adjust.
0x03
Register Setting
0
0
0
0
0
1
1
1
1
Reserved.
Test Pattern Black Bar. 2
ED/HD Sync Output Enable.
0
0
x
x
LSBs for GY.
0x03
x
x
0xF0
x
x
x
x
x
x
x
x
x
x
x
x
LSBs for RV.
LSBs for BU.
LSBs for GV.
LSBs for GU.
Bits[9:2 ] for GY.
x
x
x
x
x
x
x
x
Bits[9:2] for GU.
0x0E
x
x
x
x
x
x
x
x
Bits[9:2] for GV.
0x24
x
x
x
x
x
x
x
x
Bits[9:2] for BU.
0x92
x
x
x
x
x
x
x
x
Bits[9:2] for RV.
0x7C
x
x
ED = enhanced definition = 525p and 625p.
Subaddress 0x31, Bit 2 must also be enabled (ED/HD). Subaddress 0x84, Bit 6 must also be enabled (SD).
Rev. 0 | Page 28 of 88
0x4E
ADV7342/ADV7343
Table 16. Register 0x0A to Register 0x10
SR7 to
SR0
0x0A
Register
DAC 4, DAC 5, DAC 6
Output Levels
Bit Description
Positive Gain to DAC Output Voltage.
Negative Gain to DAC Output Voltage.
0x0B
DAC 1, DAC 2, DAC 3
Output Levels
Positive Gain to DAC Output Voltage.
Negative Gain to DAC Output Voltage.
0x0D
DAC Power Mode
7
0
0
0
…
0
0
1
1
1
…
1
0
0
0
…
0
0
1
1
1
…
1
6
0
0
0
…
0
1
1
1
0
…
1
0
0
0
…
0
1
1
1
0
…
1
5
0
0
0
…
1
0
0
0
0
…
1
0
0
0
…
1
0
0
0
0
…
1
Bit Number
4
3
0
0
0
0
0
0
… …
1
1
0
0
0
0
0
0
0
0
… …
1
1
0
0
0
0
0
0
… …
1
1
0
0
0
0
0
0
0
0
… …
1
1
2
0
0
0
…
1
0
0
0
0
…
1
0
0
0
…
1
0
0
0
0
…
1
1
0
0
1
…
1
0
0
0
1
…
1
0
0
1
…
1
0
0
0
1
…
1
DAC 1 Low Power Enable.
0
0
1
0
…
1
0
0
1
0
…
1
0
1
0
…
1
0
0
1
0
…
1
0
1
DAC 2 Low Power Enable.
0
1
DAC 3 Low Power Enable.
0
1
0x10
Cable Detection
Reserved.
DAC 1 Cable Detect
(Read Only).
0
0
0
0
1
DAC 2 Cable Detect
(Read Only).
0
1
0
0
1
Reserved.
0
0
Rev. 0 | Page 29 of 88
0
Reset
Value
0x00
0x00
0x00
0
0
Reserved.
Unconnected DAC
Auto Power-Down.
Register Setting
0%
+0.018%
+0.036%
…
+7.382%
+7.5%
−7.5%
−7.382%
−7.364%
…
−0.018%
0%
+0.018%
+0.036%
…
+7.382%
+7.5%
−7.5%
−7.382%
−7.364%
…
−0.018%
DAC 1 low power
disabled
DAC 1 low power
enabled
DAC 2 low power
disabled
DAC 2 low power
enabled
DAC 3 low power
disabled
DAC 3 low power
enabled
Cable detected on
DAC 1
DAC 1 unconnected
Cable detected on
DAC 2
DAC 2 unconnected
0
DAC auto powerdown disable
DAC auto powerdown enable
0x00
ADV7342/ADV7343
Table 17. Register 0x12 to Register 0x17
SR7 to
SR0
0x12
0x13
0x14
0x16
Register
Pixel Port Readback (S Bus)
Pixel Port Readback (Y Bus)
Pixel Port Readback (C Bus)
Control Port Readback
Bit Description
S[7:0] Readback.
Y[7:0] Readback.
C[7:0] Readback.
P_BLANK.
P_VSYNC.
7
x
x
x
6
x
x
x
Bit Number
5 4 3 2
x x x x
x x x x
x x x x
Reset
Value
0xXX
0xXX
0xXX
0xXX
x
x
S_HSYNC.
SFL/MISO.
Reserved.
Reserved.
Software Reset.
Reserved.
Register Setting
Read only
Read only
Read only
Read only
x
S_VSYNC.
Software Reset
0
x
x
x
x
x
P_HSYNC.
0x17
1
x
x
x
x
0
0
0
0
1
0
0
0
Rev. 0 | Page 30 of 88
0
0
0
0x00
Writing a 1 resets the device;
this is a self-clearing bit
ADV7342/ADV7343
Table 18. Register 0x30
SR7 to
SR0
0x30
Register
ED/HD Mode
Register 1
Bit Description
ED/HD Output Standard.
7
6
Bit Number
5 4 3 2
ED/HD Input
Synchronization
Format.
ED/HD Input Mode.
0
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
0
0
1
1
1
1
1
1
0
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0 0 1 0
10011–11111
Register Setting
EIA770.2 output.
EIA770.3 output.
EIA770.1 output
Output levels for full
input range.
Reserved.
External HSYNC, VSYNC
and field inputs. 1
Embedded EAV/SAV
codes.
SMPTE 293M,
ITU-BT.1358.
Nonstandard timing mode.
BTA-1004, ITU-BT.1362.
ITU-BT.1358.
ITU-BT.1362.
SMPTE 296M-1,
SMPTE 274M-2.
SMPTE 296M-3.
SMPTE 296M-4,
SMPTE 274M-5.
SMPTE 296M-6.
SMPTE 296M-7,
SMPTE 296M-8.
SMPTE 240M.
Reserved.
Reserved.
SMPTE 274M-4,
SMPTE 274M-5.
SMPTE 274M-6.
SMPTE 274M-7,
SMPTE 274M-8.
SMPTE 274M-9.
SMPTE 274M-10,
SMPTE 274M-11.
ITU-R BT.709-5.
Reserved.
Note
ED
HD
525p @ 59.94 Hz
525p @ 59.94 Hz
625p @ 50 Hz
625p @ 50 Hz
720p @ 60/59.94 Hz
720p @ 50 Hz
720p @ 30/29.97 Hz
720p @ 25 Hz
720p @ 24/23.98 Hz
1035i @ 60/59.94 Hz
1080i @ 30/29.97 Hz
1080i @ 25 Hz
1080p @ 0/29.97 Hz
1080p @ 25 Hz
1080p @ 4/23.98 Hz
1080Psf @ 24 Hz
Synchronization can be controlled with a combination of either HSYNC and VSYNC inputs or HSYNC and field inputs, depending on Subaddress 0x34, Bit 6.
Rev. 0 | Page 31 of 88
Reset
Value
0x00
ADV7342/ADV7343
Table 19. Register 0x31 to Register 0x33
SR7 to
SR0
0x31
Register
ED/HD Mode
Register 2
Bit Description
ED/HD Pixel Data Valid.
7
6
Bit Number
5 4 3 2
Reserved.
ED/HD Test Pattern Enable.
0
1
0
1
ED/HD Undershoot Limiter.
0
0
1
1
ED/HD Y Delay with Respect to Falling
Edge of HSYNC.
0
0
0
0
1
ED/HD Color Delay with Respect to
Falling Edge of HSYNC.
0
0
0
0
1
ED/HD CGMS.
0
0
1
1
0
0
0
1
1
0
0
1
0
1
0
0
1
ED/HD Cr/Cb Sequence.
0
1
Reserved.
Sinc Compensation Filter on DAC 1,
DAC 2, DAC 3.
0
0
1
Reserved.
ED/HD Chroma SSAF.
0
0
1
ED/HD Chroma Input.
ED/HD Double Buffering.
0
1
0
1
0
0
1
ED/HD CGMS CRC.
ED/HD Mode
Register 4
0
1
0
1
0
1
ED/HD Sharpness Filter.
0x33
Register Setting
Pixel data valid off.
Pixel data valid on.
Reset
Value
0x00
0
ED/HD VBI Open.
ED/HD Mode
Register 3
0
0
1
0
1
ED/HD Test Pattern Hatch/Field.
0x32
1
0
1
0
1
Rev. 0 | Page 32 of 88
0
ED/HD test pattern off.
ED/HD test pattern on.
Hatch.
Field/frame.
Disabled.
Enabled.
Disabled.
−11 IRE
−6 IRE
−1.5 IRE
Disabled.
Enabled.
0 clock cycles.
1 clock cycle.
2 clock cycles.
3 clock cycles.
4 clock cycles.
0 clock cycles.
1 clock cycle.
2 clock cycles.
3 clock cycles.
4 clock cycles.
Disabled.
Enabled.
Disabled.
Enabled.
Cb after falling edge of HSYNC.
Cr after falling edge of HSYNC.
0 must be written to these bits.
Disabled.
Enabled.
0 must be written to this bit.
Disabled.
Enabled.
4:4:4
4:2:2
Disabled.
Enabled.
0x00
0x68
ADV7342/ADV7343
Table 20. Register 0x34 to Register 0x35
SR7 to
SR0
0x34
Register
ED/HD Mode
Register 5
Bit Description
ED/HD Timing Reset.
7
6
Bit Number
5 4 3 2
ED/HD HSYNC Control. 1
0
1
ED/HD Blank Polarity.
ED/HD Mode
Register 6
Macrovision disabled.
Macrovision enabled.
0 must be written to this bit.
0
0
1
ED/HD VSYNC/Field Input.
0 = field input.
1 = VSYNC input.
0
1
Update field/line counter.
Field/line counter free running.
Reserved.
ED/HD RGB Input Enable.
0
0
1
ED/HD Sync on PrPb.
0
1
ED/HD Color DAC Swap.
0
1
ED/HD Gamma
Correction Curve Select.
0
1
ED/HD Gamma
Correction Enable.
0
1
ED/HD Adaptive
Filter Mode.
ED/HD Adaptive
Filter Enable
1
2
Reset
Value
0x48
P_BLANK active high.
P_BLANK active low.
0
1
Reserved.
Register Setting
Internal ED/HD timing counters enabled.
Resets the internal ED/HD timing counters.
HSYNC output control (refer to Table 51).
VSYNC output control (refer to Table 52).
0
1
ED Macrovision Enable.
0x35
0
0
1
0
1
ED/HD VSYNC Control.1
Horizontal/Vertical
Counters. 2
1
0
1
0
1
0x00
Disabled.
Enabled.
Disabled.
Enabled.
DAC 2 = Pb, DAC 3 = Pr.
DAC 2 = Pr, DAC 3 = Pb.
Gamma Correction Curve A.
Gamma Correction Curve B.
Disabled.
Enabled.
Mode A.
Mode B.
Disabled.
Enabled.
Used in conjunction with ED/HD sync in Subaddress 0x02, Bit 7, set to 1.
When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
Rev. 0 | Page 33 of 88
ADV7342/ADV7343
Table 21. Register 0x36 to Register 0x43
SR7 to
SR0
0x36
0x37
0x38
0x39
0x40
0x41
0x42
0x43
1
Register
ED/HD Y Level 1
ED/HD Cr Level1
ED/HD Cb Level1
ED/HD Mode
Register 7
ED/HD Sharpness
Filter Gain
ED/HD CGMS
Data 0
ED/HD CGMS
Data 1
ED/HD CGMS
Data 2
Bit Description
ED/HD Test Pattern Y Level.
ED/HD Test Pattern Cr Level.
ED/HD Test Pattern Cb Level.
Reserved.
ED/HD EIA/CEA-861B
Synchronization Compliance.
7
x
x
x
6
x
x
x
Reserved.
ED/HD Sharpness Filter Gain,
Value A.
0
ED/HD Sharpness Filter Gain,
Value B.
ED/HD CGMS Data Bits.
0
0
…
0
1
…
1
0
0
0
…
1
0
…
1
0
0
0
…
1
0
…
1
0
ED/HD CGMS Data Bits.
C15
C14
ED/HD CGMS Data Bits.
C7
C6
Bit Number
4
3
x
x
x
x
x
x
0
0
5
x
x
x
2
x
x
x
0
1
x
x
x
0
0
x
x
x
0
0
1
Register Setting
Y level value
Cr level value
Cb level value
Reset
Value
0xA0
0x80
0x80
Disabled
Enabled
0
0
0
…
0
1
…
1
0
0
…
1
0
…
1
0
0
…
1
0
…
1
0
1
…
1
0
…
1
0x00
C16
Gain A = 0
Gain A = +1
…
Gain A = +7
Gain A = −8
…
Gain A = −1
Gain B = 0
Gain B = +1
…
Gain B = +7
Gain B = −8
…
Gain B = −1
CGMS C19 to C16
0
1
…
1
0
…
1
0
C19
C18
C17
C13
C12
C11
C10
C9
C8
CGMS C15 to C8
0x00
C5
C4
C3
C2
C1
C0
CGMS C7 to C0
0x00
0x00
For use with ED/HD internal test patterns only (Subaddress 0x31, Bit 2 = 1).
Table 22. Register 0x44 to Register 0x57
SR7 to
SR0
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
Register
ED/HD Gamma A0
ED/HD Gamma A1
ED/HD Gamma A2
ED/HD Gamma A3
ED/HD Gamma A4
ED/HD Gamma A5
ED/HD Gamma A6
ED/HD Gamma A7
ED/HD Gamma A8
ED/HD Gamma A9
ED/HD Gamma B0
ED/HD Gamma B1
ED/HD Gamma B2
ED/HD Gamma B3
ED/HD Gamma B4
ED/HD Gamma B5
ED/HD Gamma B6
ED/HD Gamma B7
ED/HD Gamma B8
ED/HD Gamma B9
Bit Description
ED/HD Gamma Curve A (Point 24).
ED/HD Gamma Curve A (Point 32).
ED/HD Gamma Curve A (Point 48).
ED/HD Gamma Curve A (Point 64).
ED/HD Gamma Curve A (Point 80).
ED/HD Gamma Curve A (Point 96).
ED/HD Gamma Curve A (Point 128).
ED/HD Gamma Curve A (Point 160).
ED/HD Gamma Curve A (Point 192).
ED/HD Gamma Curve A (Point 224).
ED/HD Gamma Curve B (Point 24).
ED/HD Gamma Curve B (Point 32).
ED/HD Gamma Curve B (Point 48).
ED/HD Gamma Curve B (Point 64).
ED/HD Gamma Curve B (Point 80).
ED/HD Gamma Curve B (Point 96).
ED/HD Gamma Curve B (Point 128).
ED/HD Gamma Curve B (Point 160).
ED/HD Gamma Curve B (Point 192).
ED/HD Gamma Curve B (Point 224).
7
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Rev. 0 | Page 34 of 88
6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
5
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Bit Number
4
3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
2
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Register
Setting
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
Reset
Value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
ADV7342/ADV7343
Table 23. Register 0x58 to Register 0x5D
SR7 to
SR0
0x58
0x59
Register
ED/HD Adaptive Filter Gain 1
ED/HD Adaptive Filter Gain 2
Bit Description
ED/HD Adaptive Filter Gain 1,
Value A.
7
6
5
ED/HD Adaptive Filter Gain 1,
Value B.
0
0
…
0
1
…
1
0
0
…
1
0
…
1
0
0
…
1
0
…
1
ED/HD Adaptive Filter Gain 2,
Value A.
ED/HD Adaptive Filter Gain 2,
Value B.
0x5A
ED/HD Adaptive Filter Gain 3
0x5C
0x5D
ED/HD Adaptive Filter
Threshold A
ED/HD Adaptive Filter
Threshold B
ED/HD Adaptive Filter
Threshold C
0
0
…
1
0
…
1
0
0
…
1
0
…
1
ED/HD Adaptive Filter Gain 3,
Value A.
Reset
Value
0x00
x
Register
Setting
Gain A = 0
Gain A = +1
…
Gain A = +7
Gain A = −8
…
Gain A = −1
Gain B = 0
Gain B = +1
…
Gain B = +7
Gain B = −8
…
Gain B = −1
Gain A = 0
Gain A = +1
…
Gain A = +7
Gain A = −8
…
Gain A = −1
Gain B = 0
Gain B = +1
…
Gain B = +7
Gain B = −8
…
Gain B = −1
Gain A = 0
Gain A = +1
…
Gain A = +7
Gain A = −8
…
Gain A = −1
Gain B = 0
Gain B = +1
…
Gain B = +7
Gain B = −8
…
Gain B = −1
Threshold A
2
0
0
…
1
0
…
1
1
0
0
…
1
0
…
1
0
0
1
…
1
0
…
1
0
0
…
1
0
…
1
0
0
…
1
0
…
1
0
1
…
1
0
…
1
0
0
…
1
0
…
1
0
0
…
1
0
…
1
0
1
…
1
0
…
1
x
x
0x00
0x00
ED/HD Adaptive Filter Threshold A.
0
0
…
0
1
…
1
x
0
0
…
1
0
…
1
x
0
0
…
1
0
…
1
x
ED/HD Adaptive Filter Threshold B.
x
x
x
x
x
x
x
x
Threshold B
0x00
ED/HD Adaptive Filter Threshold C.
x
x
x
x
x
x
x
x
Threshold C
0x00
ED/HD Adaptive Filter Gain 3,
Value B.
0x5B
0
0
…
0
1
…
1
Bit Number
4
3
0
0
…
0
1
…
1
0
1
…
1
0
…
1
0
0
…
0
1
…
1
0
1
…
1
0
…
1
0
0
…
0
1
…
1
0
1
…
1
0
…
1
x
x
Rev. 0 | Page 35 of 88
0x00
ADV7342/ADV7343
Table 24. Register 0x5E to Register 0x6E
SR7 to
SR0
0x5E
Register
ED/HD CGMS Type B
Register 0
Bit Description
ED/HD CGMS Type B
Enable.
7
6
5
Bit Number
4
3
2
ED/HD CGMS Type B
CRC Enable.
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
ED/HD CGMS Type B
Register 1
ED/HD CGMS Type B
Register 2
ED/HD CGMS Type B
Register 3
ED/HD CGMS Type B
Register 4
ED/HD CGMS Type B
Register 5
ED/HD CGMS Type B
Register 6
ED/HD CGMS Type B
Register 7
ED/HD CGMS Type B
Register 8
ED/HD CGMS Type B
Register 9
ED/HD CGMS Type B
Register 10
ED/HD CGMS Type B
Register 11
ED/HD CGMS Type B
Register 12
ED/HD CGMS Type B
Register 13
ED/HD CGMS Type B
Register 14
ED/HD CGMS Type B
Register 15
ED/HD CGMS Type B
Register 16
ED/HD CGMS Type B
Header Bits.
ED/HD CGMS Type B
Data Bits.
ED/HD CGMS Type B
Data Bits.
ED/HD CGMS Type B
Data Bits.
ED/HD CGMS Type B
Data Bits.
ED/HD CGMS Type B
Data Bits.
ED/HD CGMS Type B
Data Bits.
ED/HD CGMS Type B
Data Bits.
ED/HD CGMS Type B
Data Bits.
ED/HD CGMS Type B
Data Bits.
ED/HD CGMS Type B
Data Bits.
ED/HD CGMS Type B
Data Bits.
ED/HD CGMS Type B
Data Bits.
ED/HD CGMS Type B
Data Bits.
ED/HD CGMS Type B
Data Bits.
ED/HD CGMS Type B
Data Bits.
ED/HD CGMS Type B
Data Bits.
1
0
0
1
0
1
Register
Setting
Disabled
Enabled
Disabled
Enabled
H5 to H0
Reset
Value
0x00
H5
H4
H3
H2
H1
H0
P7
P6
P5
P4
P3
P2
P1
P0
P7 to P0
0x00
P15
P14
P13
P12
P11
P10
P9
P8
P15 to P8
0x00
P23
P22
P21
P20
P19
P18
P17
P16
P23 to P16
0x00
P31
P30
P29
P28
P27
P26
P25
P24
P31 to P24
0x00
P39
P38
P37
P36
P35
P34
P33
P32
P39 to P32
0x00
P47
P46
P45
P44
P43
P42
P41
P40
P47 to P40
0x00
P55
P54
P53
P52
P51
P50
P49
P48
P55 to P48
0x00
P63
P62
P61
P60
P59
P58
P57
P56
P63 to P56
0x00
P71
P70
P69
P68
P67
P66
P65
P64
P71 to P64
0x00
P79
P78
P77
P76
P75
P74
P73
P72
P79 to P72
0x00
P87
P86
P85
P84
P83
P82
P81
P80
P87 to P80
0x00
P95
P94
P93
P92
P91
P90
P89
P88
P95 to P88
0x00
P103
P102
P101
P100
P99
P98
P97
P96
P103 to P96
0x00
P111
P110
P109
P108
P107
P106
P105
P104
P111 to P104
0x00
P119
P118
P117
P116
P115
P114
P113
P112
P119 to P112
0x00
P127
P126
P125
P124
P123
P122
P121
P120
P127 to P120
0x00
Rev. 0 | Page 36 of 88
ADV7342/ADV7343
Table 25. Register 0x80 to Register 0x83
SR7 to
SR0
0x80
Register
SD Mode
Register 1
Bit Description
SD Standard.
7
6
Bit Number
5 4 3 2
SD Luma Filter.
SD Chroma Filter.
0x82
SD Mode
Register 2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SD PrPb SSAF.
0
1
0
1
SD DAC Output 2.
0
1
SD Pedestal.
0
1
SD VCR FF/RW Sync.
0
1
SD Pixel Data Valid.
SD Mode
Register 3
0
1
0
1
SD Pedestal on YPrPb
Output.
0
1
SD Output Levels Y.
0
1
SD Output Levels PrPb.
0
0
1
1
SD VBI Open.
0
1
SD Closed Captioning
Field Control.
Reserved.
0
0
1
1
0
1
0
1
0
Rev. 0 | Page 37 of 88
0
1
0
1
Register Setting
NTSC.
PAL B/D/G/H/I.
PAL M.
PAL N.
LPF NTSC.
LPF PAL.
Notch NTSC.
Notch PAL.
SSAF luma.
Luma CIF.
Luma QCIF.
Reserved.
1.3 MHz.
0.65 MHz.
1.0 MHz.
2.0 MHz.
Reserved.
Chroma CIF.
Chroma QCIF.
3.0 MHz.
Disabled.
Enabled.
Refer to Table 32 in the Output
Configuration section.
Reset
Value
0x10
0x0B
Refer to Table 32 in the Output
Configuration section.
0
1
SD Square Pixel Mode.
SD Active Video Edge Control.
0
0
1
0
1
0
1
0
1
0
1
0
1
SD DAC Output 1.
0x83
1
0
0
1
1
Disabled.
Enabled.
Disabled.
Enabled.
Disabled.
Enabled.
Disabled.
Enabled.
Disabled.
Enabled.
No pedestal on YPrPb.
7.5 IRE pedestal on YPrPb.
Y = 700 mV/300 mV.
Y = 714 mV/286 mV.
700 mV p-p (PAL), 1000 mV p-p (NTSC).
700 mV p-p.
1000 mV p-p.
648 mV p-p.
Disabled.
Enabled.
Closed captioning disabled.
Closed captioning on odd field only.
Closed captioning on even field only.
Closed captioning on both fields.
Reserved.
0x04
ADV7342/ADV7343
Table 26. Register 0x84 to Register 0x89
SR7 to
SR0
0x84
Register
SD Mode
Register 4
Bit Description
SD VSYNC-3H.
7
6
Bit Number
5 4 3 2
1
0
0
1
1
0
1
0
1
SD SFL/SCR/TR Mode Select.
SD Active Video Length.
0
1
SD Chroma.
0
1
SD Burst.
0
1
SD Color Bars.
SD Luma/Chroma Swap.
0x86
SD Mode
Register 5
0
1
0
1
NTSC Color Subcarrier Adjust (Delay
from the falling edge of output
HSYNC pulse to start of color burst).
Reserved.
SD EIA/CEA-861B Synchronization
Compliance.
0x87
SD Mode
Register 6
0
0
1
0
1
0
1
1
0
1
Disabled.
Subcarrier phase reset mode enabled.
Timing reset mode enabled.
SFL mode enabled.
720 pixels.
710 (NTSC), 702 (PAL).
Chroma enabled.
Chroma disabled.
Enabled.
Disabled.
Disabled.
Enabled.
DAC 2 = luma, DAC 3 = chroma.
DAC 2 = chroma, DAC 3 = luma.
5.17 μs.
5.31 μs.
5.59 μs (must be set for Macrovision
compliance).
Reserved.
Reset
Value
0x00
0x02
0
Disabled.
Enabled.
0
0
1
0
1
SD PrPb Scale.
0
1
SD Y Scale.
0
1
SD Hue Adjust.
0
1
SD Brightness.
0
1
SD Luma SSAF Gain.
0
1
SD Input Standard Auto Detect.
Reserved.
SD RGB Input Enable.
Register Setting
Disabled.
VSYNC = 2.5 lines (PAL),
VSYNC = 3 lines (NTSC).
0
Reserved.
SD Horizontal/Vertical Counter
Mode. 1
SD RGB Color Swap.
0
0
1
0
1
0
0
1
Rev. 0 | Page 38 of 88
Update field/line counter.
Field/line counter free running.
Normal.
Color reversal enabled.
Disabled.
Enabled.
Disabled.
Enabled.
Disabled.
Enabled.
Disabled.
Enabled.
Disabled.
Enabled.
Disabled.
Enabled.
0 must be written to this bit.
SD YCrCb input.
SD RGB input.
0x00
ADV7342/ADV7343
SR7 to
SR0
0x88
Register
SD Mode
Register 7
Bit Description
Reserved.
SD Noninterlaced Mode.
7
6
Bit Number
5 4 3 2
0
1
SD Input Format.
0
0
1
1
SD Digital Noise Reduction.
SD Mode
Register 8
0
1
0
1
SD Undershoot Limiter.
0
0
1
1
Reserved.
SD Black Burst Output on DAC
Luma.
0
0
1
SD Chroma Delay.
Reserved.
1
0
1
0
1
0
1
SD Gamma Correction Enable.
0x89
0
0
0
1
SD Double Buffering.
SD Gamma Correction Curve Select.
1
0
0
1
1
0
0
1
0
1
0
0
1
0
1
Register Setting
Disabled.
Enabled.
Disabled.
Enabled.
8-bit input.
16-bit input.
Reserved.
Reserved.
Disabled.
Enabled.
Disabled.
Enabled.
Gamma Correction Curve A.
Gamma Correction Curve B.
Disabled.
−11 IRE.
−6 IRE.
−1.5 IRE.
0 must be written to this bit.
Disabled.
Enabled.
Disabled.
4 clock cycles.
8 clock cycles.
Reserved.
0 must be written to these bits.
When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
Rev. 0 | Page 39 of 88
Reset
Value
0x00
0x00
ADV7342/ADV7343
Table 27. Register 0x8A to Register 0x98
SR7 to
SR0
0x8A
Register
SD Timing Register 0
Bit Description
SD Slave/Master Mode.
7
6
5
Bit Number
4
3
2
1
0
0
1
1
0
1
0
1
SD Timing Mode.
Reserved.
SD Luma Delay.
0
1
0
1
0
1
SD Timing Reset.
SD Timing Register 1
(Note: Applicable in
master modes only,
that is, Subaddress
0x8A, Bit 0 = 1)
x
SD HSYNC Width.
SD HSYNC to VSYNC Delay.
SD HSYNC to VSYNC Rising
Edge Delay (Mode 1 Only).
SD VSYNC Width (Mode 2 Only).
x
x
0
0
1
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
0x8C
SD FSC Register 0 1
Subcarrier Frequency Bits[7:0].
0
0
1
1
x
0x8D
SD FSC Register 11
Subcarrier Frequency Bits[15:8].
x
x
x
x
x
x
x
x
0x8E
SD FSC Register 21
x
x
x
x
x
x
x
x
0x8F
SD FSC Register 31
x
x
x
x
x
x
x
x
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
SD FSC Phase
SD Closed Captioning
SD Closed Captioning
SD Closed Captioning
SD Closed Captioning
SD Pedestal Register 0
SD Pedestal Register 1
SD Pedestal Register 2
SD Pedestal Register 3
Subcarrier Frequency
Bits[23:16].
Subcarrier Frequency
Bits[31:24].
Subcarrier Phase Bits[9:2].
Extended Data on Even Fields.
Extended Data on Even Fields.
Data on Odd Fields.
Data on Odd Fields.
Pedestal on Odd Fields.
Pedestal on Odd Fields.
Pedestal on Even Fields.
Pedestal on Even Fields.
x
x
x
x
x
17
25
17
25
x
x
x
x
x
16
24
16
24
x
x
x
x
x
15
23
15
23
x
x
x
x
x
14
22
14
22
x
x
x
x
x
13
21
13
21
x
x
x
x
x
12
20
12
20
x
x
x
x
x
11
19
11
19
x
x
x
x
x
10
18
10
18
SD HSYNC to Pixel Data Adjust.
1
Register Setting
Slave mode.
Master mode.
Mode 0.
Mode 1.
Mode 2.
Mode 3.
Reset
Value
0x08
1
0
0
1
1
SD Minimum Luma Value.
0x8B
0
0
1
0
1
0
1
x
x
x
x
x
x
x
SD subcarrier frequency registers default to NTSC subcarrier frequency values.
Rev. 0 | Page 40 of 88
No delay.
2 clock cycles.
4 clock cycles.
6 clock cycles.
−40 IRE.
−7.5 IRE.
A low-high-low transition
resets the internal SD
timing counters.
ta = 1 clock cycle.
ta = 4 clock cycles.
ta = 16 clock cycles.
ta = 128 clock cycles.
tb = 0 clock cycles.
tb = 4 clock cycles.
tb = 8 clock cycles.
tb = 18 clock cycles.
tc = tb.
tc = tb + 32 μs.
1 clock cycle.
4 clock cycles.
16 clock cycles.
128 clock cycles.
0 clock cycles.
1 clock cycle.
2 clock cycles.
3 clock cycles.
Subcarrier Frequency
Bits[7:0].
Subcarrier Frequency
Bits[15:8].
Subcarrier Frequency
Bits[23:16].
Subcarrier Frequency
Bits[31:24].
Subcarrier Phase Bits[9:2].
Extended Data Bits[7:0].
Extended Data Bits[15:8].
Data Bits[7:0].
Data Bits[15:8].
Setting any of these bits
to 1 disables pedestal
on the line number
indicated by the bit
settings.
0x00
0x1F
0x7C
0xF0
0x21
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
ADV7342/ADV7343
Table 28. Register 0x99 to Register 0xA5
SR7 to
SR0
0x99
Register
SD CGMS/WSS 0
Bit Description
SD CGMS Data.
SD CGMS CRC.
7
6
SD CGMS on Odd Fields.
0x9A
SD CGMS/WSS 1
SD CGMS/WSS Data.
0x9B
SD CGMS/WSS 2
SD CGMS Data.
SD CGMS/WSS Data.
0x9C
SD Scale LSB
Register
0x9D
0x9E
0x9F
0xA0
0xA1
SD Y Scale Register
SD Cb Scale
Register
SD Cr Scale Register
SD Hue Register
SD Brightness/WSS
0xA2
SD Luma SSAF
0xA3
SD DNR 0
LSBs for SD Y Scale Value.
LSBs for SD Cb Scale Value.
LSBs for SD Cr Scale Value.
LSBs for SD FSC Phase.
SD Y Scale Value.
SD Cb Scale Value.
SD Cr Scale Value.
SD Hue Adjust Value.
SD Brightness Value.
SD Blank WSS Data.
Bit Number
4
3
2
x
x
0
1
1
x
0
x
0
1
SD CGMS on Even Fields.
SD WSS.
5
0
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
…
0
…
1
0
…
1
…
1
0
…
1
…
0
0
…
0
…
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
SD Luma SSAF Gain/Attenuation.
Note: Only applicable if
Register 0x87, Bit 4 = 1.
Reserved.
Coring Gain Border.
Note: In DNR mode, the values
in brackets apply.
0
Coring Gain Data.
Note: In DNR mode, the values
in brackets apply.
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
Register Setting
CGMS Data Bits[C19:C16]
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
CGMS Data Bits[C13:C8] or
WSS Data Bits[W13:W8]
CGMS Data Bits[C15:C14]
CGMS Data Bits[C7:C0] or
WSS Data Bits[W7:W0]
SD Y Scale Bits[1:0]
SD Cb Scale Bits[1:0]
SD Cr Scale Bits[1:0].
Subcarrier Phase Bits[1:0]
SD Y Scale Bits[9:2]
SD Cb Scale Bits[9:2]
Reset
Value
0x00
0x00
0x00
0x00
0x00
0x00
SD Cr Scale Bits[9:2]
SD Hue Adjust Bits[7:0]
SD Brightness Bits[6:0]
Disabled
Enabled
−4 dB
…
0 dB
…
+4 dB
0x00
0x00
0x00
No gain
+1/16 [−1/8]
+2/16 [−2/8]
+3/16 [−3/8]
+4/16 [−4/8]
+5/16 [−5/8]
+6/16 [−6/8]
+7/16 [−7/8]
+8/16 [−1]
No gain
+1/16 [−1/8]
+2/16 [−2/8]
+3/16 [−3/8]
+4/16 [−4/8]
+5/16 [−5/8]
+6/16 [−6/8]
+7/16 [−7/8]
+8/16 [−1]
0x00
0x00
0
0
1
0
1
0
1
0
1
0
Rev. 0 | Page 41 of 88
ADV7342/ADV7343
SR7 to
SR0
0xA4
Register
SD DNR 1
Bit Description
DNR Threshold.
7
Border Area.
Block Size Control.
0xA5
SD DNR 2
6
5
0
0
…
1
1
Bit Number
4
3
0
0
0
0
… …
1
1
1
1
1
0
0
…
1
1
0
0
1
…
0
1
0
0
0
1
0
1
1
0
1
0
1
0
0
1
0
1
DNR Input Select.
DNR Mode.
DNR Block Offset.
2
0
0
…
1
1
0
1
0
0
…
1
1
0
0
…
1
1
0
0
…
1
1
0
1
…
0
1
Register Setting
0
1
…
62
63
2 pixels
4 pixels
8 pixels
16 pixels
Filter A
Filter B
Filter C
Filter D
DNR mode
DNR sharpness mode
0 pixel offset
1 pixel offset
…
14 pixel offset
15 pixel offset
Reset
Value
0x00
0x00
Table 29. Register 0xA6 to Register 0xBB
SR7 to
SR0
0xA6
0xA7
0xA8
0xA9
0xAA
0xAB
0xAC
0xAD
0xAE
0xAF
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
0xB6
0xB7
0xB8
0xB9
0xBA
0xBB
Register
SD Gamma A 0
SD Gamma A 1
SD Gamma A 2
SD Gamma A 3
SD Gamma A 4
SD Gamma A 5
SD Gamma A 6
SD Gamma A 7
SD Gamma A 8
SD Gamma A 9
SD Gamma B 0
SD Gamma B 1
SD Gamma B 2
SD Gamma B 3
SD Gamma B 4
SD Gamma B 5
SD Gamma B 6
SD Gamma B 7
SD Gamma B 8
SD Gamma B 9
SD Brightness Detect
Field Count Register
Bit Description
SD Gamma Curve A (Point 24).
SD Gamma Curve A (Point 32).
SD Gamma Curve A (Point 48).
SD Gamma Curve A (Point 64).
SD Gamma Curve A (Point 80).
SD Gamma Curve A (Point 96).
SD Gamma Curve A (Point 128).
SD Gamma Curve A (Point 160).
SD Gamma Curve A (Point 192).
SD Gamma Curve A (Point 224).
SD Gamma Curve B (Point 24).
SD Gamma Curve B (Point 32).
SD Gamma Curve B (Point 48).
SD Gamma Curve B (Point 64).
SD Gamma Curve B (Point 80).
SD Gamma Curve B (Point 96).
SD Gamma Curve B (Point 128).
SD Gamma Curve B (Point 160).
SD Gamma Curve B (Point 192).
SD Gamma Curve B (Point 224).
SD Brightness Value.
Field Count.
Reserved.
Revision Code.
7
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
Rev. 0 | Page 42 of 88
Bit Number
4
3
2
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
5
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Register
Setting
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
Read only.
Read only.
Reserved.
Read only.
Reset
Value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xXX
0x0X
ADV7342/ADV7343
Table 30. Register 0xE0 to Register 0xF1
SR7 to
SR0
0xE0
0xE1
0xE2
0xE3
0xE4
0xE5
0xE6
0xE7
0xE8
0xE9
0xEA
0xEB
0xEC
0xED
0xEE
0xEF
0xF0
0xF1
1
Register 1
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Bit Description
MV Control Bits.
MV Control Bits.
MV Control Bits.
MV Control Bits.
MV Control Bits.
MV Control Bits.
MV Control Bits.
MV Control Bits.
MV Control Bits.
MV Control Bits.
MV Control Bits.
MV Control Bits.
MV Control Bits.
MV Control Bits.
MV Control Bits.
MV Control Bits.
MV Control Bits.
MV Control Bit.
7
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
5
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
Bit Number
4
3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
Macrovision registers are available on the ADV7342 only.
Rev. 0 | Page 43 of 88
2
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Register Setting
Bits[7:1] must be 0.
Reset
Value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
ADV7342/ADV7343
INPUT CONFIGURATION
Subaddress 0x01, Bit 7), with S0/Y0 being the LSB. The ITU-R
BT.601/656 input standard is supported.
The ADV7342/ADV7343 support a number of different input
modes. The desired input mode is selected using Subaddress
0x01, Bits[6:4]. The ADV7342/ADV7343 default to standard
definition only (SD only) upon power-up. Table 31 provides an
overview of all possible input configurations. Each input mode
is described in detail in the following sections.
16-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0; Subaddress 0x88, Bit 3 = 1
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on
Pin S7 to Pin S0 (or Pin Y7 to Pin Y0, depending on Subaddress
0x01, Bit 7), with S0/Y0 being the LSB.
STANDARD DEFINITION ONLY
Subaddress 0x01, Bits[6:4] = 000
The CrCb pixel data is input on Pin Y7 to Pin Y0 (or Pin C7 to
Pin C0, depending on Subaddress 0x01, Bit 7), with Y0/C0
being the LSB.
Standard definition (SD) YCrCb data can be input in 4:2:2 format.
Standard definition (SD) RGB data can be input in 4:4:4 format.
24-Bit 4:4:4 RGB Mode
Subaddress 0x87, Bit 7 = 1
A 27 MHz clock signal must be provided on the CLKIN_A pin.
Input synchronization signals are provided on the S_HSYNC
and S_VSYNC pins.
In 24-bit 4:4:4 RGB input mode, the red pixel data is input on
Pin S7 to Pin S0, the green pixel data is input on Pin Y7 to
Pin Y0, and the blue pixel data is input on Pin C7 to Pin C0.
S0, Y0, and C0 are the respective bus LSBs.
8-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0; Subaddress 0x88, Bit 3 = 0
In 8-bit 4:2:2 YCrCb input mode, the interleaved pixel data is
input on Pin S7 to Pin S0 (or Pin Y7 to Pin Y0, depending on
Table 31. Input Configuration
S
Input Mode 1
000 SD Only
8-Bit YCrCb 2
16-Bit YCrCb2, 3
7
6
5
4
3
YCrCb
Y
8-Bit YCrCb2
16-Bit YCrCb2, 3
001
010
011
100
111
24-Bit RGB3
ED/HD-SDR Only 4, 5
16-Bit YCrCb
24-Bit YCrCb
24-Bit RGB3
ED/HD-DDR Only (8-Bit)5
SD and ED/HD-SDR (24-Bit)5
SD and ED/HD-DDR (16-Bit)5
ED Only (54 MHz) (8-Bit)5
R
Cr
R
YCrCb (SD)
YCrCb (SD)
2
1
0
7
Y
6 5 4 3 2 1 0
Y/C/S Bus Swap (0x01[7]) = 0
C
7
6
CrCb
Y/C/S Bus Swap (0x01[7]) = 1
YCrCb
Y
SD RGB Input Enable (0x87[7]) = 1
G
ED/HD RGB Input Enable (0x35[1]) = 0
Y
Y
ED/HD RGB Input Enable (0x35[1]) = 1
G
YCrCb
Y (ED/HD)
YCrCb (ED/HD)
YCrCb
1
The input mode is determined by Subaddress 0x01, Bits[6:4].
In SD only (YCrCb) mode, the format of the input data is determined by Subaddress 0x88, Bits[4:3]. See Table 26 for more information.
3
External synchronization signals must be used in this input mode. Embedded EAV/SAV timing codes are not supported.
4
In ED/HD-SDR only (YCrCb) mode, the format of the input data is determined by Subaddress 0x33, Bit 6. See Table 19 for more information.
5
ED = enhanced definition = 525p and 625p.
2
Rev. 0 | Page 44 of 88
5
4
3
2
CrCb
B
CrCb
Cb
B
CrCb (ED/HD)
1
0
ADV7342/ADV7343
24-Bit 4:4:4 YCrCb Mode
Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 0
ADV7342/
ADV7343
S_VSYNC,
S_HSYNC
27MHz
In 24-bit 4:4:4 YCrCb input mode, the Y pixel data is input on
Pin Y7 to Pin Y0, with Y0 being the LSB.
CLKIN_A
The Cr pixel data is input on Pin S7 to Pin S0, with S0 being
the LSB.
10
YCrCb
S[7:0] OR Y[7:0]*
The Cb pixel data is input on Pin C7 to Pin C0, with C0 being
the LSB.
06399-051
*SELECTED BY SUBADDRESS 0x01, BIT 7.
Figure 51. SD Only Example Application
ENHANCED DEFINITION/HIGH DEFINITION ONLY
Subaddress 0x01, Bits[6:4] = 001 or 010
Enhanced definition (ED) or high definition (HD) YCrCb data
can be input in either 4:2:2 or 4:4:4 formats. If desired, dual data
rate (DDR) pixel data inputs can be employed (4:2:2 format only).
24-Bit 4:4:4 RGB Mode
Subaddress 0x35, Bit 1 = 1
In 24-bit 4:4:4 RGB input mode, the red pixel data is input on
Pin S7 to Pin S0, the green pixel data is input on Pin Y7 to Pin
Y0, and the blue pixel data is input on Pin C7 to Pin C0. S0, Y0,
and C0 are the respective bus LSBs.
Enhanced definition (ED) or high definition (HD) RGB data
can be input in 4:4:4 format (single data rate only).
MPEG2
DECODER
The clock signal must be provided on the CLKIN_A pin. Input
synchronization signals are provided on the P_HSYNC,
P_VSYNC, and P_BLANK pins.
ADV7342/
ADV7343
CLKIN_A
YCrCb
Cb 10
Cr 10
INTERLACED TO
PROGRESSIVE
16-Bit 4:2:2 YCrCb Mode (SDR)
Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 1
Y 10
3
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is
input on Pin Y7 to Pin Y0, with Y0 being the LSB.
C[7:0]
S[7:0]
Y[7:0]
P_VSYNC,
P_HSYNC,
P_BLANK
06399-054
2
MPEG2
DECODER
Figure 54. ED/HD Only Example Application
The CrCb pixel data is input on Pin C7 to Pin C0, with C0
being the LSB.
SIMULTANEOUS STANDARD DEFINITION AND
ENHANCED DEFINITION/HIGH DEFINITION
8-Bit 4:2:2 YCrCb Mode (DDR)
Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 1
Subaddress 0x01, Bits[6:4] = 011 or 100
In 8-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is input
on Pin Y7 to Pin Y0 upon either the rising or falling edge of
CLKIN_A. Y0 is the LSB.
The CrCb pixel data is also input on Pin Y7 to Pin Y0
upon the opposite edge of CLKIN_A. Y0 is the LSB.
Whether the Y data is clocked in upon the rising or falling edge
of CLKIN_A is determined by Subaddress 0x01, Bits[2:1] (see
Figure 52 and Figure 53).
CLKIN_A
3FF
00
00
XY
Cb0
Y0
Cr0
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.
The SD 8-bit 4:2:2 YCrCb pixel data is input on Pin S7 to Pin
S0, with S0 being the LSB.
The ED/HD 16-bit 4:2:2 CrCb pixel data is input on Pin C7 to
Pin C0, with C0 being the LSB.
SD 8-Bit 4:2:2 YCrCb and ED/HD-DDR 8-Bit 4:2:2 YCrCb
Figure 52. ED/HD-DDR Input Sequence (EAV/SAV)—Option A
The SD 8-bit 4:2:2 YCrCb pixel data is input on Pin S7 to Pin
S0, with S0 being the LSB.
CLKIN_A
3FF
00
00
XY
Y0
Cb0
Y1
Cr0
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO11 IN THIS CASE.
Figure 53. ED/HD-DDR Input Sequence (EAV/SAV)—Option B
06399-053
Y[7:0]
SD 8-Bit 4:2:2 YCrCb and ED/HD-SDR 16-Bit 4:2:2 YCrCb
The ED/HD 16-bit 4:2:2 Y pixel data is input on Pin Y7 to Pin
Y0, with Y0 being the LSB.
Y1
06399-052
Y[7:0]
The ADV7342/ADV7343 are able to simultaneously process SD
4:2:2 YCrCb data and ED/HD 4:2:2 YCrCb data. The 27 MHz
SD clock signal must be provided on the CLKIN_A pin. The
ED/HD clock signal must be provided on the CLKIN_B pin. SD
input synchronization signals are provided on the S_HSYNC
and S_VSYNC pins. ED/HD input synchronization signals are
provided on the P_HSYNC, P_VSYNC and P_BLANK pins.
The ED/HD-DDR 8-bit 4:2:2 Y pixel data is input on Pin Y7 to
Pin Y0 upon the rising or falling edge of CLKIN_B. Y0 is the LSB.
The ED/HD-DDR 8-bit 4:2:2 CrCb pixel data is also input on Pin
Y7 to Pin Y0 upon the opposite edge of CLKIN_B. Y0 is the LSB.
Rev. 0 | Page 45 of 88
ADV7342/ADV7343
Whether the ED/HD Y data is clocked in upon the rising
or falling edge of CLKIN_B is determined by Subaddress 0x01,
Bits[2:1] (See the input sequence shown in Figure 52 and
Figure 53).
CLKIN_A
YCrCb 10
HDTV
DECODER
1080i
OR
720p
OR
1035i
CrCb 10
Y
A 54 MHz clock signal must be provided on the CLKIN_A pin.
Input synchronization signals are provided on the P_HSYNC,
P_VSYNC, and P_BLANK pins.
S_VSYNC,
S_HSYNC
10
3
74.25MHz
S[7:0]
The interleaved pixel data is input on Pin Y7 to Pin Y0, with Y0
being the LSB.
ADV7342/
ADV7343
C[7:0]
Y[7:0]
P_VSYNC,
P_HSYNC,
P_BLANK
CLKIN_B
CLKIN_A
Y[7:0]
27MHz
YCrCb 10
HDTV
DECODER
1080i
OR
720p
OR
1035i
CrCb 10
Y
10
3
74.25MHz
YCrCb
S_VSYNC,
S_HSYNC
CLKIN_A
INTERLACED TO
PROGRESSIVE
ADV7342/
ADV7343
C[7:0]
CLKIN_B
XY
54MHz
Cb0
Y0
Cr0
Y1
CLKIN_A
YCrCb 10
S[7:0]
Y[7:0]
P_VSYNC,
P_HSYNC,
P_BLANK
00
MPEG2
DECO DER
3
ADV7342/
ADV7343
Y[7:0]
P_VSYNC,
P_HSYNC,
P_BLANK
Figure 58. ED Only (at 54 MHz) Example Application
06399-056
SDTV
DECODER
00
Figure 57. ED Only (at 54 MHz) Input Sequence (EAV/SAV)
Figure 55. Simultaneous SD and ED Example Application
2
3FF
Figure 56. Simultaneous SD and HD Example Application
Rev. 0 | Page 46 of 88
06399-057
27MHz
Enhanced definition (ED) YCrCb data can be input in an
interleaved 4:2:2 format on an 8-bit bus at a rate of 54 MHz.
06399-055
SDTV
DECODER
Subaddress 0x01, Bits[6:4] = 111
06399-058
2
CrCb
ENHANCED DEFINITION ONLY (AT 54 MHz)
ADV7342/ADV7343
OUTPUT CONFIGURATION
The ADV7342/ADV7343 support a number of different output configurations. Table 32 to Table 35 lists all possible output configurations.
Table 32. SD Only Output Configurations
RGB/YPrPb
Output Select 1
(0x02, Bit 5)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
SD DAC
Output 2
(0x82, Bit 2)
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SD DAC
Output 1
(0x82, Bit 1)
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SD Luma/Chroma
Swap (0x84, Bit 7)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC 1
G
G
CVBS
CVBS
CVBS
CVBS
G
G
Y
Y
CVBS
CVBS
CVBS
CVBS
Y
Y
DAC 2
B
B
Luma
Chroma
B
B
Luma
Chroma
Pb
Pb
Luma
Chroma
Pb
Pb
Luma
Chroma
DAC 3
R
R
Chroma
Luma
R
R
Chroma
Luma
Pr
Pr
Chroma
Luma
Pr
Pr
Chroma
Luma
DAC 4
CVBS
CVBS
G
G
G
G
CVBS
CVBS
CVBS
CVBS
Y
Y
Y
Y
CVBS
CVBS
DAC 5
Luma
Chroma
B
B
Luma
Chroma
B
B
Luma
Chroma
Pb
Pb
Luma
Chroma
Pb
Pb
DAC 6
Chroma
Luma
R
R
Chroma
Luma
R
R
Chroma
Luma
Pr
Pr
Chroma
Luma
Pr
Pr
If SD RGB output is selected, a color reversal is possible using Subaddress 0x86, Bit 7.
Table 33. ED/HD Only Output Configurations
RGB/YPrPb Output Select (0x02, Bit 5)
0
0
1
1
ED/HD Color DAC Swap (0x35, Bit 3)
0
1
0
1
DAC 1
G
G
Y
Y
DAC 2
B
R
Pb
Pr
DAC 3
R
B
Pr
Pb
DAC 4
N/A
N/A
N/A
N/A
DAC 5
N/A
N/A
N/A
N/A
DAC 6
N/A
N/A
N/A
N/A
Table 34. Simultaneous SD and ED/HD Output Configurations
RGB/YPrPb Output
Select (0x02, Bit 5)
0
0
0
0
1
1
1
1
ED/HD Color
DAC Swap
(0x35, Bit 3)
0
0
1
1
0
0
1
1
SD Luma/Chroma
Swap (0x84, Bit 7)
0
1
0
1
0
1
0
1
DAC 1
(ED/HD)
G
G
G
G
Y
Y
Y
Y
DAC 2
(ED/HD)
B
B
R
R
Pb
Pb
Pr
Pr
DAC 3
(ED/HD)
R
R
B
B
Pr
Pr
Pb
Pb
DAC 4
(SD)
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
DAC 5
(SD)
Luma
Chroma
Luma
Chroma
Luma
Chroma
Luma
Chroma
DAC 6
(SD)
Chroma
Luma
Chroma
Luma
Chroma
Luma
Chroma
Luma
Table 35. ED Only (at 54 MHz) Output Configurations
RGB/YPrPb Output Select (0x02, Bit 5)
0
0
1
1
ED/HD Color DAC Swap (0x35, Bit 3)
0
1
0
1
Rev. 0 | Page 47 of 88
DAC 1
G
G
Y
Y
DAC 2
B
R
Pb
Pr
DAC 3
R
B
Pr
Pb
DAC 4
N/A
N/A
N/A
N/A
DAC 5
N/A
N/A
N/A
N/A
DAC 6
N/A
N/A
N/A
N/A
ADV7342/ADV7343
FEATURES
OUTPUT OVERSAMPLING
The ADV7342/ADV7343 include two on-chip phase locked
loops (PLLs) that allow for oversampling of SD, ED, and HD
video data. Table 36 shows the various oversampling rates
supported in the ADV7342/ADV7343.
SD Only, ED Only, and HD Only Modes
PLL 1 is used in SD only, ED only, and HD only modes. PLL 2 is
unused in these modes. PLL 1 is disabled by default and can be
enabled using Subaddress 0x00, Bit 1 = 0.
SD and ED/HD Simultaneous Modes
Both PLL 1 and PLL 2 are used in simultaneous modes. The use
of two PLLs allows for independent oversampling of SD and
ED/HD video. PLL 1 is used to oversample SD video data, and
PLL 2 is used to oversample ED/HD video data. In simultaneous
modes, PLL 2 is always enabled. PLL 1 is disabled by default and
can be enabled using Subaddress 0x00, Bit 1 = 0.
ED/HD nonstandard timing mode can be enabled by setting
Subaddress 0x30, Bits[7:3] to 00001.
A clock signal must be provided on the CLKIN_A pin.
P_HSYNC and P_VSYNC must be toggled by the user to
generate the appropriate horizontal and vertical synchronization
pulses on the analog output from the encoder. Figure 59 illustrates
the various output levels that can be generated .Table 37 lists the
transitions required to generate these output levels.
Embedded EAV/SAV timing codes are not supported in
ED/HD nonstandard timing mode.
The user must ensure that appropriate pixel data is applied to
the encoder where the blanking level is expected at the output.
Macrovision (ADV7342 only) and output oversampling are not
available in ED/HD nonstandard timing mode.
b
ANALOG
OUTPUT
ACTIVE VIDEO
a
ED/HD NONSTANDARD TIMING MODE
b
Subaddress 0x30, Bits[7:3] = 00001
b
BLANKING LEVEL
c
a = TRI-LEVEL SYNCHRONIZATION PULSE LEVEL.
b = BLANKING LEVEL/ACTIVE VIDEO LEVEL.
c = SYNCHRONIZATION PULSE LEVEL.
06399-141
For any ED/HD input data that does not conform to the
standards available in the ED/HD input mode table
(Subaddress 0x30, Bits[7:3]), the ED/HD nonstandard timing
mode can be used to interface to the ADV7342/ADV7343.
Figure 59. ED/HD Nonstandard Timing Mode Output Levels
Table 36. Output Oversampling Modes and Rates
Input Mode
Subaddress 0x01 [6:4]
000
SD only
000
SD only
001/010
ED only
001/010
ED only
001/010
HD only
001/010
HD only
011/100
SD and ED
011/100
SD and ED
011/100
SD and HD
011/100
SD and HD
111
ED only (at 54 MHz)
111
ED only (at 54 MHz)
PLL and Oversampling Control
Subaddress 0x00, Bit 1
1
0
1
0
1
0
1
0
1
0
1
0
Oversampling Mode and Rate
SD (2×)
SD (16×)
ED (1×)
ED (8×)
HD (1×)
HD (4×)
SD (2×) and ED (8×)
SD (16×) and ED (8×)
SD (2×) and HD (4×)
SD (16×) and HD (4×)
ED only (at 54 MHz) (1×)
ED only (at 54 MHz) (8×)
Table 37. ED/HD Nonstandard Timing Mode Synchronization Signal Generation
Output Level Transition 1
P_HSYNC
P_VSYNC
b→c
c→a
a→b
c→b
1→0
0
0→1
0→1
1 → 0 or 0 2
0→1
1
0
1
2
a = tri-level synchronization pulse level; b = blanking level/active video level; c = synchronization pulse level.
If P_VSYNC = 1, it should transition to 0. If P_VSYNC = 0, it should remain at 0. If tri-level synchronization pulse generation is not required, P_VSYNC should always be 0.
Rev. 0 | Page 48 of 88
ADV7342/ADV7343
ED/HD TIMING RESET
Subcarrier Phase Reset (SCR) Mode
Subaddress 0x34, Bit 0
In this mode (Subaddress 0x84, Bits[2:1] = 01), a low-to-high
transition on the SFL/MISO pin (Pin 48) resets the subcarrier
phase to 0 on the field following the subcarrier phase reset. This
reset signal must be held high for a minimum of one clock cycle.
An ED/HD timing reset is achieved by toggling the ED/HD
timing reset control bit (Subaddress 0x34, Bit 0) from 0 to 1.
In this state, the horizontal and vertical counters remain reset.
When this bit is set back to 0, the internal counters resume
counting. This timing reset applies to the ED/HD timing
counters only.
Because the field counter is not reset, it is recommended that
the reset signal be applied in Field 7 (PAL) or Field 3 (NTSC).
The reset of the phase then occurs on the next field, that is,
Field 1, lined up correctly with the internal counters. The field
count register at Subaddress 0xBB can be used to identify the
number of the active field.
SD SUBCARRIER FREQUENCY LOCK, SUBCARRIER
PHASE RESET, AND TIMING RESET
Subaddress 0x84, Bits[2:1]
Subcarrier Frequency Lock (SFL) Mode
Together with the SFL/MISO pin and SD Mode Register 4
(Subaddress 0x84, Bits[2:1]), the ADV7342/ADV7343 can be used
in timing reset mode, subcarrier phase reset mode, or SFL mode.
In this mode (Subaddress 0x84, Bits[2:1] = 11), the ADV7342
/ADV7343 can be used to lock to an external video source. The
SFL mode allows the ADV7342/ADV7343 to automatically alter
the subcarrier frequency to compensate for line length
variations. When the part is connected to a device such as an
ADV7403 video decoder (see Figure 62) that outputs a digital
data stream in the SFL format, the part automatically changes to
the compensated subcarrier frequency on a line-by-line basis.
This digital data stream is 67 bits wide, and the subcarrier is
contained in Bit 0 to Bit 21. Each bit is two clock cycles long.
Timing Reset (TR) Mode
In this mode (Subaddress 0x84, Bits[2:1] = 10), a timing reset is
achieved in a low-to-high transition on the SFL/MISO pin (Pin 48).
In this state, the horizontal and vertical counters remain reset.
Upon releasing this pin (set to low), the internal counters resume
counting, starting with Field 1, and the subcarrier phase is reset.
The minimum time the pin must be held high is one clock
cycle; otherwise, this reset signal might not be recognized. This
timing reset applies to the SD timing counters only.
DISPLAY
307
START OF FIELD 4 OR 8
310
FSC PHASE = FIELD 4 OR 8
313
320
NO TIMING RESET APPLIED
DISPLAY
START OF FIELD 1
1
2
3
4
5
6
7
21
TIMING RESET PULSE
TIMING RESET APPLIED
06399-061
307
FSC PHASE = FIELD 1
Figure 60. SD Timing Reset Timing Diagram (Subaddress 0x84, Bits [2:1] = 10)
DISPLAY
307
310
START OF FIELD 4 OR 8
313
FSC PHASE = FIELD 4 OR 8
320
NO FSC RESET APPLIED
307
310
START OF FIELD 4 OR 8
313
FSC PHASE = FIELD 1
320
FSC RESET PULSE
FSC RESET APPLIED
Figure 61. SD Subcarrier Phase Reset Timing Diagram (Subaddress 0x84, Bits [2:1] = 01)
Rev. 0 | Page 49 of 88
06399-062
DISPLAY
ADV7342/ADV7343
ADV7342/ADV7343
CLKIN_A
LCC1
COMPOSITE
VIDEO1
DAC 1
DAC 2
SFL
SFL/MISO
DAC 5
Y[7:0]/S[7:0] 5
DECODER
14 BITS
H/L TRANSITION
SUBCARRIER
COUNT START
LOW PHASE
128
13
0
DAC 3
DAC 4
ADV7403 P[19:12]
VIDEO
DAC 6
4 BITS
RESERVED
21
SEQUENCE
BIT3
FSC PLL INCREMENT2
0
RESET BIT4
RESERVED
RTC
TIME SLOT 01
6768
19
14
VALID INVALID
SAMPLE SAMPLE
8/LINE
LOCKED
CLOCK
5 BITS
RESERVED
1FOR EXAMPLE, VCR OR CABLE.
2F
SC PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7342/ADV7343 FSC DDS REGISTER IS
FSC PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS.
3SEQUENCE BIT
06399-063
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
4RESET ADV7342/ADV7343 DDS.
5SELECTED BY SUBADDRESS 0x01, BIT 7.
Figure 62. SD Subcarrier Frequency Lock Timing and Connections Diagram (Subaddress 0x84, Bits [2:1] = 11)
SD VCR FF/RW SYNC
Subaddress 0x82, Bit 5
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW sync control bit can be used for nonstandard input video, that is, in fast forward or rewind modes.
For the SMPTE 293M (525p) standard, VBI data can be
inserted on Line 13 to Line 42 of each frame, or on Line 6 to
Line 43 for the ITU-R BT.1358 (625p) standard.
VBI data can be present on Line 10 to Line 20 for NTSC and on
Line 7 to Line 22 for PAL.
In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct
number of lines/fields is reached. In rewind mode, this sync
signal usually occurs after the total number of lines/fields is
reached. Conventionally, this means that the output video has
corrupted field signals because one signal is generated by the
incoming video and another is generated when the internal
line/field counters reach the end of a field.
In SD Timing Mode 0 (slave option), if VBI is enabled, the
blanking bit in the EAV/SAV code is overwritten. It is possible
to use VBI in this timing mode as well.
When the VCR FF/RW sync control is enabled (Subaddress 0x82,
Bit 5), the line/field counters are updated according to the
incoming VSYNC signal and when the analog output matches
the incoming VSYNC signal.
Four 8-bit registers are used to set up the subcarrier frequency.
The value of these registers is calculated using:
If CGMS is enabled and VBI is disabled, the CGMS data is
nevertheless available at the output.
SD SUBCARRIER FREQUENCY REGISTERS
Subaddress 0x8C to Subaddress 0x8F
Subcarrier Frequency Register =
Number of subcarrier periods in one video line
Number of 27 MHz clk cycles in one video line
This control is available in all slave-timing modes except
Slave Mode 0.
× 2 32
where the sum is rounded to the nearest integer.
VERTICAL BLANKING INTERVAL
For example, in NTSC mode:
Subaddress 0x31, Bit 4; Subaddress 0x83, Bit 4
The ADV7342/ADV7343 are able to accept input data that
contains VBI data (such as CGMS, WSS, and VITS) in SD, ED,
and HD modes.
If VBI is disabled (Subaddress 0x31, Bit 4 for ED/HD;
Subaddress 0x83, Bit 4 for SD), VBI data is not present at the
output and the entire VBI is blanked. These control bits are
valid in all master and slave timing modes.
227.5 ⎞ 32
Subcarrier Register Value = ⎛⎜
⎟ × 2 = 569408543
⎝ 1716 ⎠
where:
Subcarrier Register Value = 569408543d = 0×21F07C1F
SD FSC Register 0: 0x1F
SD FSC Register 1: 0x7C
SD FSC Register 2: 0xF0
SD FSC Register 3: 0x21
Rev. 0 | Page 50 of 88
ADV7342/ADV7343
Programming the FSC
The subcarrier frequency register value is divided into four FSC
registers as shown in the previous example. The four subcarrier
frequency registers must be updated sequentially, starting with
Subcarrier Frequency Register 0 and ending with Subcarrier
Frequency Register 3. The subcarrier frequency updates only
after the last subcarrier frequency register byte has been
received by the ADV7342/ADV7343.
Typical FSC Values
Table 38 outlines the values that should be written to the
subcarrier frequency registers for NTSC and PAL B/D/G/H/I.
Table 38. Typical FSC Values
Description
FSC0
FSC1
FSC2
FSC3
NTSC
0x1F
0x7C
0xF0
0x21
PAL B/D/G/H/I
0xCB
0x8A
0x09
0x2A
All input configurations, output configurations and features
available in NTSC and PAL modes are available in SD noninterlaced mode.
For 240p/59.94 Hz input, the ADV7342/ADV7343 should be
configured for NTSC operation and Subaddress 0x88, Bit 1
should be set to 1.
For 288p/50 Hz input, the ADV7342/ADV7343 should be
configured for PAL operation and Subaddress 0x88, Bit 1
should be set to 1.
SD SQUARE PIXEL MODE
Subaddress 0x82, Bit 4
The ADV7342/ADV7343 can be used to operate in square pixel
mode (Subaddress 0x82, Bit 4). For NTSC operation, an input
clock of 24.5454 MHz is required. Alternatively, for PAL
operation, an input clock of 29.5 MHz is required.
SD NONINTERLACED MODE
Subaddress 0x88, Bit 1
The ADV7342/ADV7343 support a SD noninterlaced mode.
Using this mode, progressive inputs at twice the frame rate of
NTSC and PAL (240p/59.94 Hz and 288p/50 Hz, respectively)
can be input into the ADV7342/ADV7343. The SD noninterlaced
mode can be enabled using Subaddress 0x88, Bit 1.
The internal timing logic adjusts accordingly for square pixel
mode operation. In square pixel mode, the timing diagrams
shown in Figure 63 and Figure 64 apply.
ANALOG
VIDEO
EAV CODE
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
PAL SYSTEM
(625 LINES/50Hz)
Y
C
F 0 0 X 8 1 8 1
Y
r
F 0 0 Y 0 0 0 0
4 CLOCK
4 CLOCK
SAV CODE
0 F F A A A
0 F F B B B
C
C
8 1 8 1 F 0 0 X C Y C Y C
Y r Y b
b
0 0 0 0 F 0 0 Y b
r
ANCILLARY DATA
(HANC)
272 CLOCK
4 CLOCK
1280 CLOCK
4 CLOCK
344 CLOCK
1536 CLOCK
06399-064
INPUT PIXELS
START OF ACTIVE
VIDEO LINE
END OF ACTIVE
VIDEO LINE
Figure 63. Square Pixel Mode EAV/SAV Embedded Timing
HSYNC
FIELD
PIXEL
DATA
Cb
Y
Cr
Y
PAL = 308 CLOCK CYCLES
NTSC = 236 CLOCK CYCLES
Figure 64. Square Pixel Mode Active Pixel Timing
Rev. 0 | Page 51 of 88
06399-065
Subaddress
0x8C
0x8D
0x8E
0x8F
A 27 MHz clock signal must be provided on the CLKIN_A pin.
Embedded EAV/SAV timing codes or external horizontal and
vertical synchronization signals provided on the S_HSYNC and
S_VSYNC pins can be used to synchronize the input pixel data.
ADV7342/ADV7343
EXTENDED (SSAF) PrPb FILTER MODE
FILTERS
0
Table 39 shows an overview of the programmable filters
available on the ADV7342/ADV7343.
–10
Subaddress
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x82
0x33
0x33
0x33
–20
–30
–40
–50
–60
0
1
2
3
4
FREQUENCY (MHz)
5
6
06399-066
Filter
SD Luma LPF NTSC
SD Luma LPF PAL
SD Luma Notch NTSC
SD Luma Notch PAL
SD Luma SSAF
SD Luma CIF
SD Luma QCIF
SD Chroma 0.65 MHz
SD Chroma 1.0 MHz
SD Chroma 1.3 MHz
SD Chroma 2.0 MHz
SD Chroma 3.0 MHz
SD Chroma CIF
SD Chroma QCIF
SD PrPb SSAF
ED/HD Chroma Input
ED/HD Sinc Compensation Filter
ED/HD Chroma SSAF
GAIN (dB)
Table 39. Selectable Filters
Figure 65. PrPb SSAF Filter
If this filter is disabled, one of the chroma filters shown in
Table 40 can be selected and used for the CVBS or luma/
chroma signal.
Table 40. Internal Filter Specifications
SD Internal Filter Response
Subaddress 0x80, Bits[7:2]; Subaddress 0x82, Bit 0
The Y filter supports several different frequency responses,
including two low-pass responses, two notch responses, an
extended (SSAF) response with or without gain boost
attenuation, a CIF response, and a QCIF response. The PrPb
filter supports several different frequency responses, including
six low-pass responses, a CIF response, and a QCIF response, as
shown in Figure 39 and Figure 40.
If SD SSAF gain is enabled (Subaddress 0x87, Bit 4), there are 13
response options in the −4 dB to +4 dB range. The desired response
can be programmed using Subaddress 0xA2. The variation of
frequency responses is shown in Figure 36 to Figure 38.
In addition to the chroma filters listed in Table 39, the ADV7342/
ADV7343 contain an SSAF filter specifically designed for the color
difference component outputs, Pr and Pb. This filter has a cutoff
frequency of ~2.7 MHz and a gain of –40 dB at 3.8 MHz (see
Figure 65). This filter can be controlled with Subaddress 0x82,
Bit 0.
Filter
Luma LPF NTSC
Luma LPF PAL
Luma Notch NTSC
Luma Notch PAL
Luma SSAF
Luma CIF
Luma QCIF
Chroma 0.65 MHz
Chroma 1.0 MHz
Chroma 1.3 MHz
Chroma 2.0 MHz
Chroma 3.0 MHz
Chroma CIF
Chroma QCIF
1
Pass-Band
Ripple (dB)1
0.16
0.1
0.09
0.1
0.04
0.127
Monotonic
Monotonic
Monotonic
0.09
0.048
Monotonic
Monotonic
Monotonic
3 dB Bandwidth (MHz)2
4.24
4.81
2.3/4.9/6.6
3.1/5.6/6.4
6.45
3.02
1.5
0.65
1
1.395
2.2
3.2
0.65
0.5
Pass-band ripple is the maximum fluctuation from the 0 dB response in the
pass band, measured in dB. The pass band is defined to have 0 Hz to fc (Hz)
frequency limits for a low-pass filter, and 0 Hz to f1 (Hz) and f2 (Hz) to infinity
for a notch filter, where fc, f1, and f2 are the −3 dB points.
2
3 dB bandwidth refers to the −3 dB cutoff frequency.
Rev. 0 | Page 52 of 88
ADV7342/ADV7343
Table 41. Sample Color Values for EIA 770.2/EIA 770.3
ED/HD Output Standard Selection
ED/HD Sinc Compensation Filter Response
Subaddress 0x33, Bit 3
The ADV7342/ADV7343 include a filter designed to counter
the effect of sinc roll-off in DAC 1, DAC 2, and DAC 3 while
operating in ED/HD mode. This filter is enabled by default. It
can be disabled using Subaddress 0x33, Bit 3. The benefit of the
filter is illustrated in Figure 66 and Figure 67.
0.5
0.4
0.3
GAIN (dB)
0.2
Cr Value
128 (0x80)
128 (0x80)
240 (0xF0)
34
(0x22)
110 (0x6E)
146 (0x92)
16
(0x10)
222 (0xDE)
Cb Value
128 (0x80)
128 (0x80)
90
(0x5A)
54
(0x36)
240 (0xF0)
16
(0x10)
166 (0xA6)
202 (0xCA)
Subaddress 0x03 to Subaddress 0x09
0
The internal color space conversion (CSC) matrix automatically
performs all color space conversions based on the input mode
programmed in the mode select register (Subaddress 0x01,
Bits[6:4]). Table 42 and Table 43 show the options available in
this matrix.
–0.1
–0.2
–0.3
0
5
10
15
20
FREQUENCY (MHz)
25
30
06399-067
–0.4
Figure 66. ED/HD Sinc Compensation Filter Enabled
0.5
An SD color space conversion from RGB-in to YPrPb-out is
possible. An ED/HD color space conversion from RGB-in to
YPrPb-out is not possible.
Table 42. SD Color Space Conversion Options
0.4
Input
YCrCb
YCrCb
RGB
RGB
0.3
0.2
GAIN (dB)
Y Value
235 (0xEB)
16
(0x10)
81
(0x51)
145 (0x91)
41
(0x29)
210 (0xD2)
170 (0xAA)
106 (0x6A)
COLOR SPACE CONVERSION MATRIX
0.1
–0.5
Sample Color
White
Black
Red
Green
Blue
Yellow
Cyan
Magenta
0.1
0
–0.1
1
Output1
YPrPb
RGB
YPrPb
RGB
YPrPb/RGB Out
(Reg. 0x02, Bit 5)
1
0
1
0
RGB In/YCrCb In
(Reg. 0x87, Bit 7)
0
0
1
1
CVBS/YC outputs are available for all CSC combinations.
–0.2
Table 43. ED/HD Color Space Conversion Options
–0.3
–0.5
0
5
10
15
20
FREQUENCY (MHz)
25
30
06399-068
–0.4
Figure 67. ED/HD Sinc Compensation Filter Disabled
Input
YCrCb
YCrCb
RGB
Output
YPrPb
RGB
RGB
YPrPb/RGB Out
(Reg. 0x02, Bit 5)
1
0
0
RGB In/YCrCb In
(Reg. 0x35, Bit 1)
0
0
1
ED/HD TEST PATTERN COLOR CONTROLS
ED/HD Manual CSC Matrix Adjust Feature
Subaddress 0x36 to Subaddress 0x38
Three 8-bit registers at Subaddress 0x36 to Subaddress 0x38
are used to program the output color of the internal ED/HD
test pattern generator (Subaddress 0x31, Bit 2 = 1), whether it
be the lines of the cross hatch pattern or the uniform field test
pattern. They are not functional as color controls for external
pixel data input.
The values for the luma (Y) and the color difference (Cr and
Cb) signals used to obtain white, black, and saturated primary
and complementary colors conform to the ITU-R BT.601-4
standard.
The ED/HD manual CSC matrix adjust feature provides custom
coefficient manipulation for color space conversions and is used
in ED and HD modes only. The ED/HD manual CSC matrix
adjust feature can be enabled using Subaddress 0x02, Bit 3.
Normally, there is no need to enable this feature because the CSC
matrix automatically performs the color space conversion based
on the input mode chosen (ED or HD) and the input and output
color spaces selected (see Table 43). For this reason, the ED/HD
manual CSC matrix adjust feature is disabled by default.
Table 41 shows sample color values that can be programmed
into the color registers when the output standard selection is set
to EIA 770.2/EIA 770.3 (Subaddress 0x30, Bits[1:0] = 00).
Rev. 0 | Page 53 of 88
ADV7342/ADV7343
If RGB output is selected, the ED/HD CSC matrix scalar uses
the following equations:
input standard color space. The user should consider that the
color component conversion could use different scale values.
For example, SMPTE 293M uses the following conversion:
R = GY × Y + RV × Pr
G = GY × Y − (GU × Pb) − (GV × Pr)
R = Y + 1.402Pr
B = GY × Y + BU × Pb
G = Y – 0.714Pr – 0.344Pb
Note that subtractions are implemented in hardware.
B = Y + 1.773Pb
If YPrPb output is selected, the following equations are used:
Y = GY × Y
Pr = RV × Pr
Programming the CSC Matrix
Pb = BU × Pb
where:
GY = Subaddress 0x05, Bits[7:0] and Subaddress 0x03, Bits[1:0].
GU = Subaddress 0x06, Bits[7:0] and Subaddress 0x04, Bits[7:6].
GV = Subaddress 0x07, Bits[7:0] and Subaddress 0x04, Bits[5:4].
BU = Subaddress 0x08, Bits[7:0] and Subaddress 0x04, Bits[3:2].
RV = Subaddress 0x09, Bits[7:0] and Subaddress 0x04, Bits[1:0].
Upon power-up, the CSC matrix is programmed with the
default values shown in Table 44.
If custom manipulation of the ED/HD CSC matrix coefficients
is required for a YCrCb-to-RGB color space conversion, use the
following procedure:
1.
2.
3.
4.
Enable the ED/HD manual CSC matrix adjust feature
(Subaddress 0x02, Bit 3).
Set the output to RGB (Subaddress 0x02, Bit 5).
Disable sync on PrPb (Subaddress 0x35, Bit 2).
Enable sync on RGB (optional) (Subaddress 0x02, Bit 4).
The GY value controls the green signal output level, the BU
value controls the blue signal output level, and the RV value
controls the red signal output level.
Table 44. ED/HD Manual CSC Matrix Default Values
Subaddress
0x03
0x04
0x05
0x06
0x07
0x08
0x09
The programmable CSC matrix is used for external ED/HD
pixel data and is not functional when internal test patterns are
enabled.
Default
0x03
0xF0
0x4E
0x0E
0x24
0x92
0x7C
SD LUMA AND COLOR CONTROL
Subaddress 0x9C to Subaddress 0x9F
SD Y Scale, SD Cb Scale, and SD Cr Scale are three 10-bit
control registers that scale the SD Y, Cb, and Cr output levels.
When the ED/HD manual CSC matrix adjust feature is enabled,
the default coefficient values in Subaddress 0x03 to
Subaddress 0x09 are correct for the HD color space only. The
color components are converted according to the following
1080i and 720p standards (SMPTE 274M, SMPTE 296M):
Each of these registers represents the value required to scale the
Cb or Cr level from 0.0 to 2.0 times its initial value and the Y
level from 0.0 to 1.5 times its initial level. The value of these 10
bits is calculated using the following equation:
Y, Cb, or Cr Scale Value = Scale Factor × 512
For example, if Scale Factor = 1.3
Y, Cb, or Cr Scale Value = 1.3 × 512 = 665.6
R = Y + 1.575Pr
Y, Cb, or Cr Scale Value = 666 (rounded to the nearest integer)
G = Y − 0.468Pr − 0.187Pb
Y, Cb, or Cr Scale Value = 1010 0110 10b
B = Y + 1.855Pb
The conversion coefficients should be multiplied by 315 before
being written to the ED/HD CSC matrix registers This is
reflected in the default values for GY = 0x13B, GU = 0x03B,
GV = 0x093, BU = 0x248, and RV = 0x1F0.
If the ED/HD manual CSC matrix adjust feature is enabled and
another input standard (such as ED) is used, the scale values for
GY, GU, GV, BU, and RV must be adjusted according to this
Subaddress 0x9C, SD Scale LSB Register = 0x2A
Subaddress 0x9D, SD Y Scale Register = 0xA6
Subaddress 0x9E, SD Cb Scale Register = 0xA6
Subaddress 0x9F, SD Cr Scale Register = 0xA6
Note that this feature affects all interlaced output signals, that is,
CVBS, Y/C, YPrPb, and RGB.
Rev. 0 | Page 54 of 88
ADV7342/ADV7343
SD HUE ADJUST CONTROL
Subaddress 0xA0
When enabled, the SD hue adjust control register (Subaddress
0xA0) is used to adjust the hue on the SD composite and chroma
outputs. This feature can be enabled using Subaddress 0x87, Bit 2.
Subaddress 0xA0 contains the bits required to vary the hue of
the video data, that is, the variance in phase of the subcarrier
during active video with respect to the phase of the subcarrier
during the color burst. The ADV7342/ADV7343 provide a
range of ±22.5° in increments of 0.17578125°. For normal
operation (zero adjustment), this register is set to 0x80. Values
0xFF and 0x00 represent the upper and lower limits, respectively,
of the attainable adjustment in NTSC mode. Values 0xFF and
0x01 represent the upper and lower limits, respectively, of the
attainable adjustment in PAL mode.
For NTSC with pedestal, the setup can vary from 0 IRE to 22.5 IRE.
For NTSC without pedestal and for PAL, the setup can vary
from −7.5 IRE to +15 IRE.
The SD brightness control register is an 8-bit register. The seven
LSBs of this 8-bit register are used to control the brightness
level, which can be a positive or negative value.
For example, to add +20 IRE brightness level to an NTSC signal
with pedestal, write 0x28 to Subaddress 0xA1.
0 × (SD Brightness Value) =
0 × (IRE Value × 2.015631) =
0 × (20 × 2.015631) = 0 × (40.31262) ≈ 0x28
To add –7 IRE brightness level to a PAL signal, write 0x72 to
Subaddress 0xA1.
0 × (SD Brightness Value) =
The hue adjust value is calculated using the following equation:
0 × (IRE Value × 2.075631) =
Hue Adjust (°) = 0.17578125° (HCRd − 128)
0 × (7 × 2.015631) = 0x(14.109417) ≈ 0001110b
where HCRd is the hue adjust control register (decimal)
0001110b into twos complement = 1110010b = 0x72
For example, to adjust the hue by +4°, write 0x97 to the hue
adjust control register.
Table 45. Sample Brightness Control Values1
Setup Level
(NTSC) with
Pedestal
4
⎛
⎞ + 128 ≈ 151d = 0 x 97
⎜
⎟
⎝ 0.17578125 ⎠
where the sum is rounded to the nearest integer.
To adjust the hue by −4°, write 0x69 to the hue adjust control
register.
−4
⎛
⎞ + 128 ≈ 105d = 0 x 69
⎜
⎟
⎝ 0.17578125 ⎠
22.5 IRE
15 IRE
7.5 IRE
0 IRE
1
Setup Level
(NTSC)
Without
Pedestal
15 IRE
7.5 IRE
0 IRE
−7.5 IRE
Setup
Level
(PAL)
15 IRE
7.5 IRE
0 IRE
−7.5 IRE
Brightness
Control
Value
0x1E
0x0F
0x00
0x71
Values in the range of 0x3F to 0x44 could result in an invalid output signal.
where the sum is rounded to the nearest integer.
SD INPUT STANDARD AUTO DETECTION
SD BRIGHTNESS DETECT
Subaddress 0x87, Bit 5
Subaddress 0xBA
The ADV7342/ADV7343 include an SD input standard autodetect feature. This SD feature can be enabled by setting
Subaddress 0x87, Bit 5 to 1.
The ADV7342/ADV7343 allow monitoring of the brightness
level of the incoming video data. The SD brightness detect
register (Subaddress 0xBA) is a read-only register.
SD BRIGHTNESS CONTROL
Subaddress 0xA1, Bits[6:0]
When this feature is enabled, the SD brightness/WSS control
register (Subaddress 0xA1) is used to control brightness by
adding a programmable setup level onto the scaled Y data. This
feature can be enabled using Subaddress 0x87, Bit 3.
When enabled, the ADV7342/ADV7343 can automatically
identify an NTSC or PAL B/D/G/H/I input stream. The
ADV7342/ADV7343 automatically update the subcarrier
frequency registers with the appropriate value for the identified
standard. The ADV7342/ADV7343 are also configured to
correctly encode the identified standard.
The SD standard bits (Subaddress 0x80, Bits[1:0]) and the
subcarrier frequency registers are not updated to reflect the
identified standard. All registers retain their default or userdefined values.
NTSC WITHOUT PEDESTAL
+7.5 IRE
100 IRE
0 IRE
POSITIVE SETUP
VALUE ADDED
NEGATIVE SETUP
VALUE ADDED
Figure 68. Examples of Brightness Control Values
Rev. 0 | Page 55 of 88
06399-069
–7.5 IRE
NO SETUP
VALUE ADDED
ADV7342/ADV7343
with respect to the reference video output signal. The overall
gain of the signal is reduced from the reference signal.
DOUBLE BUFFERING
Subaddress 0x33, Bit 7 for ED/HD,
Subaddress 0x88, Bit 2 for SD
Double-buffered registers are updated once per field. Double
buffering improves overall performance, because modifications
to register settings are not made during active video, but take
effect prior to the start of the active video on the next field.
Double buffering can be activated on the following ED/HD
registers using Subaddress 0x33, Bit 7: ED/HD Gamma A and
Gamma B curves, and ED/HD CGMS registers.
Double buffering can be activated on the following SD registers
using Subaddress 0x88, Bit 2: SD Gamma A and Gamma B
curves, SD Y scale, SD Cr scale, SD Cb scale, SD brightness, SD
closed captioning, and SD Macrovision Bits[5:0] (Subaddress
0xE0, Bits[5:0]).
PROGRAMMABLE DAC GAIN CONTROL
Subaddress 0x0A to Subaddress 0x0B
It is possible to adjust the DAC output signal gain up or down
from its absolute level. This is illustrated in Figure 69.
DAC 4 to DAC 6 are controlled by Register 0x0A.
The range of this feature is specified for ±7.5% of the nominal
output from the DACs. For example, if the output current of the
DAC is 4.33 mA, the DAC gain control feature can change this
output current from 4.008 mA (−7.5%) to 4.658 mA (+7.5%).
The reset value of the control registers is 0x00, that is, nominal
DAC current is output. Table 46 is an example of how the
output current of the DACs varies for a nominal 4.33 mA
output current.
Table 46. DAC Gain Control
Reg. 0x0A or
Reg.0x0B
0100 0000 (0x40)
0011 1111 (0x3F)
0011 1110 (0x3E)
...
...
0000 0010 (0x02)
0000 0001 (0x01)
0000 0000 (0x00)
DAC
Current (mA)
4.658
4.653
4.648
...
...
4.43
4.38
4.33
% Gain
7.5000%
7.3820%
7.3640%
...
...
0.0360%
0.0180%
0.0000%
1111 1111 (0xFF)
1111 1110 (0xFE)
...
...
1100 0010 (0xC2)
1100 0001 (0xC1)
1100 0000 (0xC0)
4.25
4.23
...
...
4.018
4.013
4.008
−0.0180%
−0.0360%
...
...
−7.3640%
−7.3820%
−7.5000%
DAC 1 to DAC 3 are controlled by Register 0x0B.
CASE A
GAIN PROGRAMMED IN DAC OUTPUT LEVEL
REGISTERS, SUBADDRESS 0x0A, 0x0B
700mV
Note
Reset value,
nominal
GAMMA CORRECTION
Subaddress 0x44 to Subaddress 0x57 for ED/HD,
Subaddress 0xA6 to Subaddress 0xB9 for SD
300mV
CASE B
Generally, gamma correction is applied to compensate for the
nonlinear relationship between signal input and output
brightness level (as perceived on a CRT). It can also be applied
wherever nonlinear processing is used.
NEGATIVE GAIN PROGRAMMED IN
DAC OUTPUT LEVEL REGISTERS,
SUBADDRESS 0x0A, 0x0B
700mV
Gamma correction uses the function
SignalOUT = (SignalIN)γ
where γ = is the gamma correction factor.
06399-070
300mV
Figure 69. Programmable DAC Gain—Positive and Negative Gain
In Case A of Figure 69, the video output signal is gained. The
absolute level of the sync tip and blanking level both increase
with respect to the reference video output signal. The overall
gain of the signal is increased from the reference signal.
In Case B of Figure 69, the video output signal is reduced. The
absolute level of the sync tip and blanking level both decrease
Gamma correction is available for SD and ED/HD video. For
both variations, there are 20, 8-bit registers. They are used to
program the Gamma Correction Curve A and Gamma
Correction Curve B.
ED/HD gamma correction is enabled using Subaddress 0x35,
Bit 5. ED/HD Gamma Correction Curve A is programmed at
Subaddress 0x44 to Subaddress 0x4D, and ED/HD Gamma
Correction Curve B is programmed at Subaddress 0x4E to
Subaddress 0x57.
Rev. 0 | Page 56 of 88
ADV7342/ADV7343
SD gamma correction is enabled using Subaddress 0x88, Bit 6.
SD Gamma Correction Curve A is programmed at Subaddress
0xA6 to Subaddress 0xAF, and SD Gamma Correction Curve B
is programmed at Subaddress 0xB0 to Subaddress 0xB9.
Gamma correction is performed on the luma data only. The
user can choose one of two correction curves, Curve A or
Curve B. Only one of these curves can be used at a time. For
ED/HD gamma correction, curve selection is controlled using
Subaddress 0x35, Bit 4. For SD gamma correction, curve
selection is controlled using Subaddress 0x88, Bit 7.
The shape of the gamma correction curve is controlled by
defining the curve response at 10 different locations along the
curve. By altering the response at these locations, the shape of
the gamma correction curve can be modified. Between these
points, linear interpolation is used to generate intermediate
values. Considering the curve has a total length of 256 points,
the 10 programmable locations are at points 24, 32, 48, 64, 80,
96, 128, 160, 192, and 224. Locations 0, 16, 240, and 255 are
fixed and cannot be changed.
To program the gamma correction registers, calculate the
10 programmable curve values using the following formula:
⎛ n − 16 ⎞ γ
⎞
γ n = ⎜⎜ ⎛⎜
⎟ × (240 − 16) ⎟⎟ + 16
⎝ ⎝ 240 − 16 ⎠
⎠
where:
γn is the value to be written into the gamma correction register
for point n on the gamma correction curve.
n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224.
γ is the gamma correction factor.
For example, setting γ = 0.5 for all programmable curve data
points results in the following yn values:
y24 = [(8/224)0.5 × 224] + 16 = 58
y32 = [(16/224)0.5 × 224] + 16 = 76
y48 = [(32/224)0.5 × 224] + 16 = 101
y64 = [(48/224)0.5 × 224] + 16 = 120
y80 = [(64/224)0.5 × 224] + 16 = 136
y96 = [(80/224)0.5 × 224] + 16 = 150
From curve locations 16 to 240, the values at the programmable
locations and, therefore, the response of the gamma correction
curve should be calculated to produce the following result:
xDESIRED = (xINPUT)
y128 = [(112/224)0.5 × 224] + 16 = 174
y160 = [(144/224)0.5 × 224] + 16 = 195
γ
y192 = [(176/224)0.5 × 224] + 16 = 214
where:
xDESIRED is the desired gamma corrected output.
xINPUT is the linear input signal.
γ is the gamma correction factor.
y224 = [(208/224)0.5 × 224] + 16 = 232
where the sum of each equation is rounded to the nearest integer.
The gamma curves in Figure 70 and Figure 71 are examples only;
any user-defined curve in the range from 16 to 240 is acceptable.
GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT
300
GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR
VARIOUS GAMMA VALUES
250
0.5
150
100
SIGNAL INPUT
50
0
0
50
100
150
LOCATION
200
250
250
0.5
150
100
SI
AL
GN
T
PU
IN
1.5
1.8
50
0
Figure 70. Signal Input (Ramp) and Signal Output for Gamma 0.5
0.3
200
0
50
100
150
LOCATION
200
250
Figure 71. Signal Input (Ramp) and Selectable Output Curves
Rev. 0 | Page 57 of 88
06399-072
200
GAMMA CORRECTED AMPLITUDE
SIGNAL OUTPUT
06399-071
GAMMA CORRECTED AMPLITUDE
300
ADV7342/ADV7343
There are three filter modes available on the ADV7342/ADV7343:
a sharpness filter mode and two adaptive filter modes.
ED/HD Sharpness Filter Mode
To enhance or attenuate the Y signal in the frequency ranges
shown in Figure 72, the ED/HD sharpness filter must be
enabled (Subaddress 0x31, Bit 7) and the ED/HD adaptive filter
must be disabled (Subaddress 0x35, Bit 7).
To select one of the 256 individual responses, the corresponding
gain values, which range from –8 to +7 for each filter, must be
programmed into the ED/HD sharpness filter gain register at
Subaddress 0x40.
The edges can then be attenuated with the settings in the
ED/HD Adaptive Filter Gain 1, 2, and 3 registers (Subaddress
0x58, Subaddress 0x59, and Subaddress 0x5A, respectively), and
the ED/HD sharpness filter gain register (Subaddress 0x40).
There are two adaptive filter modes available. The mode
is selected using the ED/HD adaptive filter mode control
(Subaddress 0x35, Bit 6):
•
ED/HD Adaptive Filter Mode
The ED/HD Adaptive Filter Threshold A, B, and C registers, the
ED/HD Adaptive Filter Gain 1, 2, and 3 registers, and the
ED/HD sharpness filter gain register are used in adaptive filter
mode. To activate the adaptive filter control, the ED/HD
sharpness filter and the ED/HD adaptive filter must be enabled
(Subaddress 0x31, Bit 7, and Subaddress 0x35, Bit 7, respectively).
SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK
1.5
1.4
1.4
1.3
1.3
1.2
1.2
MAGNITUDE
INPUT SIGNAL:
STEP
MAGNITUDE
1.5
1.1
1.0
0.9
1.1
1.0
0.9
0.8
0.8
0.7
0.7
0.6
0.6
0.5
•
Mode A is used when the ED/HD adaptive filter mode
control is set to 0. In this case, Filter B (LPF) is used in the
adaptive filter block. In addition, only the programmed
values for Gain B in the ED/HD sharpness filter gain
register and ED/HD Adaptive Filter Gain 1, 2, and 3
registers are applied when needed. The Gain A values are
fixed and cannot be changed.
Mode B is used when ED/HD adaptive filter mode control
is set to 1. In this mode, a cascade of Filter A and Filter B is
used. Both settings for Gain A and Gain B in the ED/HD
sharpness filter gain register and ED/HD Adaptive Filter
Gain 1, 2, and 3 registers become active when needed.
FREQUENCY (MHz)
FILTER A RESPONSE (Gain Ka)
0.5
FREQUENCY (MHz)
FILTER B RESPONSE (Gain Kb)
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0
2
6
8
4
10
FREQUENCY (MHz)
12
FREQUENCY RESPONSE IN SHARPNESS
FILTER MODE WITH Ka = 3 AND Kb = 7
Figure 72. ED/HD Sharpness and Adaptive Filter Control Block
Rev. 0 | Page 58 of 88
06399-073
Subaddress 0x40, Subaddress 0x58 to Subaddress 0x5D
The derivative of the incoming signal is compared to the three
programmable threshold values: ED/HD Adaptive Filter
Threshold A, B, and C (Subaddress 0x5B, Subaddress 0x5C,
and Subaddress 0x5D, respectively). The recommended
threshold range is 16 to 235, although any value in the range of
0 to 255 can be used.
MAGNITUDE RESPONSE (Linear Scale)
ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER
CONTROLS
ADV7342/ADV7343
d
a
R2
1
e
b
R4
R1
c
R2
CH1 500mV
REF A
500mV 4.00µs
M 4.00µs
1
9.99978ms
CH1
ALL FIELDS
CH1 500mV
REF A
500mV 4.00µs
1
M 4.00µs
9.99978ms
CH1
ALL FIELDS
06399-074
1
f
Figure 73. ED/ HD Sharpness Filter Control with Different Gain Settings for ED/HD Sharpness Filter Gain Values
ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER
APPLICATION EXAMPLES
Sharpness Filter Application
The ED/HD sharpness filter can be used to enhance or
attenuate the Y video output signal. The register settings in
Table 47 were used to achieve the results shown in Figure 73.
Input data was generated by an external signal source.
Table 47. ED/HD Sharpness Control
Subaddress
0x00
0x01
0x02
0x30
0x31
0x40
0x40
0x40
0x40
0x40
0x40
Reference1
a
b
c
d
e
f
The register settings in Table 48 are used to obtain the results
shown in Figure 75, that is, to remove the ringing on the input
Y signal, as shown in Figure 74. Input data is generated by an
external signal source.
Table 48. Register Settings for Figure 75
Subaddress
0x00
0x01
0x02
0x30
0x31
0x35
0x40
0x58
0x59
0x5A
0x5B
0x5C
0x5D
Register Setting
0xFC
0x38
0x20
0x00
0x81
0x80
0x00
0xAC
0x9A
0x88
0x28
0x3F
0x64
06399-076
See Figure 73.
06399-075
1
Register Setting
0xFC
0x10
0x20
0x00
0x81
0x00
0x08
0x04
0x40
0x80
0x22
Adaptive Filter Control Application
Figure 75. Output Signal from ED/HD Adaptive Filter (Mode A)
Figure 74. Input Signal to ED/HD Adaptive Filter
Rev. 0 | Page 59 of 88
ADV7342/ADV7343
When changing the adaptive filter mode to Mode B
(Subaddress 0x35, Bit 6), the output shown in Figure 76
can be obtained.
DNR MODE
DNR CONTROL
BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET
GAIN
NOISE
SIGNAL PATH
CORING GAIN DATA
CORING GAIN BORDER
INPUT FILTER
BLOCK
FILTER
OUTPUT
< THRESHOLD?
Y DATA
INPUT
FILTER OUTPUT
> THRESHOLD
–
SUBTRACT
SIGNAL IN
THRESHOLD
RANGE FROM
ORIGINAL SIGNAL
+
DNR OUT
06399-077
MAIN SIGNAL PATH
DNR
SHARPNESS
MODE
Figure 76. Output Signal from ED/HD Adaptive Filter (Mode B)
DNR CONTROL
BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET
SD DIGITAL NOISE REDUCTION
GAIN
Subaddress 0xA3 to Subaddress 0xA5
In DNR mode, if the absolute value of the filter output is smaller
than the threshold, it is assumed to be noise. A programmable
amount (coring gain border, coring gain data) of this noise
signal is subtracted from the original signal. In DNR sharpness
mode, if the absolute value of the filter output is less than the
programmed threshold, it is assumed to be noise. Otherwise, if
the level exceeds the threshold, now identified as a valid signal,
a fraction of the signal (coring gain border, coring gain data) is
added to the original signal to boost high frequency components
and sharpen the video image.
In MPEG systems, it is common to process the video information
in blocks of 8 pixels × 8 pixels for MPEG2 systems, or 16 pixels ×
16 pixels for MPEG1 systems (block size control). DNR can be
applied to the resulting block transition areas that are known to
contain noise. Generally, the block transition area contains two
pixels. It is possible to define this area to contain four pixels
(border area).
It is also possible to compensate for variable block positioning
or differences in YCrCb pixel timing with the use of the DNR
block offset.
The digital noise reduction registers are three 8-bit registers.
They are used to control the DNR processing.
NOISE
SIGNAL PATH
INPUT FILTER
BLOCK
Y DATA
INPUT
ADD SIGNAL
ABOVE
THRESHOLD
RANGE FROM
ORIGINAL SIGNAL
FILTER
OUTPUT
> THRESHOLD?
FILTER OUTPUT
< THRESHOLD
+
+
MAIN SIGNAL PATH
DNR OUT
06399-078
Digital noise reduction (DNR) is applied to the Y data only.
A filter block selects the high frequency, low amplitude components of the incoming signal (DNR input select). The absolute
value of the filter output is compared to a programmable
threshold value (DNR threshold control). There are two DNR
modes available, DNR mode and DNR sharpness mode.
CORING GAIN DATA
CORING GAIN BORDER
Figure 77. SD DNR Block Diagram
Coring Gain Border—Subaddress 0xA3, Bits[3:0]
These four bits are assigned to the gain factor applied to border
areas. In DNR mode, the range of gain values is 0 to 1 in
increments of 1/8. This factor is applied to the DNR filter
output that lies below the set threshold range. The result is then
subtracted from the original signal.
In DNR sharpness mode, the range of gain values is 0 to 0.5 in
increments of 1/16. This factor is applied to the DNR filter
output that lies above the threshold range. The result is added to
the original signal.
Coring Gain Data—Subaddress 0xA3, Bits[7:4]
These four bits are assigned to the gain factor applied to the luma
data inside the MPEG pixel block. In DNR mode, the range of
gain values is 0 to 1 in increments of 1/8. This factor is applied
to the DNR filter output that lies below the set threshold range.
The result is then subtracted from the original signal.
In DNR sharpness mode, the range of gain values is 0 to 0.5 in
increments of 1/16. This factor is applied to the DNR filter
output that lies above the threshold range. The result is added to
the original signal.
Rev. 0 | Page 60 of 88
ADV7342/ADV7343
APPLY DATA
CORING GAIN
APPLY BORDER
CORING GAIN
DNR Mode Control—Subaddress 0xA5, Bit 4
This bit controls the DNR mode selected. Logic 0 selects DNR
mode; Logic 1 selects DNR sharpness mode.
OXXXXXXOOXXXXXXO
OFFSET CAUSED
BY VARIATIONS IN
INPUT TIMING
06399-079
OXXXXXXOOXXXXXXO
OXXXXXXOOXXXXXXO
DNR27 TO DNR24 = 0x01
Figure 78. SD DNR Offset Control
DNR Threshold—Subaddress 0xA4, Bits[5:0]
These six bits are used to define the threshold value in the range
of 0 to 63. The range is an absolute value.
Border Area—Subaddress 0xA4, Bit 6
When this bit is set to Logic 1, the block transition area can be
defined to consist of four pixels. If this bit is set to Logic 0, the
border transition area consists of two pixels, where one pixel
refers to two clock cycles at 27 MHz.
720 × 485 PIXELS
(NTSC)
2-PIXEL
BORDER
DATA
DNR works on the principle of defining low amplitude, high
frequency signals as probable noise and subtracting this noise
from the original signal.
In DNR mode, it is possible to subtract a fraction of the signal
that lies below the set threshold, assumed to be noise, from the
original signal. The threshold is set in DNR Register 1.
When DNR sharpness mode is enabled, it is possible to add a
fraction of the signal that lies above the set threshold to the
original signal, because this data is assumed to be valid data and
not noise. The overall effect is that the signal is boosted (similar
to using the extended SSAF filter).
DNR Block Offset Control—Subaddress 0xA5, Bits[7:4]
Four bits are assigned to this control, which allows a shift of the
data block of 15 pixels maximum. Consider the coring gain
positions fixed. The block offset shifts the data in steps of one
pixel such that the border coring gain factors can be applied at the
same position regardless of variations in input timing of the data.
SD ACTIVE VIDEO EDGE CONTROL
Subaddress 0x82, Bit 7
8 × 8 PIXEL BLOCK
The ADV7342/ADV7343 are able to control fast rising and
falling signals at the start and end of active video in order to
minimize ringing.
06399-080
8 × 8 PIXEL BLOCK
Figure 79. SD DNR Border Area
Block Size Control—Subaddress 0xA4, Bit 7
This bit is used to select the size of the data blocks to be
processed. Setting the block size control function to Logic 1
defines a 16 pixel × 16 pixel data block, and Logic 0 defines an
8 pixel × 8 pixel data block, where one pixel refers to two clock
cycles at 27 MHz.
DNR Input Select Control—Subaddress 0xA5, Bits[2:0]
Three bits are assigned to select the filter, which is applied to the
incoming Y data. The signal that lies in the pass band of the
selected filter is the signal that is DNR processed. Figure 80
shows the filter responses selectable with this control.
When the active video edge control feature is enabled
(Subaddress 0x82, Bit 7 = 1), the first three pixels and the last
three pixels of the active video on the luma channel are scaled
so that maximum transitions on these pixels are not possible.
At the start of active video, the first three pixels are multiplied
by 1/8, 1/2, and 7/8, respectively. Approaching the end of active
video, the last three pixels are multiplied by 7/8, 1/2, and 1/8,
respectively. All other active video pixels pass through
unprocessed.
1.0
FILTER D
FILTER C
0.6
0.4
FILTER B
0.2
FILTER A
0
0
1
2
3
4
FREQUENCY (MHz)
5
6
06399-081
MAGNITUDE
0.8
Figure 80. SD DNR Input Select
Rev. 0 | Page 61 of 88
ADV7342/ADV7343
LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
DISABLED
LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
ENABLED
100 IRE
100 IRE
87.5 IRE
50 IRE
06399-082
12.5 IRE
0 IRE
0 IRE
Figure 81. Example of Active Video Edge Functionality
VOLTS
IRE:FLT
100
0.5
50
0
F2
L135
–50
0
2
4
6
8
10
12
06399-083
0
Figure 82. Example of Video Output with Subaddress 0x82, Bit 7 = 0
VOLTS
IRE:FLT
100
0.5
50
0
F2
L135
–50
–2
0
2
4
6
8
10
Figure 83. Example of Video Output with Subaddress 0x82, Bit 7 = 1
Rev. 0 | Page 62 of 88
12
06399-084
0
ADV7342/ADV7343
EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL
For timing synchronization purposes, the ADV7342/ADV7343 are able to accept either EAV/SAV time codes embedded in the input
pixel data or external synchronization signals provided on the S_HSYNC, S_VSYNC, P_HSYNC, P_VSYNC, and P_BLANK pins (see
Table 49). It is also possible to output synchronization signals on the S_HSYNC and S_VSYNC pins (see Table 50 to Table 52).
Table 49. Timing Synchronization Signal Input Options
Signal
SD HSYNC In
SD VSYNC/FIELD In
ED/HD HSYNC In
ED/HD VSYNC/FIELD In
ED/HD BLANK In
1
Pin
S_HSYNC
S_VSYNC
P_HSYNC
P_VSYNC
P_BLANK
Condition
SD Slave Timing Mode 1, 2, or 3 Selected (Subaddress 0x8A[2:0]).1
SD Slave Timing Mode 1, 2, or 3 Selected (Subaddress 0x8A[2:0]).1
ED/HD Timing Synchronization Inputs Enabled (Subaddress 0x30, Bit 2 = 0).
ED/HD Timing Synchronization Inputs Enabled (Subaddress 0x30, Bit 2 = 0).
SD and ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02[7:6] = 00).
Table 50. Timing Synchronization Signal Output Options
Signal
SD HSYNC Out
SD VSYNC/FIELD Out
ED/HD HSYNC Out
ED/HD VSYNC/FIELD Out
1
Pin
S_HSYNC
S_VSYNC
S_HSYNC
S_VSYNC
Condition
SD Timing Synchronization Outputs Enabled (Subaddress 0x02, Bit 6 = 1).1
SD Timing Synchronization Outputs Enabled (Subaddress 0x02, Bit 6 = 1).1
ED/HD Timing Synchronization Outputs Enabled (Subaddress 0x02, Bit 7 = 1).
ED/HD Timing Synchronization Outputs Enabled (Subaddress 0x02, Bit 7 = 1).
ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02, Bit 7 = 0).
Table 51. S_HSYNC Output Control1
ED/HD Input Sync
Format (0x30, Bit 2)
x
x
ED/HD HSYNC
Control
(0x34, Bit 1)
x
x
ED/HD Sync
Output Enable
(0x02, Bit 7)
0
0
SD Sync
Output Enable
(0x02, Bit 6)
0
1
0
1
0
0
1
1
x
x
x
1
1
x
1
Signal on S_HSYNC Pin
Tristate.
Pipelined SD HSYNC.
Pipelined ED/HD HSYNC.
Pipelined ED/HD HSYNC based on
AV Code H bit.
Pipelined ED/HD HSYNC based on
horizontal counter.
Duration
–
See Appendix 5—
SD Timing.
As per HSYNC timing.
Same as line blanking
interval.
Same as embedded
HSYNC.
In all ED/HD standards where there is an HSYNC output, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video.
Table 52. S_VSYNC Output Control 1
ED/HD Input
Sync Format
(0x30, Bit 2)
x
x
ED/HD VSYNC
Control
(0x34, Bit 2)
X
X
ED/HD Sync
Output Enable
(0x02, Bit 7)
0
0
SD Sync
Output Enable
(0x02, Bit 6)
0
1
Video Standard
x
Interlaced
0
0
1
x
x
1
0
1
x
1
0
1
x
x
1
1
x
x
1
1
x
All HD interlaced
standards
All ED/HD
progressive
standards
All ED/HD
standards
except 525p
525p
1
Signal on S_VSYNC Pin
Duration
–
See Appendix
Tristate.
Pipelined SD VSYNC
/Field.
Pipelined ED/HD VSYNC
or field signal.
Pipelined field signal
based on AV Code F bit.
Pipelined VSYNC based
on AV Code V bit.
Vertical blanking
interval.
Pipelined ED/HD VSYNC
based on vertical counter.
Aligned with
serration lines.
Pipelined ED/HD VSYNC
based on vertical counter.
Vertical blanking
interval.
5—SD Timing.
As per VSYNC or
field signal timing.
Field.
In all ED/HD standards where there is a VSYNC output, the start of the VSYNC pulse is aligned with the falling edge of the embedded VSYNC in the output video.
Rev. 0 | Page 63 of 88
ADV7342/ADV7343
LOW POWER MODE
Subaddress 0x0D, Bits[2:0]
For power sensitive applications, the ADV7342/ADV7343
support an Analog Devices, Inc. proprietary low power mode of
operation on DAC 1, DAC 2, and DAC 3. To utilize this low
power mode, these DACs must be operating in full-drive mode
(RSET = 510 Ω, RL = 37.5 Ω). Low power mode is not available in
low drive mode (RSET = 4.12 kΩ, RL = 300 Ω). Low power mode
can be independently enabled or disabled on DAC 1, DAC 2, and
DAC 3 using Subaddress 0x0D, Bits[2:0]. Low power mode is
disabled by default on each DAC.
In low power mode, DAC current consumption is content
dependent. On a typical video stream, it can be reduced by as
much as 40%. For applications requiring the highest possible video
performance, low power mode should be disabled.
With this feature enabled, the cable detection circuitry monitors
DAC 1 and/or DAC 2 once per frame. If they are unconnected,
some or all of the DACs automatically power down. Which
DAC or DACs are powered down depends on the selected
output configuration.
For CVBS/YC output configurations, if DAC 1 is unconnected,
only DAC 1 powers down. If DAC 2 is unconnected, DAC 2 and
DAC 3 power down.
For YPrPb and RGB output configurations, if DAC 1 is
unconnected, all three DACs power down. DAC 2 is not
monitored for YPrPb and RGB output configurations.
CABLE DETECTION
Once per frame, DAC 1 and/or DAC 2 are monitored. If a cable
is detected, the appropriate DAC or DACs remain powered up
for the duration of the frame. If no cable is detected, the appropriate
DAC or DACs power down until the next frame, when the process
is repeated.
Subaddress 0x10
PIXEL AND CONTROL PORT READBACK
The ADV7342/ADV7343 include an Analog Devices, Inc.
proprietary cable detection feature.
Subaddress 0x12 to Subaddress 0x14, Subaddress 0x16
The cable detection feature is available on DAC 1 and DAC 2,
while operating in full-drive mode (RSET1 = 510 Ω, RL1 = 37.5 Ω,
assuming a connected cable). The feature is not available in low
drive mode (RSET = 4.12 kΩ, RL = 300 Ω). For a DAC to be
monitored, the DAC must be powered up in Subaddress 0x00.
The cable detection feature can be used with all SD, ED, and
HD video standards. It is available for all output configurations,
that is, CVBS, YC, YPrPb, and RGB output configurations.
For CVBS/YC output configurations, both DAC 1 and DAC 2
are monitored, that is, the CVBS and YC luma outputs are
monitored. For YPrPb and RGB output configurations, only
DAC 1 is monitored, that is, the luma or green output is
monitored.
Once per frame, the ADV7342/ADV7343 monitor DAC 1
and/or DAC 2, updating Subaddress 0x10, Bit 0 and Bit 1,
respectively. If a cable is detected on one of the DACs, the
relevant bit is set to 0. If not, the bit is set to 1.
The ADV7342/ADV7343 support the readback of most digital
inputs via the I2C/SPI MPU port. This feature is useful for
board level connectivity testing with upstream devices.
The pixel port (S[7:0], Y[7:0], and C[7:0]), the control port
(S_HSYNC, S_VSYNC, P_HSYNC, P_VSYNC and P_BLANK),
and the SFL/MISO pin are available for readback via the MPU
port. The readback registers are located at Subaddress 0x12 to
Subaddress 0x14 and Subaddress 0x16.
When using this feature, a clock signal should be applied to the
CLKIN_A pin to register the levels applied to the input pins.
RESET MECHANISM
Subaddress 0x17, Bit 1
The ADV7342/ADV7343 have a software reset accessible via
the I2C/SPI MPU port. A software reset is activated by writing
a 1 to Subaddress 0x17, Bit 1. This resets all registers to their
default values. This bit is self-clearing, that is, after a 1 has been
written to the bit, the bit automatically returns to 0.
When operating in SPI mode, a software reset does not cause
the device to revert to I2C mode. For this to occur, the
ADV7342/ADV7343 need to be powered down.
DAC AUTO POWER-DOWN
Subaddress 0x10, Bit 4
For power sensitive applications, a DAC auto power-down
feature can be enabled using Subaddress 0x10, Bit 4. This feature
is only available when the cable detection feature is enabled.
The ADV7342/ADV7343 include a power-on reset (POR)
circuit to ensure correct operation after power-up.
Rev. 0 | Page 64 of 88
ADV7342/ADV7343
PRINTED CIRCUIT BOARD LAYOUT AND DESIGN
DAC CONFIGURATIONS
The ADV7342/ADV7343 contain six DACs. All six DACs can
be configured to operate in low drive mode. Low drive mode is
defined as 4.33 mA full-scale current into a 300 Ω load, RL.
DAC 1, DAC 2, and DAC 3 can also be configured to operate in
full-drive mode. Full-drive mode is defined as 34.7 mA fullscale current into a 37.5 Ω load, RL. Full-drive is the recommended
mode of operation for DAC 1, DAC 2, and DAC 3.
The ADV7342/ADV7343 contain two RSET pins. A resistor
connected between the RSET1 pin and AGND is used to control
the full-scale output current and, therefore, the DAC output
voltage levels of DAC 1, DAC 2, and DAC 3. For low drive
operation, RSET1 must have a value of 4.12 kΩ, and RL must have a
value of 300 Ω. For full-drive operation, RSET1 must have a value
of 510 Ω, and RL must have a value of 37.5 Ω.
A resistor connected between the RSET2 pin and AGND is used
to control the full-scale output current and, therefore, the DAC
output voltage levels of DAC 4, DAC 5, and DAC 6. RSET2 must
have a value of 4.12 kΩ, and RL must have a value of 300 Ω (that
is, low drive operation only).
For applications requiring an output buffer and reconstruction
filter, the ADA4430-1, ADA4411-3, and ADA4410-6 integrated
video filter buffers should be considered.
Table 53. ADV7342/ADV7343 Output Rates
Input Mode
(0x01, Bits[6:4])
SD Only
PLL Control
(0x00, Bit 1)
Off
On
Off
On
Off
On
ED Only
HD Only
Output Rate (MHz)
27
(2x)
216
(16x)
27
(1x)
216
(8x)
74.25
(1x)
297
(4x)
Table 54. Output Filter Requirements
The resistors connected to the RSET1 and RSET2 pins should have a
1% tolerance.
Application
SD
SD
ED
ED
HD
HD
The ADV7342/ADV7343 contain two compensation pins,
COMP1 and COMP2. A 2.2 nF compensation capacitor should
be connected from each of these pins to VAA.
DAC
OUTPUT
Cutoff
Frequency
(MHz)
>6.5
>6.5
>12.5
>12.5
>30
>30
Oversampling
2×
16×
1×
8×
1×
4×
Attenuation
–50 dB @
(MHz)
20.5
209.5
14.5
203.5
44.25
267
10µH
3
600Ω
VOLTAGE REFERENCE
22pF
600Ω
75Ω
1
BNC
OUTPUT
4
Figure 84. Example of Output Filter for SD, 16× Oversampling
4.7µH
DAC
OUTPUT
3
6.8pF
6.8pF
75Ω
BNC
OUTPUT
1
4
560Ω
560Ω
06399-086
600Ω
600Ω
VIDEO OUTPUT BUFFER AND OPTIONAL
OUTPUT FILTER
An output buffer is necessary on any DAC that operates in low
drive mode (RSET = 4.12 kΩ, RL = 300 Ω). Analog Devices, Inc.
produces a range of op amps suitable for this application, for
example, the AD8061. For more information about line driver
buffering circuits, see the relevant op amp data sheet.
560Ω
06399-085
560Ω
Figure 85. Example of Output Filter for ED, 8× Oversampling
DAC
OUTPUT
3
300Ω
An optional reconstruction (anti-imaging) low-pass filter (LPF)
may be required on the ADV7342/ADV7343 DAC outputs if
the ADV7342/ADV7343 are connected to a device that requires
this filtering.
The filter specifications vary with the application. The use of
16× (SD), 8× (ED), or 4× (HD) oversampling can remove the
requirement for a reconstruction filter altogether.
Rev. 0 | Page 65 of 88
1
4
75Ω
390nH
BNC
OUTPUT
3
33pF
33pF
75Ω
1
4
500Ω
500Ω
Figure 86. Example of Output Filter for HD, 4× Oversampling
06399-087
The ADV7342/ADV7343 contain an on-chip voltage reference
that can be used as a board-level voltage reference via the VREF
pin. Alternatively, the ADV7342/ADV7343 can be used with an
external voltage reference by connecting the reference source to
the VREF pin. For optimal performance, an external voltage
reference such as the AD1580 should be used with the ADV7342/
ADV7343. If an external voltage reference is not used, a 0.1 μF
capacitor should be connected from the VREF pin to VAA.
ADV7342/ADV7343
CIRCUIT FREQUENCY RESPONSE
0
0
–10
The ADV7342/ADV7343 are highly integrated circuits
containing both precision analog and high speed digital
circuitry. They have been designed to minimize interference
effects on the integrity of the analog circuitry by the high speed
digital circuitry. It is imperative that these same design and
layout techniques be applied to the system-level design so that
optimal performance is achieved.
21n
MAGNITUDE (dB)
–60
–20
18n
–90
–30
PHASE (Degrees)
15n
–120
–40
12n
–150
–50
9n
–180
GROUP DELAY (Seconds)
–60
The layout should be optimized for lowest noise on the
ADV7342/ADV7343 power and ground planes by shielding the
digital inputs and providing good power supply decoupling.
6n
–210
–70
–80
1M
3n
–240
0
1G
10M
100M
FREQUENCY (Hz)
06399-088
GAIN (dB)
PRINTED CIRCUIT BOARD (PCB) LAYOUT
24n
–30
Figure 87. Output Filter Plot for SD, 16× Oversampling
It is recommended to use a 4-layer printed circuit board with
ground and power planes separating the signal trace layer and
the solder side layer.
Component Placement
CIRCUIT FREQUENCY RESPONSE
0
Component placement should be carefully considered to
separate noisy circuits, such as clock signals and high speed
digital circuitry from analog circuitry.
480
18n
400
–10
MAGNITUDE (dB)
16n
–20
320
–30
240
The external loop filter components and components connected
to the COMP, VREF, and RSET pins should be placed as close as
possible to and on the same side of the PCB as the ADV7342/
ADV7343. Adding vias to the PCB to get the components closer
to the ADV7342/ADV7343 are not recommended.
GAIN (dB)
14n
PHASE
(Degrees)
GROUP DELAY (Seconds)
–40
160
12n
10n
–50
80
–60
0
–70
–80
–80
–160
8n
It is recommended that the ADV7342/ADV7343 be placed as
close as possible to the output connector, with the DAC output
traces as short as possible.
6n
4n
10M
2n
–240
0
1G
100M
06399-089
–90
1M
FREQUENCY (Hz)
Figure 88. Output Filter Plot for ED, 8× Oversampling
CIRCUIT FREQUENCY RESPONSE
0
PHASE
(Degrees)
External filter and buffer components connected to the DAC
outputs should be placed as close as possible to the ADV7342/
ADV7343 to minimize the possibility of noise pickup from
neighboring circuitry, and to minimize the effect of trace
capacitance on output bandwidth. This is particularly important
when operating in low drive mode (RSET = 4.12 kΩ, RL = 300 Ω).
200
MAGNITUDE (dB)
GAIN (dB)
GROUP DELAY (Seconds)
PHASE (Degrees)
120
–20
40
–30
–40
–40
–120
–50
1
10
100
FREQUENCY (MHz)
Figure 89. Output Filter Plot for HD, 4× Oversampling
–200
Power Supplies
06399-090
–10
The termination resistors on the DAC output traces should be
placed as close as possible to and on the same side of the PCB as
the ADV7342/ADV7343. The termination resistors should
overlay the PCB ground plane.
It is recommended that a separate regulated supply be provided
for each power domain (VAA, VDD, VDD_IO, and PVDD). For
optimal performance, linear regulators rather than switch mode
regulators should be used. If switch mode regulators must be
used, care must be taken with regard to the quality of the output
voltage in terms of ripple and noise. This is particularly true for
the VAA and PVDD power domains. Each power supply should be
individually connected to the system power supply at a single
point through a suitable filtering device, such as a ferrite bead.
Rev. 0 | Page 66 of 88
ADV7342/ADV7343
Power Supply Decoupling
It is recommended that each power supply pin be decoupled
with 10 nF and 0.1 μF ceramic capacitors. The VAA, PVDD,
VDD_IO, and both VDD pins should be individually decoupled to
ground. The decoupling capacitors should be placed as close as
possible to the ADV7342/ADV7343 with the capacitor leads
kept as short as possible to minimize lead inductance.
A 1 μF tantalum capacitor is recommended across the VAA
supply in addition to the 10 nF and 0.1 μF ceramic capacitors.
Power Supply Sequencing
The ADV7342/ADV7343 are robust to all power supply
sequencing combinations. Any particular sequence can be used.
Digital Signal Interconnect
The digital signal traces should be isolated as much as possible
from the analog outputs and other analog circuitry. Digital
signal traces should not overlay the VAA or PVDD power planes.
Due to the high clock rates used, avoid long clock traces to the
ADV7342/ADV7343 to minimize noise pickup.
Any pull-up termination resistors for the digital inputs should
be connected to the VDD power supply.
Any unused digital inputs should be tied to ground.
Analog Signal Interconnect
DAC output traces should be treated as transmission lines with
appropriate measures taken to ensure optimal performance (for
example, impedance matched traces). The DAC output traces
should be kept as short as possible. The termination resistors on
the DAC output traces should be placed as close as possible to
and on the same side of the PCB as the ADV7342/ADV7343.
To avoid crosstalk between the DAC outputs, it is recommended that as much space as possible be left between the
traces connected to the DAC output pins. Adding ground traces
between the DAC output traces is also recommended.
Rev. 0 | Page 67 of 88
ADV7342/ADV7343
TYPICAL APPLICATION CIRCUIT
FERRITE BEAD
33µF
10µF
GND_IO
GND_IO
FERRITE BEAD
PVDD
(1.8V)
33µF
10µF
0.1µF
0.01µF
GND_IO
GND_IO
0.1µF
0.01µF
PGND
PGND
FERRITE BEAD
VAA
33µF
PGND
10µF
AGND
AGND
FERRITE BEAD
VDD
(1.8V)
33µF
DGND
AGND
10µF
0.1µF
DGND
PGND
AGND
VDD POWER SUPPLY
DECOUPLING FOR
EACH POWER PIN
DGND
VAA
VDD_IO
VAA
PVDD
VDD
VDD
2.2nF
PIXEL PORT INPUTS
3. THE RESISTORS CONNECTED TO THE RSET PINS SHOULD HAVE A 1%
TOLERANCE.
VAA POWER
SUPPLY
AGND DECOUPLING
VAA
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
ALSB/SPI_SS = 0, I2C DEVICE ADDRESS = 0xD4 OR 0x54
ALSB/SPI_SS = 1, I2C DEVICE ADDRESS = 0xD6 OR 0x56
1µF
0.01µF
DGND
2. WHEN OPERATING IN I2C MODE, THE I2C DEVICE ADDRESS IS
CONFIGURABLE USING THE ALSB/SPI_SS PIN:
PVDD POWER
SUPPLY
DECOUPLING
0.01µF
0.1µF
NOTES
1. FOR OPTIMUM PERFORMANCE, EXTERNAL COMPONENTS CONNECTED
TO THE COMP, RSET , VREF AND DAC OUTPUT PINS SHOULD BE LOCATED
CLOSE TO AND ON THE SAME SIDE OF THE PCB AS THE ADV7342/ADV7343.
VDD_IO POWER
SUPPLY
DECOUPLING
VAA
COMP1
COMP2
1.1kΩ
1.235V
VREF
AD1580
0.1µF
ADV7342/ADV7343
S0
S1
S2
S3
S4
S5
S6
S7
C0
C1
C2
C3
C4
C5
C6
C7
OPTIONAL. IF THE INTERNAL VOLTAGE
REFERENCE IS USED, A 0.1µF CAPACITOR
SHOULD BE CONNECTED FROM VREF TO VAA.
2.2nF
RSET1
AGND
RSET2
510Ω
4.12kΩ
AGND
AGND
OPTIONAL LPF
DAC 1
DAC 1
OPTIONAL LPF
DAC 2
DACs 1-3 FULL DRIVE OPTION
DAC 2
DAC 3
DAC 3
OPTIONAL LPF
75Ω
75Ω
75Ω
AGND
AGND
AGND
DACs 1-3 LOW DRIVE OPTION
OPTIONAL LPF
DAC 4
AD8061
+
–
+V
–V
75Ω
DAC 4
RSET1
4.12kΩ
AGND
300Ω
UNUSED
CONNECT TO DGND
S_HSYNC
S_VSYNC
CONTROL
INPUTS/OUTPUTS
CLOCK INPUTS
MPU PORT
INPUTS/OUTPUTS
510Ω
TEST0
TEST1
TEST2
TEST3
TEST4
TEST5
AGND
AGND
150nF
+V
–V
75Ω
510Ω
DAC 5
AGND
510Ω
OPTIONAL LPF
AGND
–
AGND
+
+V
–V
75Ω
510Ω
DAC 6
AGND
510Ω
OPTIONAL LPF
AGND
170Ω
510Ω
DAC 3
AD8061
+
–
LOOP FILTER COMPONENTS
SHOULD BE LOCATED
CLOSE TO THE EXT_LF
PINS AND ON THE SAME
SIDE OF THE PCB AS THE
ADV7342/ADV7343.
AGND
AGND PGND DGND DGND
DAC 2
AGND
300Ω
GND_IO
75Ω
510Ω
AD8061
–
EXT_LF2
+V
–V
300Ω
OPTIONAL LPF
DAC 6
AGND PGND DGND DGND
AD8061
+
DAC 2
510Ω
170Ω
12nF
DAC 1
AGND
300Ω
SDA/SCLK
SCL/MOSI
SFL/MISO
ALSB/SPI_SS
75Ω
510Ω
–
CLKIN_A
CLKIN_B
+V
–V
300Ω
AD8061
+
EXT_LF1
150nF
–
OPTIONAL LPF
DAC 5
AD8061
+
DAC 1
510Ω
P_HSYNC
P_VSYNC
P_BLANK
EXTERNAL LOOP FILTERS
PVDD
12nF
OPTIONAL LPF
GND_IO
+V
–V
75Ω
DAC 3
300Ω
510Ω
AGND
510Ω
AGND
Figure 90. ADV7342/ADV7343 Typical Application Circuit
Rev. 0 | Page 68 of 88
06399-091
VDD_IO
ADV7342/ADV7343
APPENDIX 1—COPY GENERATION MANAGEMENT SYSTEM
SD CGMS
Subaddress 0x99 to Subaddress 0x9B
The ADV7342/ADV7343 support copy generation management
system (CGMS) conforming to the EIAJ CPR-1204 and ARIB
TR-B15 standards. CGMS data is transmitted on Line 20 of the
odd fields and Line 283 of even fields. Subaddress 0x99,
Bits[6:5] control whether CGMS data is output on odd or even
fields or both.
SD CGMS data can only be transmitted when the ADV7342/
ADV7343 are configured in NTSC mode. The CGMS data is 20
bits long. The CGMS data is preceded by a reference pulse of
the same amplitude and duration as a CGMS bit (see Figure 91).
When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 720p
CGMS data is applied to Line 24 of the luminance vertical
blanking interval.
When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 1080i
CGMS data is applied to Line 19 and Line 582 of the luminance
vertical blanking interval.
The HD CGMS data registers are at Subaddress 0x41,
Subaddress 0x42, and Subaddress 0x43.
The ADV7342/ADV7343 also support CGMS Type B packets in
HD mode (720p and 1080i) in accordance with CEA-805-A.
ED CGMS
When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 =
1), 720p CGMS data is applied to Line 23 of the luminance
vertical blanking interval.
Subaddress 0x41 to Subaddress 0x43
Subaddress 0x5E to Subaddress 0x6E
525p
When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 =
1), 1080i CGMS data is applied to Line 18 and Line 581 of the
luminance vertical blanking interval.
The ADV7342/ADV7343 support copy generation management
system (CGMS) in 525p mode in accordance with EIAJ CPR1204-1.
The HD CGMS Type B data registers are at Subaddress 0x5E to
Subaddress 0x6E.
When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 525p
CGMS data is inserted on Line 41. The 525p CGMS data
registers are at Subaddress 0x41, Subaddress 0x42, and
Subaddress 0x43.
The ADV7342/ADV7343 also support CGMS Type B packets in
525p mode in accordance with CEA-805-A.
When ED CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),
525p CGMS Type B data is inserted on Line 40. The 525p CGMS
Type B data registers are at Subaddress 0x5E to Subaddress 0x6E.
625p
The ADV7342/ADV7343 support copy generation management
system (CGMS) in 625p mode in accordance with IEC62375
(2004).
When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 625p
CGMS data is inserted on Line 43. The 625p CGMS data
registers are at Subaddress 0x42 and Subaddress 0x43.
HD CGMS
Subaddress 0x41 to Subaddress 0x43
Subaddress 0x5E to Subaddress 0x6E
The ADV7342/ADV7343 support copy generation management
system (CGMS) in HD mode (720p and 1080i) in accordance
with EIAJ CPR-1204-2.
CGMS CRC FUNCTIONALITY
If SD CGMS CRC (Subaddress 0x99, Bit 4) or ED/HD CGMS
CRC (Subaddress 0x32, Bit 7) is enabled, the upper six CGMS
data bits, C19 to C14, which comprise the 6-bit CRC check
sequence, are automatically calculated on the ADV7342/ADV7343.
This calculation is based on the lower 14 bits (C13 to C0) of the
data in the CGMS data registers and the result is output with
the remaining 14 bits to form the complete 20 bits of the CGMS
data. The calculation of the CRC sequence is based on the
polynomial x6 + x + 1 with a preset value of 111111.
If SD CGMS CRC or ED/HD CGMS CRC are disabled, all
20 bits (C19 to C0) are output directly from the CGMS registers
(CRC must be calculated by the user manually).
If ED/HD CGMS Type B CRC (Subaddress 0x5E, Bit 1) is
enabled, the upper six CGMS Type B data bits (P122 to P127)
that comprise the 6-bit CRC check sequence are automatically
calculated on the ADV7342/ADV7343. This calculation is
based on the lower 128 bits (H0 to H5 and P0 to P121) of the
data in the CGMS Type B data registers. The result is output
with the remaining 128 bits to form the complete 134 bits of the
CGMS Type B data. The calculation of the CRC sequence is
based on the polynomial x6 + x + 1 with a preset value of
111111.
If ED/HD CGMS Type B CRC is disabled, all 134 bits (H0 to H5
and P0 to P127) are output directly from the CGMS Type B
registers (CRC must be calculated by the user manually).
Rev. 0 | Page 69 of 88
ADV7342/ADV7343
+100 IRE
CRC SEQUENCE
REF
+70 IRE
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0 IRE
–40 IRE
06399-092
49.1µs ± 0.5µs
11.2µs
2.235µs ± 20ns
Figure 91. Standard Definition CGMS Waveform
CRC SEQUENCE
+700mV
REF
BIT 1 BIT 2
BIT 20
70% ± 10%
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV
–300mV
T = 1/(fH × 33) = 963ns
fH = HORIZONTAL SCAN FREQUENCY
T ± 30ns
06399-093
21.2µs ± 0.22µs
22T
5.8µs ± 0.15µs
6T
Figure 92. Enhanced Definition (525p) CGMS Waveform
R = RUN-IN
S = START CODE
PEAK WHITE
R
500mV ± 25mV
S
C0
LSB
C1
C2
C3
C4
SYNC LEVEL
C5
C6
C7
C8
C9
C10
C11 C12
C13
MSB
06399-094
13.7µs
5.5µs ± 0.125µs
Figure 93. Enhanced Definition (625p) CGMS Waveform
CRC SEQUENCE
+700mV
REF
70% ± 10%
BIT 1 BIT 2
C0
0mV
C2
C3
C4
C5
C6
C7
C8
C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
T ± 30ns
4T
3.128µs ± 90ns
17.2µs ± 160ns
22T
T = 1/(fH × 1650/58) = 781.93ns
fH = HORIZONTAL SCAN FREQUENCY
1H
Figure 94. High Definition (720p) CGMS Waveform
Rev. 0 | Page 70 of 88
06399-095
–300mV
C1
BIT 20
ADV7342/ADV7343
CRC SEQUENCE
+700mV
REF
BIT 1 BIT 2
70% ± 10%
C0
C1
0mV
C3
C4
C5
C6
C7
C8
C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
T ± 30ns
22.84µs ± 210ns
22T
T = 1/(fH × 2200/77) = 1.038µs
fH = HORIZONTAL SCAN FREQUENCY
1H
4T
4.15µs ± 60ns
06399-096
–300mV
C2
BIT 20
Figure 95. High Definition (1080i) CGMS Waveform
CRC SEQUENCE
+700mV
START
70% ± 10%
BIT 1 BIT 2
H0
H1
BIT 134
H2
H3
H4
H5
P0
P1
P2
P3
P4
.
.
.
P122 P123 P124 P125 P126 P127
0mV
06399-097
–300mV
NOTES
1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION.
Figure 96. Enhanced Definition (525p) CGMS Type B Waveform
CRC SEQUENCE
+700mV
70% ± 10%
START
BIT 1 BIT 2
H0
H1
BIT 134
H2
H3
H4
H5
P0
P1
P2
P3
P4
.
.
.
P122 P123 P124 P125 P126 P127
0mV
Figure 97. High Definition (720p and 1080i) CGMS Type B Waveform
Rev. 0 | Page 71 of 88
06399-098
–300mV
NOTES
1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION.
ADV7342/ADV7343
APPENDIX 2—SD WIDE SCREEN SIGNALING
(see Figure 98). The latter portion of Line 23 (after 42.5 μs from
the falling edge of HSYNC) is available for the insertion of
video. WSS data transmission on Line 23 can be enabled using
Subaddress 0x99, Bit 7. It is possible to blank the WSS portion
of Line 23 with Subaddress 0xA1, Bit 7.
Subaddress 0x99, Subaddress 0x9A, Subaddress 0x9B
The ADV7342/ADV7343 support wide screen signaling (WSS)
conforming to the ETSI 300 294 standard. WSS data is
transmitted on Line 23. WSS data can be transmitted only when
the device is configured in PAL mode. The WSS data is 14 bits
long. The function of each of these bits is shown in Table 55.
The WSS data is preceded by a run-in sequence and a start code
Table 55. Function of WSS
Bit Description
Aspect Ratio, Format, Position
13
12
11
10
9
Bit Number
8 7 6 5
Mode
4
3
1
0
0
1
0
1
1
0
2
0
0
0
0
1
1
1
1
0
1
Color Encoding
0
1
Helper Signals
0
1
Reserved
Teletext Subtitles
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
Setting
4:3, full format, N/A
14:9, letterbox, center
14:9, letterbox, top
16:9, letterbox, center
16:9, letterbox, top
>16:9, letterbox, center
14:9, full format, center
16:0, N/A, N/A
Camera mode
Film mode
Normal PAL
Motion Adaptive ColorPlus
Not present
Present
0
0
1
Open Subtitles
0
0
1
1
Surround Sound
No
Yes
No
Subtitles in active image area
Subtitles out of active image area
Reserved
No
Yes
No copyright asserted or unknown
Copyright asserted
Copying not restricted
Copying restricted
0
1
0
1
0
1
Copyright
0
1
Copy Protection
0
1
500mV
RUN-IN
SEQUENCE
START
CODE
W0
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10 W11 W12 W13
ACTIVE
VIDEO
11.0µs
06399-099
38.4µs
42.5µs
Figure 98. WSS Waveform Diagram
Rev. 0 | Page 72 of 88
ADV7342/ADV7343
APPENDIX 3—SD CLOSED CAPTIONING
and Line 284. All pixels inputs are ignored on Line 21 and Line
284 if closed captioning is enabled.
Subaddress 0x91 to Subaddress 0x94
The ADV7342/ADV7343 support closed captioning conforming
to the standard television synchronizing waveform for color
transmission. Closed captioning is transmitted during the
blanked active line time of Line 21 of the odd fields and
Line 284 of the even fields.
The FCC Code of Federal Regulations (CFR) 47 Section 15.119
and EIA608 describe the closed captioning information for
Line 21 and Line 284.
The ADV7342/ADV7343 use a single buffering method. This
means that the closed captioning buffer is only 1-byte deep.
Therefore, there is no frame delay in outputting the closed
captioning data, unlike other 2-byte deep buffering systems.
The data must be loaded one line before it is output on Line 21
and Line 284. A typical implementation of this method is to use
VSYNC to interrupt a microprocessor, which in turn loads the
new data (2 bytes) in every field. If no new data is required for
transmission, 0s must be inserted in both data registers; this is
called nulling. It is also important to load control codes, all of
which are double bytes, on Line 21. Otherwise, a TV does not
recognize them. If there is a message such as “Hello World”
that has an odd number of characters, it is important to add a
blank character at the end to make sure that the end-of-caption,
2-byte control code lands in the same field.
Closed captioning consists of a 7-cycle sinusoidal burst that is
frequency- and phase-locked to the caption data. After the clock
run-in signal, the blanking level is held for two data bits and is
followed by the Logic 1 start bit. Sixteen bits of data follow the
start bit. These consist of two 8-bit bytes, seven data bits, and one
odd parity bit. The data for these bytes is stored in the SD closed
captioning registers (Subaddress 0x93 to Subaddress 0x94).
The ADV7342/ADV7343 also support the extended closed
captioning operation, which is active during even fields and
encoded on Scan Line 284. The data for this operation is stored
in the SD closed captioning registers (Subaddress 0x91 to
Subaddress 0x92).
The ADV7342/ADV7343 automatically generate all clock runin signals and timing that support closed captioning on Line 21
10.5 ± 0.25µs
12.91µs
7 CYCLES OF
0.5035MHz
CLOCK RUN-IN
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
P
A
R
I
T
Y
S
T
A D0 TO D6
R
T
50 IRE
D0 TO D6
BYTE 0
40 IRE
P
A
R
I
T
Y
BYTE 1
10.003µs
27.382µs
33.764µs
Figure 99. SD Closed Captioning Waveform, NTSC
Rev. 0 | Page 73 of 88
06399-100
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = FSC = 3.579545MHz
AMPLITUDE = 40 IRE
ADV7342/ADV7343
APPENDIX 4—INTERNAL TEST PATTERN GENERATION
SD TEST PATTERNS
The ADV7342/ADV7343 are able to generate SD color bar and
black bar test patterns.
The register settings in Table 56 are used to generate an SD
NTSC 75% color bar test pattern. CVBS output is available on
DAC 4, S-Video (Y/C) output is on DAC 5 and DAC 6, and
YPrPb output is on DAC 1 to DAC 3. Upon power-up, the
subcarrier frequency registers default to the appropriate values
for NTSC. All other registers are set as normal/default.
Table 56. SD NTSC Color Bar Test Pattern Register Writes
Subaddress
0x00
0x82
0x84
To generate an SD NTSC black bar test pattern, the same
settings shown in Table 56 should be used with an additional
write of 0x24 to Subaddress 0x02.
For PAL output of either test pattern, the same settings are used,
except that Subaddress 0x80 is programmed to 0x11 and the
subcarrier frequency registers are programmed as shown in
Table 57.
Subaddress
0x8C
0x8D
0x8E
0x8F
Description
FSC0
FSC1
FSC2
FSC3
Setting
0xCB
0x8A
0x09
0x2A
ED/HD TEST PATTERNS
The ADV7342/ADV7343 are able to generate ED/HD color bar,
black bar, and hatch test patterns.
The register settings in Table 58 are used to generate an ED
525p hatch test pattern. YPrPb output is available on DAC 1 to
DAC 3. All other registers are set as normal/default.
Table 58. ED 525p Hatch Test Pattern Register Writes
Setting
0xFC
0xC9
0x40
Table 57. PAL FSC Register Writes
Note that when programming the FSC registers, the user must
write the values in the sequence FSC0, FSC1, FSC2, FSC3. The full
FSC value to be written is accepted only after the FSC3 write is
complete.
Subaddress
0x00
0x01
0x31
Setting
0x1C
0x10
0x05
To generate an ED 525p black bar test pattern, the same settings
as shown in Table 58 should be used with an additional write of
0x24 to Subaddress 0x02.
To generate an ED 525p flat field test pattern, the same settings
shown in Table 58 should be used, except that 0x0D should be
written to Subaddress 0x31.
The Y, Cr, and Cb levels for the hatch and flat field test patterns
can be controlled using Subaddress 0x36, Subaddress 0x37, and
Subaddress 0x38, respectively.
For ED/HD standards other than 525p, the same settings as
shown in Table 58 (and subsequent comments) are used except
that Subaddress 0x30, Bits[7:3] are updated as appropriate.
Rev. 0 | Page 74 of 88
ADV7342/ADV7343
APPENDIX 5—SD TIMING
Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = X X X X X 0 0 0)
The ADV7342/ADV7343 are controlled by the SAV (start of active video) and EAV (end of active video) time codes embedded in the
pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately
before and after each line during active picture and retrace. If the S_VSYNC and S_HSYNC pins are not used, they should be tied high
during this mode.
ANALOG
VIDEO
EAV CODE
SAV CODE
ANCILLARY DATA
(HANC)
4 CLOCK
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
PAL SYSTEM
(625 LINES/50Hz)
8 1 8 1 F 0 0 X C Y C Y C Y C Y C
b
r
b
0 0 0 0 F 0 0 Y b
r
0 F F A A A
0 F F B B B
4 CLOCK
268 CLOCK
4 CLOCK
4 CLOCK
280 CLOCK
1440 CLOCK
1440 CLOCK
06399-101
INPUT PIXELS
C
F 0 0 X 8 1 8 1
Y
Y
r
F 0 0 Y 0 0 0 0
START OF ACTIVE
VIDEO LINE
END OF ACTIVE
VIDEO LINE
Figure 100. SD Slave Mode 0
Mode 0 (CCIR-656)—Master Option (Subaddress 0x8A = X X X X X 0 0 1)
The ADV7342/ADV7343 generate H and F signals required for the SAV and EAV time codes in the CCIR656 standard. The H bit is
output on S_HSYNC and the F bit is output on S_VSYNC.
DISPLAY
522
523
DISPLAY
VERTICAL BLANK
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
H
EVEN FIELD
F
ODD FIELD
DISPLAY
260
261
DISPLAY
VERTICAL BLANK
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
F
ODD FIELD
06399-102
H
EVEN FIELD
Figure 101. SD Master Mode 0, NTSC
Rev. 0 | Page 75 of 88
ADV7342/ADV7343
DISPLAY
622
DISPLAY
VERTICAL BLANK
623
624
625
1
2
4
3
5
6
21
7
22
23
H
ODD FIELD
EVEN FIELD
F
DISPLAY
309
DISPLAY
VERTICAL BLANK
310
311
312
313
314
315
316
318
317
319
335
334
320
336
ODD FIELD
F
06399-103
H
EVEN FIELD
Figure 102. SD Master Mode 0, PAL
ANALOG
VIDEO
06399-104
H
F
Figure 103. SD Master Mode 0, Data Transitions
Mode 1—Slave Option (Subaddress 0x8A = X X X X X 0 1 0)
In this mode, the ADV7342/ADV7343 accept horizontal sync and odd/even field signals. When HSYNC is low, a transition of the field
input indicates a new frame, that is, vertical retrace. The ADV7342/ADV7343 automatically blank all normally blank lines as per CCIR624. HSYNC and FIELD are input on the S_HSYNC and S_VSYNC pins, respectively.
DISPLAY
522
523
DISPLAY
VERTICAL BLANK
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
HSYNC
FIELD
EVEN FIELD ODD FIELD
DISPLAY
260
261
DISPLAY
VERTICAL BLANK
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
FIELD
ODD FIELD
06399-105
HSYNC
EVEN FIELD
Figure 104. SD Slave Mode 1, NTSC
Rev. 0 | Page 76 of 88
ADV7342/ADV7343
DISPLAY
622
623
DISPLAY
VERTICAL BLANK
624
625
1
2
4
3
5
6
7
21
22
23
HSYNC
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
309
310
DISPLAY
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
ODD FIELD
FIELD
06399-106
HSYNC
EVEN FIELD
Figure 105. SD Slave Mode 1, PAL
Mode 1—Master Option (Subaddress 0x8A = X X X X X 0 1 1)
In this mode, the ADV7342/ADV7343 can generate horizontal sync and odd/even field signals. When HSYNC is low, a transition of the
field input indicates a new frame, that is, vertical retrace. The ADV7342/ADV7343 automatically blank all normally blank lines as per
CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions. HSYNC and FIELD are output on the
S_HSYNC and S_VSYNC pins, respectively.
HSYNC
FIELD
Cb
Y
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Cr
Y
06399-107
PIXEL
DATA
Figure 106. SD Timing Mode 1, Odd/Even Field Transitions (Master/Slave)
Mode 2— Slave Option (Subaddress 0x8A = X X X X X 1 0 0)
In this mode, the ADV7342/ADV7343 accept horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC
inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The
ADV7342/ADV7343 automatically blank all normally blank lines as per CCIR-624. HSYNC and VSYNC are input on the S_HSYNC and
S_VSYNC pins, respectively.
Rev. 0 | Page 77 of 88
ADV7342/ADV7343
DISPLAY
522
DISPLAY
VERTICAL BLANK
523
524
525
1
4
3
2
5
7
6
8
10
9
20
11
21
22
HSYNC
VSYNC
ODD FIELD
EVEN FIELD
DISPLAY
260
261
DISPLAY
VERTICAL BLANK
262
263
264
265
266
267
268
269
270
271
272
273
283
274
284
285
VSYNC
06399-108
HSYNC
EVEN FIELD
ODD FIELD
Figure 107. SD Slave Mode 2, NTSC
DISPLAY
622
623
DISPLAY
VERTICAL BLANK
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
309
310
DISPLAY
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
VSYNC
ODD FIELD
06399-109
HSYNC
EVEN FIELD
Figure 108. SD Slave Mode 2, PAL
Mode 2—Master Option (Subaddress 0x8A = X X X X X 1 0 1)
In this mode, the ADV7342/ADV7343 can generate horizontal and vertical sync signals. A coincident low transition of both HSYNC and
VSYNC inputs indicates the start of an odd field.
A VSYNC low transition when HSYNC is high indicates the start of an even field. The ADV7342/ADV7343 automatically blank all
normally blank lines as per CCIR-624. HSYNC and VSYNC are output on the S_HSYNC and S_VSYNC pins, respectively.
HSYNC
VSYNC
Cb
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 109. SD Timing Mode 2, Even-to-Odd Field Transition (Master/Slave)
Rev. 0 | Page 78 of 88
Y
Cr
Y
06399-110
PIXEL
DATA
ADV7342/ADV7343
HSYNC
VSYNC
PAL = 864 × CLOCK/2
NTSC = 858 × CLOCK/2
PIXEL
DATA
Cb
Y
Cr
Cb
06399-111
Y
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 110. SD Timing Mode 2 Odd-to-Even Field Transition (Master/Slave)
Mode 3—Master/Slave Option (Subaddress 0x8A = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode, the ADV7342/ADV7343 accept or generate horizontal sync and odd/even field signals. When HSYNC is high, a transition
of the field input indicates a new frame, that is, vertical retrace. The ADV7342/ADV7343 automatically blank all normally blank lines as
per CCIR-624. HSYNC and VSYNC are output in master mode and input in slave mode on the S_VSYNC and S_VSYNC pins,
respectively.
DISPLAY
522
523
DISPLAY
VERTICAL BLANK
524
525
1
2
4
3
5
6
7
8
9
10
20
11
21
22
HSYNC
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
260
DISPLAY
VERTICAL BLANK
261
262
263
264
265
266
267
268
269
270
271
272
273
283
274
285
284
FIELD
ODD FIELD
06399-112
HSYNC
EVEN FIELD
Figure 111. SD Timing Mode 3, NTSC
DISPLAY
622
623
DISPLAY
VERTICAL BLANK
624
625
1
2
3
4
5
6
21
7
22
23
HSYNC
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
309
310
DISPLAY
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
FIELD
EVEN FIELD
06399-113
HSYNC
ODD FIELD
Figure 112. SD Timing Mode 3, PAL
Rev. 0 | Page 79 of 88
ADV7342/ADV7343
APPENDIX 6—HD TIMING
DISPLAY
FIELD 1
VERTICAL BLANKING INTERVAL
1124
1125
1
2
3
4
5
6
7
8
20
21
22
560
P_VSYNC
P_HSYNC
DISPLAY
VERTICAL BLANKING INTERVAL
FIELD 2
561
562
563
564
565
566
567
568
569
570
583
584
585
1123
06399-114
P_VSYNC
P_HSYNC
Figure 113. 1080i HSYNC and VSYNC Input Timing
Rev. 0 | Page 80 of 88
ADV7342/ADV7343
APPENDIX 7—VIDEO OUTPUT LEVELS
SD YPrPb OUTPUT LEVELS—SMPTE/EBU N10
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
Pattern: 100% Color Bars
700mV
700mV
300mV
06399-115
06399-118
300mV
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
WHITE
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
YELLOW
Figure 117. Y Levels—PAL
Figure 114. Y Levels—NTSC
700mV
06399-116
06399-119
700mV
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
WHITE
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
YELLOW
Figure 118. Pr Levels—PAL
Figure 115. Pr Levels—NTSC
700mV
06399-117
06399-120
700mV
Figure 119. Pb Levels—PAL
Figure 116. Pb Levels—NTSC
Rev. 0 | Page 81 of 88
ADV7342/ADV7343
ED/HD YPrPb OUTPUT LEVELS
INPUT CODE
EIA-770.2, STANDARD FOR Y
INPUT CODE
OUTPUT VOLTAGE
EIA-770.3, STANDARD FOR Y
OUTPUT VOLTAGE
940
940
700mV
700mV
64
64
300mV
300mV
EIA-770.3, STANDARD FOR Pr/Pb
EIA-770.2, STANDARD FOR Pr/Pb
OUTPUT VOLTAGE
OUTPUT VOLTAGE
960
960
600mV
512
700mV
64
06399-123
700mV
64
06399-121
512
Figure 122. EIA-770.3 Standard Output Signals (1080i/720p)
Figure 120. EIA-770.2 Standard Output Signals (525p/625p)
INPUT CODE
INPUT CODE
EIA-770.1, STANDARD FOR Y
OUTPUT VOLTAGE
782mV
Y–OUTPUT LEVELS FOR
FULL INPUT SELECTION
OUTPUT VOLTAGE
1023
940
700mV
714mV
64
300mV
64
286mV
INPUT CODE
EIA-770.1, STANDARD FOR Pr/Pb
Pr/Pb–OUTPUT LEVELS FOR
FULL INPUT SELECTION
OUTPUT VOLTAGE
1023
OUTPUT VOLTAGE
960
700mV
512
700mV
06399-122
64
300mV
Figure 123. Output Levels for Full Input Selection
Figure 121. EIA-770.1 Standard Output Signals (525p/625p)
Rev. 0 | Page 82 of 88
06399-124
64
ADV7342/ADV7343
SD/ED/HD RGB OUTPUT LEVELS
Pattern: 100%/75% Color Bars
R
R
700mV/525mV
700mV/525mV
300mV
300mV
G
G
700mV/525mV
700mV/525mV
300mV
300mV
B
B
06399-125
300mV
300mV
06399-127
700mV/525mV
700mV/525mV
Figure 126. HD RGB Output Levels—RGB Sync Disabled
Figure 124. SD/ED RGB Output Levels—RGB Sync Disabled
R
R
700mV/525mV
600mV
700mV/525mV
300mV
300mV
0mV
0mV
G
G
700mV/525mV
600mV
700mV/525mV
300mV
300mV
0mV
0mV
B
B
700mV/525mV
600mV
700mV/525mV
06399-126
0mV
06399-128
300mV
300mV
0mV
Figure 127. HD RGB Output Levels—RGB Sync Enabled
Figure 125. SD/ED RGB Output Levels—RGB Sync Enabled
Rev. 0 | Page 83 of 88
ADV7342/ADV7343
SD OUTPUT PLOTS
VOLTS
VOLTS IRE:FLT
0.6
100
0.4
0.5
50
0.2
0
0
0
–0.2
F1
L76
L608
10
20
30
40
50
60
MICROSECONDS
NOISE REDUCTION: 0.00dB
APL = 39.1%
PRECISION MODE OFF
625 LINE NTSC NO FILTERING
SYNCHRONOUS SOUND-IN-SYNC OFF
SLOW CLAMP TO 0.00 AT 6.72µs
FRAMES SELECTED 1, 2, 3, 4
20
10
Figure 128. NTSC Color Bars (75%)
06399-132
30
40
50
60
MICROSECONDS
APL = 44.5%
PRECISION MODE OFF
525 LINE NTSC
SYNCHRONOUS SYNC = A
SLOW CLAMP TO 0.00V AT 6.72μs
µ
FRAMES SELECTED 1, 2
0
0
06399-129
–50
Figure 131. PAL Color Bars (75%)
VOLTS
VOLTS IRE:FLT
0.6
0.5
0.4
50
0.2
0
00
0
F2
L238
10
L575
20
30
40
50
60
MICROSECONDS
NOISE REDUCTION: 15.05dB
APL = 44.3%
PRECISION MODE OFF
525 LINE NTSC NO FILTERING
SYNCHRONOUS SYNC = SOURCE
SLOW CLAMP TO 0.00V AT 6.72μs
µ
FRAMES SELECTED 1, 2
0
10
20
30
40
50
60
70
MICROSECONDS
APL NEEDS SYNC SOURCE.
NO BUNCH SIGNAL
625 LINE PAL NO FILTERING
PRECISION MODE OFF
SLOW CLAMP TO 0.00 AT 6.72µs
SYNCHRONOUS SOUND-IN-SYNC OFF
FRAMES SELECTED 1
Figure 129. NTSC Luma
06399-133
–0.2
06399-130
0
Figure 132. PAL Luma
VOLTS IRE:FLT
0.4
50
VOLTS
0.5
0.2
0
0
0
–0.2
–50
–0.4
–0.5
F1
L76
L575
20
0
06399-131
10
30
40
50
60
MICROSECONDS
APL NEEDS SYNC SOURCE.
NO BUNCH SIGNAL
625 LINE PAL NO FILTERING
PRECISION MODE OFF
SLOW CLAMP TO 0.00 AT 6.72µs
SYNCHRONOUS SOUND-IN-SYNC OFF
FRAMES SELECTED 1
Figure 130. NTSC Chroma
10
20
Figure 133. PAL Chroma
Rev. 0 | Page 84 of 88
06399-134
30
40
50
60
MICROSECONDS
NOISE REDUCTION: 15.05dB
PRECISION MODE OFF
APL NEEDS SYNC SOURCE.
SYNCHRONOUS SYNC = B
525 LINE NTSC NO FILTERING
FRAMES SELECTED 1, 2
SLOW CLAMP TO 0.00 AT 6.72µs
0
ADV7342/ADV7343
APPENDIX 8—VIDEO STANDARDS
0HDATUM
SMPTE 274M
ANALOG WAVEFORM
DIGITAL HORIZONTAL BLANKING
*1
272T
4T
ANCILLARY DATA
(OPTIONAL) OR BLANKING CODE
EAV CODE
1920T
DIGITAL
ACTIVE LINE
F 0 0 F C
V b Y C
r
F 0 0 H*
0 0 F
0 0 V
H*
F
F
INPUT PIXELS
4T
SAV CODE
4 CLOCK
SAMPLE NUMBER
2112
C Y
r
4 CLOCK
0
2199
2116 2156
44
188
192
2111
06399-135
FVH* = FVH AND PARITY BITS
SAV/EAV: LINE 1–562: F = 0
SAV/EAV: LINE 563–1125: F = 1
SAV/EAV: LINE 1–20; 561–583; 1124–1125: V = 1
SAV/EAV: LINE 21–560; 584–1123: V = 0
FOR A FRAME RATE OF 30Hz: 40 SAMPLES
FOR A FRAME RATE OF 25Hz: 480 SAMPLES
Figure 134. EAV/SAV Input Data Timing Diagram (SMPTE 274M)
SMPTE 293M
ANALOG WAVEFORM
ANCILLARY DATA
(OPTIONAL)
EAV CODE
F
F 0 0 V
F 0 0 H*
INPUT PIXELS
F 0 0 F
V
F 0 0 H*
4 CLOCK
719
SAMPLE NUMBER
DIGITAL
ACTIVE LINE
SAV CODE
C
C
b Y r
C
Y r Y
4 CLOCK
723 736
0HDATUM
799
853
857 0
719
DIGITAL HORIZONTAL BLANKING
06399-136
FVH* = FVH AND PARITY BITS
SAV: LINE 43–525 = 200H
SAV: LINE 1–42 = 2AC
EAV: LINE 43–525 = 274H
EAV: LINE 1–42 = 2D8
Figure 135. EAV/SAV Input Data Timing Diagram (SMPTE293M)
522
523
524
ACTIVE
VIDEO
VERTICAL BLANK
525
1
2
5
6
7
8
9
12
13
Figure 136. SMPTE 293M (525p)
Rev. 0 | Page 85 of 88
14
15
16
42
43
44
06399-137
ACTIVE
VIDEO
ADV7342/ADV7343
622
623
ACTIVE
VIDEO
VERTICAL BLANK
624
625
1
2
5
4
6
7
8
9
10
12
11
13
43
44
45
06399-138
ACTIVE
VIDEO
Figure 137. ITU-R BT.1358 (625p)
DISPLAY
747
748
749
1
750
4
3
2
5
6
7
8
25
26
27
744
745
06399-139
VERTICAL BLANKING INTERVAL
Figure 138. SMPTE 296M (720p)
DISPLAY
VERTICAL BLANKING INTERVAL
FIELD 1
1124
1125
1
2
3
4
5
6
7
8
20
21
560
22
DISPLAY
VERTICAL BLANKING INTERVAL
561
562
563
564
565
566
567
568
569
Figure 139. SMPTE 274M (1080i)
Rev. 0 | Page 86 of 88
570
583
584
585
1123
06399-140
FIELD 2
ADV7342/ADV7343
OUTLINE DIMENSIONS
0.75
0.60
0.45
12.20
12.00 SQ
11.80
1.60
MAX
64
49
1
48
PIN 1
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
16
33
32
17
0.08
COPLANARITY
VIEW A
VIEW A
0.50
BSC
LEAD PITCH
ROTATED 90° CCW
0.27
0.22
0.17
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
051706-A
1.45
1.40
1.35
Figure 140. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADV7342BSTZ 2
ADV7343BSTZ2
EVAL-ADV7342EBZ2
EVAL-ADV7343EBZ2
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
Macrovision 1
Antitaping
Yes
No
Yes
No
Package Description
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
ADV7342 Evaluation Platform
ADV7343 Evaluation Platform
Package Option
ST-64-2
ST-64-2
Macrovision-enabled ICs require the buyer to be an approved licensee (authorized buyer) of ICs that are able to output Macrovision Rev 7.1.L1-compliant video.
Z = Pb-free part.
Rev. 0 | Page 87 of 88
ADV7342/ADV7343
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06399-0-10/06(0)
Rev. 0 | Page 88 of 88