FAIRCHILD ACE8000

ACE8001 Product Family
Arithmetic Controller Engine (ACEx™)
for Low Power Applications
■ Multi-input wake-up 3 I/O pins
■ 8-bit Timer1 with PWM output
■ On-chip oscillator
— No external components
— 1µs instruction cycle time
■ On-chip Power-on Reset
— External Reset pin option (ACE8000)
■ Brown-out Reset
■ Programmable read and write disable functions
■ Memory mapped I/O
■ Multilevel Low Voltage Detection
■ Fully static CMOS
— Low power HALT mode (100nA @ 3.3V)
— Power saving IDLE mode
■ Single supply operaton
— 2.2 - 5.5V
■ Software selectable I/O options
— Push-pull outputs with tri-state option
— Weak pull-up or high impedance inputs
■ 40 years data retention
■ 1,000,000 writes
■ 8-pin SOIC and TSSOP packages.
General Description
The ACE8001 is a member of the ACEx (Arithmetic Controller
Engine) family of microcontrollers. It is a dedicated programmable monolithic integrated circuit for applications requiring high
performance, low power, and small size. It is a fully static part
fabricated using CMOS technology.
The ACE8001 product family has an 8-bit core processor, 64
bytes of RAM, 64 bytes of data EEPROM and 1K bytes of code
EEPROM. Its on-chip peripherals include a programmable 8-bit
timer with PWM output, watch-dog/idle timer, and programmable undervoltage detection circuitry. The on-chip clock and reset
functions reduce the number of required external components.
The ACE8001 product family is available in 8-pin SOIC and
TSSOP packages.
Features
■
■
■
■
■
■
Arithmetic Controller Engine
1K bytes on-board code EEPROM
64 bytes data EEPROM
Fast Startup (<10µS)
64 bytes RAM
Watchdog
Block and Connection Diagram
VCC1
GND1
RESET
Power-on Reset
(CKO) G0
(CKI) G1
(T1) G2
(MIW) G3 2
(MIW) G4
(MIW) G5
GPORT
general
purpose
I/O with
multiinput
wakeup
on 3
inputs
Brown-out Reset
Internal Oscillator
HALT & IDLE Power
Saving Modes
ACE1001 core
12-bit Timer0 with
Watchdog Timer
(4 interrupt
sources
and vectors)
8-bit PWM Timer1
Programming Interface
64 bytes of Data
EEPROM
1K bytes of Code
EEPROM
64 bytes of RAM
1. 100nf decoupling capacitor recommended.
2. Input only
©2002 Fairchild Semiconductor Corporation
ACE8001 Product Family Rev. B.2
1
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
November 2002
(b) Programming Mode
(MIW) G3
1
8
VCC
LOAD
1
8
VCC
(MIW) G4
2
7
GND
SFT_IN
2
7
GND
(MIW) G5
(CKO) G0
3
6
3
6
SFT_OUT
5
G2 (T1)
G1 (CKI)
NC/VCC
4
NC
4
5
CKI
Figure 2: ACE8000 SOIC 8-Pin Reset Option
(a) Normal Operation
(b) Programming Mode
(MIW) G3
1
8
VCC
LOAD
1
8
VCC
(MIW) G4
2
7
GND
SFT_IN
2
7
GND
Reset
(CKO) G0
3
6
NC
3
6
SFT_OUT
4
5
G2 (T1)
G1 (CKI)
NC
4
5
CKI
Figure 3: ACE8001 TSSOP 8-Pin Device Pinout
(a) Normal Operation
VCC
1
8
G2 (T1)
(MIW) G3
2
7
GND
(MIW) G5
3
6
(MIW) G4
4
5
(b) Programming Mode
VCC
1
8
SFT_OUT
LOAD
2
7
GND
G1 (CKI)
NC/VCC
3
6
CKI
G0 (CKO)
SFT_IN
4
5
NC
2
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 1: ACE8001 SOIC 8-Pin Device Pinout
(a) Normal Operation
Absolute Maximum Ratings
Ambient Storage Temperature
Input Voltage not including G3
G3 Input Voltage
Lead Temperature (10s max)
Electrostatic Discharge on all pins
Operating Conditions
-65˚C to +150˚C
-0.3V to VCC+0.3V
0.3V to 13V
+300˚C
2000V min
Relative Humidity (non-condensing)
EEPROM write limits
95%
See DC Electrical
Characteristics
Device
Operating Voltage
Operating Temperature
ACE8001
2.2 to 5.5V
0°C to 70°C
ACE8001E
2.2 to 5.5V
-40°C to +85°C
ACE8000
2.2 to 5.5V
0°C to 70°C
ACE8000E
2.2 to 5.5V
-40°C to +85°C
3
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
2.0 Electrical Characteristics
VCC = 2.2 to 5.5V
All measurements valid for ambient operating temperature unless otherwise stated.
Symbol
ICC
3
Parameter
Conditions
MIN
TYP
MAX
Units
Supply Current –
no data EEPROM write in
progress
-40°C to +85°C
2.2V
2.7V
3.3V
5.5V
0.4
0.7
1.2
3.7
1.0
1.2
2.0
6.0
mA
mA
mA
mA
ICCH
HALT Mode current
3.3V @ -40°C to +85°C
100
5000
nA
5.5V @ -40°C to +85°C
0.7
25
µA
ICCL4
IDLE Mode Current
3.3V
5.5V
120
140
200
350
µA
µA
VCCW
EEPROM Write Voltage
Code EEPROM in
Programming Mode
4.5
5.0
5.5
V
Data EEPROM in
Operating Mode
2.4
5.5
V
1µs/V
10ms/V
SVCC
Power Supply Slope
VIL
Input Low with Schmitt
Trigger Buffer
VCC = 2.2 -5.5V
VIH
Input High with Schmitt
Trigger Buffer
VCC = 2.2V
VCC > 2.2V
IIP
Input Pull-up Current
VCC =5.5V, VIN =0V
ITL
TRI-STATE Leakage
VCC =5.5V
Output Low Voltage
VCC = 2.2V – 3.3V
G0, G1, G2, G4
VOL
VOH
0.2VCC
0.9VCC
0.8VCC
V
V
65
350
µA
2
200
nA
3.0 mA sink
0.2VCC
V
G5
5.0 mA sink
0.2VCC
V
Output Low Voltage
VCC = 3.3V – 5.5V
G0, G1, G2, G4
5.0 mA sink
0.2VCC
V
G5
10.0 mA sink
0.2VCC
V
Output High Voltage
VCC = 2.2V – 5.5V
G0, G1, G2, G4
0.4 mA source
0.8VCC
V
G5
0.8 mA source
0.8VCC
V
Output High Voltage
VCC = 3.3V – 5.5V
G0, G1, G2, G4
0.4 mA source
0.8VCC
V
G5
1.0 mA source
0.8VCC
V
3
ICC active current is dependent on the program code.
4
Based on a continuous IDLE looping program.
30
V
4
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
ACE8001 DC Electrical Characteristics
VCC = 2.2 to 5.5V
All measurements valid for ambient operating temperature unless otherwise stated.
Parameter
Conditions
Instruction cycle time from
internal clock - setpoint
5.0V at +25°C
Internal clock frequency
variation
2.4V to 5.5V at
constant temperature
2.4V to 5.5V at
full temperature range
MIN
TYP
MAX
Units
0.96
1.0
1.04
µs
10
%
+8
%
-12
Crystal oscillator frequency
(Note 5)
4
MHz
External clock frequency
(Note 5)
4
MHz
3
ms
20
µs
EEPROM write time
2.5
Internal clock start up time
(Note 6)
Oscillator start up time
(Note 6)
5 The
maximum permissible frequency is guaranteed by design but not 100% tested.
6 The
parameter is guaranteed by design but not 100% tested.
5
cycles
ACE8001 Electrical Characteristics for programming
All data following is valid between 4.5V and 5.5V at ambient temperature. The following characteristics are
guaranteed by design but are not 100% tested. See “EEPROM write time” in the AC Electrical Characteristics for definition of the programming ready time.
Parameter
Description
MIN
MAX
Units
tHI
CLOCK high time
500
DC
ns
tLO
CLOCK low time
500
DC
ns
tDIS
SHIFT_IN setup time
100
ns
tDIH
SHIFT_IN hold time
100
ns
tDOS
SHIFT_OUT setup time
100
ns
tDOH
SHIFT_OUT hold time
900
ns
tSV1, tSV2
LOAD supervoltage timing
50
µs
tLOAD1, tLOAD2, tLOAD3, tLOAD4
LOAD timing
5
µs
VSUPERVOLTAGE
Supervoltage level
11.5
12.5
V
ACE8001 Brown-out Reset (BOR) Characteristics
VCC = 2.2 to 5.5V
Parameter
BOR Voltage Threshold
Variation (BLSEL = 1)
Conditions
MIN
-40°C to +85°C
2.25
5
ACE8001 Product Family Rev. B.2
TYP
MAX
Units
V
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
ACE8001 AC Electrical Characteristics
The graphs in this section are for design guidance and are based on preliminary test data.
Figure 4: RC Oscillator Frequency vs. Temperature
Frequency (MHz)
(a) VCC = 5.0V
2.600
2.400
2.200
2.000
1.800
1.600
1.400
1.200
1.000
Avg
Min
Max
3.3k/82pF
5.6k/100pF
6.8K/100pF
Resistor & Capacitor Values [k & pF]
(b)VCC=2.5V
Frequency (MHz)
1.600
1.400
Avg
Min
Max
1.200
1.000
0.800
0.600
3.3k/82pF
5.6k/100pF
6.8K/100pF
Resistor & Capacitor Values [k & pF]
Figure 5: Internal Oscillator Frequency
1.040
1.020
Frequency (MHz)
1.000
2.4 V
3.0 V
3.3 V
3.6 V
4.0 V
4.5 V
5.0 V
5.5 V
0.980
0.960
0.940
0.920
0.900
0.880
-45C
-20C
0C
25C
85C
125C
Temperature (°C)
6
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
3.0 AC & DC Electrical Characteristic Graphs
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 6: LBD and BOR Threshold Levels
LBD Voltage Levels vs. Temperature
4.00
3.80
3.60
3.40
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Level 8
Voltage (V)
3.20
3.00
2.80
2.60
2.40
2.20
2.00
-45C
0C
25C
85C
125C
Temperature [°C]
BOR Voltage Level vs. Temperature
2.70
2.60
2.50
Voltage (V)
2.40
2.30
BOR Level
2.20
2.10
2.00
1.90
-45C
0C
25C
85C
125C
Temperature [°C]
7
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 7: ICC Active Current
ICC Active (no data EEPROM writes) vs. Temperature
4.50
4.00
3.50
Current (mA)
3.00
2.50
2.2V
2.7V
3.3V
5.0V
5.5V
2.00
1.50
1.00
0.50
0.00
-45
0
25
85
125
Temperature [°C]
ICC Active (data EEPROM writes) vs. Temperature
12.00
10.00
Current (mA)
8.00
2.2V
2.7V
3.3V
5.0V
5.5V
6.00
4.00
2.00
0.00
-45
0
25
85
125
Temperature [°C]
8
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 8: HALT Mode Currents
HALT current vs. Temperature
12.000
10.000
Current (nA)
8.000
5.5V
5.0V
3.3V
6.000
4.000
2.000
0.000
-45C
0C
25C
85C
125C
Temperature [°C]
Figure 9: IDLE Mode Current
IDLE current vs. Temperature
160.00
140.00
120.00
Current (µA)
100.00
2.2V
2.7V
3.3V
5.0V
5.5V
80.00
60.00
40.00
20.00
0.00
-45
0
25
85
125
Temperature [°C]
9
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
VOL vs. IOL (G5 @ 25°C)
VOL vs. IOL (G0-G4 @ 25°C)
0.80
1.40
0.70
1.20
1.00
Voltage (V)
Voltage (V)
0.60
0.50
2.2V
2.7V
0.40
0.30
0.80
2.2V
2.7V
3.3V
3.6V
5.5V
0.60
0.40
0.20
0.20
0.10
0.00
0.00
0
2
5
8
15
0
2
Current (mA)
5
8
15
Current (mA)
VOH vs. IOH (G0-G4 @ 25°C)
VOH vs. IOH (G5 @ 25°C)
6.00
6.00
5.50
5.50
5.00
5.00
4.50
4.50
Voltage (V)
4.00
3.50
2.2V
2.7V
3.00
2.50
2.00
4.00
2.2V
2.7V
3.3V
3.6V
5.5V
3.50
3.00
2.50
1.50
2.00
1.00
1.50
0.50
1.00
0.00
0
0.2
0.4
0.5
0.8
1
1.2
0
Current (mA)
0.4
0.5
0.8
1
1.2
Current (mA)
10
ACE8001 Product Family Rev. B.2
0.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 10: VOL/VOH
either segment of the memory map. This modification improves
the overall code efficiency of the core and takes advantage of
the flexibility found on Von Neumann style machines.
The ACEx microcontroller core is specifically designed for low
cost applications involving bit manipulation, shifting and arithmetic operations. It is based on a modified Harvard architecture
meaning peripheral, I/O, and RAM locations are addressed separately from instruction data.
4.1 CPU Registers
The ACEx microcontroller has five general-purpose registers.
These registers are the Accumulator (A), X-Pointer (X), Program Counter (PC), Stack Pointer (SP), and Status Register
(SR). The X, SP, and SR registers are all memory-mapped.
The core differs from the traditional Harvard architecture by
aligning the data and instruction memory sequentially. This
allows the X-pointer (11-bits) to point to any memory location in
Figure 11: Programming Model
7
A
0
8-bit accumulator register
X
10
0
11-bit X pointer register
PC
9
0
10-bit program counter
0
4-bit stack pointer
SP
SR
3
8-bit status register
R 0 0GZCHN
NEGATIVE flag
HALF CARRY flag (from bit 3)
CARRY flag (from MSB)
ZERO flag
GLOBAL Interrupt Mask
READY flag (from EEPROM)
11
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
4.0 Arithmetic Controller Core
The stack is configured as a data structure which decrements
from high to low memory. Each time a new address is pushed
onto the stack, the core decrements the stack pointer by two.
Each time an address is pulled from the stack, the core increments the stack pointer by two. At any given time, the stack
pointer points to the next free location in the stack.
The Accumulator is a general-purpose 8-bit register that is used
to hold data and results of arithmetic calculations or data manipulations.
4.1.2 X-Pointer (X)
When a subroutine is called by a jump to subroutine (JSR)
instruction, the address of the instruction is automatically
pushed onto the stack least significant byte first. When the subroutine is finished, a return from subroutine (RET) instruction is
executed. The RET instruction pulls the previously stacked
return address from the stack and loads it into the program
counter. Execution then continues at the recovered return
address.
The X-Pointer register allows for an 11-bit indexing value to be
added to an 8-bit offset creating an effective address used for
reading and writing between the entire memory space. (Software can only read from code EEPROM.) This provides software with the flexibility of storing lookup tables in the code
EEPROM memory space for the core’s accessibility during normal operation.
The X register is divided into two sections. The 10 least significant bits (LSB) of the register is the address of the program or
data memory space. The most significant bit (MSB) of the register is write only and selects between the data (0x000 to 0x0FF)
or program (0xC00 to 0xFFF) memory space.
4.1.5 Status Register (SR)
This 8-bit register contains four condition code indicators (C, H,
Z, and N), an interrupt masking bit (G), and an EEPROM write
flag (R). The condition code indicators are automatically
updated by most instructions. (See Table 8)
Example: If Bit 10 = 0, then the LD A, [00,X] instruction will take
a value from address range 0x000 to 0x0FF and load it into A. If
Bit 10 = 1, then the LD A, [00,X] instruction will take a value
from address range 0xC00 to 0xFFF and load it into A.
Carry/Borrow (C)
The 10-bit program counter register contains the address of the
next instruction to be executed. After a reset, if in normal mode
the program counter is initialized to 0xC00.
The carry flag is set if the arithmetic logic unit (ALU) performs a
carry or borrow during an arithmetic operation and by its dedicated instructions. The rotate instruction operates with and
through the carry bit to facilitate multiple-word shift operations.
The LDC and INVC instructions facilitate direct bit manipulation
using the carry flag.
4.1.4 Stack Pointer (SP)
Half Carry (H)
The ACEx microcontroller has an automatic program stack with
a 4-bit stack pointer. The stack can be initialized to any location
between addresses 0x30-0x3F. After a reset, the stack pointer
is defaulted to 0xF pointing to address 0x3F. Normally, the stack
pointer is initialized by one of the first instructions in an application program.
The half carry flag indicates whether an overflow has taken
place on the boundary between the two nibbles in the accumulator. It is primarily used for Binary Coded Decimal (BCD) arithmetic calculation.
4.1.3 Program Counter (PC)
Zero (Z)
The zero flag is set if the result of an arithmetic, logic, or data
manipulation operation is zero. Otherwise, it is cleared.
Interrupt Source with Priority
Figure 12: Basic Interrupt Structure
INTR
T1
T1PND
T0
T0PND
MIW
WKPND
Interrupt
Pending
Flags
Interrupt
T1EN
T0INT
EN
WKINT
EN
G
Global Interrupt
Enable
Interrupt Enable Bits
12
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
4.1.1 Accumulator (A)
stacked and the G bit is cleared. This means, if the G bit was
enabled prior to the software interrupt the RETI instruction must
be used to return from interrupt in order to restore the G bit to its
previous state. However, if the G bit was not enabled prior to the
software interrupt the RET instruction must be used.
The negative flag is set if the MSB of the result from an arithmetic, logic, or data manipulation operation is set to one. Otherwise, the flag is cleared. A result is said to be negative if its MSB
is a one.
In case of multiple interrupts occurring at the same time, the
ACEx microcontroller core has prioritized the interrupts. The
interrupt priority sequence in shown in Table 6.
Interrupt Mask (G)
The interrupt request mask (G) is a global mask that disables all
maskable interrupt sources. If the G Bit is cleared, interrupts
can become pending, but the operation of the core continues
uninterrupted. However, if the G Bit is set an interrupt is recognized. After any reset, the G bit is cleared by default and can
only be set by a software instruction. When an interrupt is recognized, the G bit is cleared after the PC is stacked and the
interrupt vector is fetched. Once the interrupt is serviced, a
return from interrupt instruction is normally executed to restore
the PC to the value that was present before the interrupt
occurred. The G bit is the reset to one after a return from interrupt is executed. Although the G bit can be set within an interrupt service routine, “nesting” interrupts in this way should only
be done when there is a clear understanding of latency and of
the arbitration mechanism.
4.3 Addressing Modes
The ACEx microcontroller has six addressing modes indexed,
direct, immediate, absolute jump, and relative jump.
Indexed
The instruction allows an 8-bit unsigned offset value to be
added to the 10-LSBs of the X-pointer yielding a new effective
address. This mode can be used to address any memory space
(program or data).
Direct
The instruction contains an 8-bit address field that directly
points to the data memory space as an operand.
4.2 Interrupt handling
Immediate
When an interrupt is recognized, the current instruction completes its execution. The return address (the current value in the
program counter) is pushed onto the stack and execution continues at the address specified by the unique interrupt vector
(see Table 9). This process takes five instruction cycles. At the
end of the interrupt service routine, a return from interrupt
(RETI) instruction is executed. The RETI instruction causes the
saved address to be pulled off the stack in reverse order. The G
bit is set and instruction execution resumes at the return
address.
The instruction contains an 8-bit immediate field as an operand.
Inherent
This instruction has no operands associated with it.
Absolute
The instruction contains a 10-bit address that directly points to a
location in the program memory space. There are two operands
associated with this addressing mode. Each operand contains a
byte of an address. This mode is used only for the long jump
(JMP) and JSR instructions.
The ACEx microcontroller is capable of supporting four interrupts. Three are maskable through the G bit of the SR and the
fourth (software interrupt) is not inhibited by the G bit (see Figure 12). The software interrupt is generated by the execution of
the INTR instruction. Once the INTR instruction is executed, the
ACEx core will interrupt whether the G bit is set or not. The
INTR interrupt is executed in the same manner as the other
maskable interrupts where the program counter register is
Relative
This mode is used for the short jump (JP) instructions where the
operand is a value relative to the current PC address. With this
instruction, software is limited to the number of bytes it can
jump, -31 or +32.
Table 6: Interrupt Priority Sequence
Priority (4 highest, 1 lowest)
Interrupt
4
MIW (EDGEI)
3
Timer0 (TMRI0)
2
Timer1 (TMRI1)
1
Software (INTR)
13
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Negative (N)
Instruction
Immediate
Direct
A, #
A, #
A, #
A, #
A, M
A, M
A, M
A, M
ADC
AND
SUBC
XOR
CLR
INC
DEC
IFEQ
IFGT
IFNE
Indexed
M
M
M
A, #
A, #
A, #
M,#
A
A
A
Relative
Absolute
X
X
A, M
A, M
A, M
SC
RC
IFC
IFNC
INVC
LDC
STC
no-op
no-op
no-op
no-op
no-op
#, M
#, M
RLC
RRC
LD
ST
LD
Inherent
A
A
A, #
M, #
X, #
A, M
A, M
M, M
A, [00,X]
A, [00,X]
NOP
IFBIT
SBIT
RBIT
no-op
#, M
#, M
#, M
JP
JSR
JMP
RET
RETI
INTR
Rel
M
M
no-op
no-op
no-op
14
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Table 7: Instruction Addressing Modes
Mnemonic
Operand
Bytes
Cycles
Flags
affected
Mnemonic
Operand
Flags
affected
Bytes
Cycles
1
1
None
ADC
A, #
2
2
C,H,Z,N
JP
ADC
A, M
2
2
C,H,Z,N
JSR
M
3
5
None
AND
A, #
2
2
Z,N
LD
A, #
2
2
None
AND
A, M
2
2
Z,N
LD
A, [00,X]
2
3
None
CLR
A
1
1
Z,N,C,H
LD
A, M
2
2
None
CLR
M
2
1
Z,N,C,H
LD
M, #
3
3
None
DEC
A
1
1
Z,N
LD
M, M
3
3
None
DEC
M
2
2
Z,N
LD
X, #
3
3
None
DEC
X
1
1
Z
LDC
#, M
2
2
C
IFBIT
#, M
2
2
None
NOP
1
1
None
1
1
None
RBIT
#, M
2
2
Z,N
IFC
IFEQ
A, #
2
2
None
RC
1
1
C,H
IFEQ
A, M
2
2
None
RET
1
5
None
IFEQ
M, #
3
3
None
RETI
1
5
None
IFGT
A, #
2
2
None
RLC
A
1
1
C,Z,N
IFGT
A, M
2
2
None
RRC
A
1
1
C,Z,N
IFNE
A, #
2
2
None
SBIT
#, M
2
2
Z,N
IFNE
A, M
2
2
None
SC
1
1
C,H
1
1
None
ST
A, [00,X]
2
3
None
IFNC
INC
A
1
1
Z,N
ST
A, M
2
2
None
INC
M
2
2
Z,N
STC
#, M
2
2
Z,N
INC
X
INTR
INVC
JMP
M
1
1
Z
SUBC
A, #
2
2
C,H,Z,N
1
5
None
SUBC
A, M
2
2
C,H,Z,N
1
1
C
XOR
A, #
2
2
Z,N
3
4
None
XOR
A, M
2
2
Z,N
15
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Table 8: Instruction Cycles and Bytes
All I/O ports, peripheral registers and core registers (except the accumulator and the program counter) are mapped into memory
space.
Table 9: Memory Map
Memory Space
Block
0x00 - 0x3F
Address
Data
SRAM
0x40 - 0x7F
Data
EEPROM
Data EEPROM
0xAA
Data
Timer1
T1RA register
0xAC
Data
Timer1
TMR1 register
0xAE
Data
Timer1
T1CNTRL register
0xAF
Data
MIW
WKEDG register
0xB0
Data
MIW
WKPND register
0xB1
Data
MIW
WKEN register
0xB2
Data
I/O
PORTGD register
0xB3
Data
I/O
PORTGC register
0xB4
Data
I/O
PORTGP register
0xB5
Data
Timer0
WDSVR register
0xB6
Data
Timer0
0xB7
Data
Clock
0xBB
Data
Init. Reg.
Initialization register 1
0xBC
Data
Init. Reg.
Initialization register 2
0xBD
Data
LBD
LBD register
0xBE
Data
Core
XHI register
0xBF
Data
Core
XLO register
0xC0
Data
Clock
Power mode clear (PMC) register
0xCE
Data
Core
SP register
0xAB, 0xAD
Reserved
0xB8 - 0xBA
0xCF
Contents
Data RAM
T0CNTRL register
HALT mode register
Reserved
Data
Core
0xC00 - 0xFF5
Program
EEPROM
0xFF6 - 0xFF7
Program
Core
Timer0 Interrupt vector
0xFF8 - 0xFF9
Program
Core
Timer1 Interrupt vector
0xFFA - 0xFFB
Program
Core
MIW Interrupt vector
0xFFC - 0xFFD
Program
Core
Soft Interrupt vector
0xFFE - 0xFFF
Reserved
16
ACE8001 Product Family Rev. B.2
Status register (SR)
Code EEPROM
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
4.4 Memory Map
4.6 Initialization Registers
The ACEx microcontroller device has 64 bytes of SRAM and 64
bytes of EEPROM available for data storage. The device also
has 1K bytes of EEPROM for program storage. Software can
read and write to SRAM and data EEPROM but can only read
from the code EEPROM. While in normal mode, the code
EEPROM is protected from any writes. The code EEPROM can
only be rewritten when the device is in program mode and if the
write disable (WDIS) bit of the initialization register is not set to
1.
The ACEx microcontroller has two 8-bit wide initialization registers. These registers are read from the memory space on
power-up to initialize certain on-chip peripherals. Figure 13 provides a detailed description of Initialization Register 1. The Initialization Register 2 is used to trim the internal oscillator to its
appropriate frequency. This register is pre-programmed in the
factory to yield an internal instruction clock of 1MHz.
Both Initialization Registers 1 and 2 can be read from and written to during programming mode. However, re-trimming the
internal oscillator (writing to the Initialization Register 2) once it
has left the factory is discouraged.
While in normal mode, the user can write to the data EEPROM
array by 1) polling the ready (R) flag of the SR, then 2) executing the appropriate instruction. If the R flag is 1, the data
EEPROM block is ready to perform the next write. If the R flag is
0, the data EEPROM is busy. The data EEPROM array will reset
the R flag after the completion of a write cycle. Attempts to read,
write, or enter HALT/IDLE mode while the data EEPROM is
busy (R = 0) can affect the current data being written.
Figure 13: Initialization Register 1
Bit 7
Bit 6
CMODE[0:1]
(0) RDIS 8,9
(1) WDIS 8,9
(2) UBD 8,9
(3) BLSEL 7
(4) BOREN
(5) WDEN
(6) CMODE[1]
(7) CMODE[0]
7 The
Bit 5
WDEN
Bit 4
Bit 3
BOREN
BLSEL
Bit 2
7
UBD
8,9
Bit 1
WDIS
8,9
Bit 0
RDIS 8,9
If set, disables attempts to read the contents from the EEPROMs while in programming mode
If set, disables attempts to write new contents to the EEPROMs while in programming mode
If set, the device will not allow any writes to occur in the upper block of data EEPROM (0x60-0x7F)
If set, the Brown-out Reset (BOR) voltage reference level is set to its higher range for the ACE8001
If not set, the BOR voltage reference level is set to its lower range
If set, allows a BOR to occur if VCC falls below the voltage reference level
If set, enables the on-chip processor watchdog circuit
Clock mode select bit 1 (See table 13)
Clock mode select bit 0 (See table 13)
BLSEL bit is set to its appropriate level in the factory. If writing to the initialization register is necessary, be sure to maintain bits set value.
8 If
both the WDIS and RDIS bits are set, the device will no longer be able to be placed into program mode.
9 If
the RDIS or UBD bits are not set while the WDIS bit is not set, then the RDIS and UBD bits can be reset.
17
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
4.5 Memory
timer underflow (transitions from 0x00 to 0xFF or reload) can
either generate an interrupt and/or toggle the T1 output pin.
Timer 1 is a versatile 8-bit timer. Its main function is to operate
as a Pulse Width Modulation (PWM) generator that generates
pulses of a specified width and duty cycles.
Timer 1’s interrupt (TMRI1) can be enabled by the interrupt
enable (T1EN) bit in the T1CNTRL register. When the timer
interrupt is enabled, the source of the interrupt is a timer underflow. By default, the timer register is reset to 0xFF and the autoreload register is reset to 0x00.
Timer 1 contains an 8-bit timer register (TMR1), an 8-bit autoreload register (T1RA), and an 8-bit control register
(T1CNTRL). All registers are memory-mapped for simple
access through the core. For the PWM signal generation the
timer contains an output (T1) that is multiplexed with the I/O pin
G2.
5.1 Timer control bits
Reading and writing to the T1CNTRL register controls the
timer’s operation. By writing to the control bits, the user can
enable or disable the timer interrupts, set the mode of operation,
start or stop the timer, and select the clock. The T1CNTRL register bits are described in Table 10.
The timer can be started or stopped through the T1CNTRL register bit T1C0. When running, the timer counts down (decrements) every clock cycle. The timer’s clock has a pre-scalar and
is selectable through two T1CNTRL register bits T1PSC[1:0].
Depending on the selected operating mode, occurrences of
Table 10: TIMER1 Control Register Bits
T1CNTRL Register
Name
Function
Bit 7
-----------
Reserved
Bit 6
-----------
Reserved
Bit 5
T1C1
T1 toggle enable bit: 1 = T1 toggle enabled, 0 = T1 toggle disabled
Bit 4
T1C0
TMR1 run: 1 = Start timer, 0 = Stop timer
Bit 3
T1PND
Bit 2
T1EN
Bit 1,0
T1PSC
Timer1 interrupt pending flag: 1 = Timer1 interrupt
pending, 0 = Timer1 interrupt not pending
Timer1 interrupt enable bit: 1 = Timer1 interrupt enabled,
0 = Timer1 interrupt disabled
Pre-scalar selection bits: Selects the 1MHz clock divider to be by 1 (00b),
2 (01b), 4 (10b), or 8 (11b)
18
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
5.0 Timer 1
1. Configure T1 as an output by setting bit 2 of PORTGC.
- SBIT 2, PORTGC
; Configure G2 as an output
In the PWM mode, the timer counts down at the instruction
clock rate. When an underflow occurs, the timer register is
reloaded from T1RA and the count down proceeds from the
loaded value. At every underflow, a pending flag (T1PND)
located in the T1CNTRL register is set. Software must then
clear the T1PND flag and load the T1RA register with an alternate PWM value. In addition, the timer can be configured to toggle the T1 output bit upon underflow. Configuring the timer to
toggle T1 results in the generation of a signal outputted from
port G2 with the width and duty cycle controlled by the values
stored in the T1RA. A block diagram of the timer’s PWM mode
of operation is shown in Figure 14.
2. Initialize T1 to 1 (or 0) by setting (or clearing) bit 2 of
PORTGD.
- SBIT 2, PORTGD
; Set G2 high
3. Load the initial PWM high (low) time into the timer register.
- LD TMR1, #6FH
; High (Low) for .444ms
(1MHz/4 clock)
4. Load the PWM low (high) time into the T1RA register.
- LD T1RA, #2FH
; Low (High) for .188ms
(1MHz/4 clock)
5. Write the appropriate control value to the T1CNTRL register
to select PWM mode with T1 toggle, to select the divide by 4
pre-scalar, and to clear the enable and pending flags. (See
Table 12)
- LD T1CNTRL, #22H
; Setting the T1C0 bit starts
the timer
The timer has one interrupt (TMRI1) that is maskable through
the T1EN bit of the T1CNTRL register. However, the core is only
interrupted if the T1EN bit and the G (Global Interrupt enable)
bit of the SR is set. If interrupts are enabled, the timer will generate an interrupt each time T1PND flags is set (whenever the
timer underflows provided that the pending flag was cleared.)
The interrupt service routine is responsible for proper handling
of the T1PND flag and the T1EN bit.
6. Set the T1CO bit to start the timer.
- SBIT T1CP, T1CNTRL
; T1CO equals 4
7. After every underflow, load T1RA with alternate values. If the
user wishes to generate an interrupt on timer output transitions, reset the pending flags and then enable the interrupt
using T1EN. The G bit must also be set. The interrupt service routine must reset the pending flag and perform whatever processing is desired.
- RBIT T1PND, T1CNTRL ; T1PND equals 3
- LD T1RA, #6FH
; Low for .444ms
(1MHz/4 clock)
The interrupt will be synchronous with every rising and falling
edge of the T1 output signal. Generating interrupts only on rising or falling edges of T1 is achievable through appropriate handling of the T1EN bit or T1PND flag through software.
The following steps show how to properly configure Timer 1 to
operate in the PWM mode. For this example, the T1 output signal is toggled with every timer underflow and the “high” and
“low” times for the T1 output can be set to different values. The
T1 output signal can start out either high or low depending on
the configuration of I/O G2; the instructions below are for starting with the T1 output high. Follow the instructions in parentheses to start the T1 output low.
Figure 14: Pulse Width Modulation Mode
Underflow
Interrupt
8-bit Auto-Reload
Register (T1RA)
Data
Latch
T1
Data
Bus
Instruction
Clock
÷8
3
÷4
2
÷2
1
8-bit Timer
(TMR1)
0
Sel
T1PSC[1:0]
19
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
5.2 Pulse Width Modulation (PWM) Mode
The WKINTEN bit is used in the Multi-input Wakeup/Interrupt
block. See Section 8.0 for details.
Timer 0 is a 12-bit free running idle timer. Upon power-up or any
reset, the timer is reset to 0x000 and then counts up continuously based on the instruction clock of 1MHz (1 µs). Software
cannot read from or write to this timer. However, software can
monitor the timer’s pending (T0PND) bit that is set every 8192
cycles (initially 4096 cycles after a reset or after the watchdog
has been- serviced). The T0PND flag is set every other time the
timer overflows (transitions from 0xFFF to 0x000). After an overflow, the timer will reset and restart its counting sequence.
7.0 Watchdog
The Watchdog timer is used to reset the device and safely
recover in the rare event of a processor “runaway condition.”
The 12-bit Timer 0 is used as a pre-scalar for Watchdog timer.
The Watchdog timer must be serviced before every 61,440
cycles but no sooner than 4096 cycles since the last Watchdog
reset. The Watchdog is serviced through software by writing the
value 0x1B to the Watchdog Service (WDSVR) register (see
Figure 16). The part resets automatically if the Watchdog is serviced too frequent, or not frequent enough.
Software can either poll the T0PND bit or vector to an interrupt
subroutine. In order to interrupt on a T0PND, software must be
sure to enable the Timer 0 interrupt enable (T0INTEN) bit in the
Timer 0 control (T0CNTRL) register and also make sure the G
bit is set in SR. Once the timer interrupt is serviced, software
should reset the T0PND bit before exiting the routine. Timer 0
supports the following functions:
2. Start up delay from HALT mode
The Watchdog timer must be enabled through the Watchdog
enable bit (WDEN) in the initialization register. The WDEN bit
can only be set while the device is in programming mode. Once
set, the Watchdog will always be powered-up enabled. Software
cannot disable the Watchdog. The Watchdog timer can only be
disabled in programming mode by resetting the WDEN bit as
long as the memory write protect (WDIS) feature is not enabled.
3. Watchdog pre-scalar (See Section 7.0 for details.)
WARNING
The T0INTEN bit is a read/write bit. If set to 0, interrupt requests
from the Timer 0 are ignored. If set to 1, interrupt requests are
accepted. Upon reset, the T0INTEN bit is reset to 0.
Ensure that the Watchdog timer has been serviced before
entering IDLE mode because it remains operational during this
time.
1. Exiting from IDLE mode (See Section 16.0 for details.)
The T0PND bit is a read/write bit. If set to 1, it indicates that a
Timer 0 interrupt is pending. This bit is set by a Timer 0 overflow
and is reset by software or system reset.
Figure 15: Timer 0 Control Register Definition (T0CNTRL)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WKINTEN
x
x
x
x
x
T0PND
T0EN
Figure 16: Watchdog Server Register (WDSVR)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
1
0
1
1
20
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
6.0 Timer 0
6. Set the WKEN bits associated with the pins to be used, thus
enabling those pins for the Wakeup/Interrupt function.
-LD WKEN, #38H
;Enabling G3, G4, G5
The Multi-Input Wakeup (MIW)/Interrupt contains three memory-mapped registers associated with this circuit: WKEDG
(Wakeup Edge), WKEN (Wakeup Enable), and WKPND
(Wakeup Pending). Each register has three bits with each bit
corresponding to an input pins as shown in Figure 17. All three
registers are initialized to zero upon reset.
Once the Multi-Input Wakeup/Interrupt function has been configured, a transition sensed on any of the enabled pins will set the
corresponding bit in the WKPND register. The WKPND bits can
bring the device out of the HALT/IDLE mode and can also trigger
an interrupt if the interrupt is enabled. The interrupt service routine
can read the WKPND register to determine which pin sensed the
interrupt.
The WKEDG register establishes the edge sensitivity for each
of the wake-up input pin: either (0) rising edge or (1) falling
edge.
The interrupt service routine or other software should clear the
pending bit. The device will not enter HALT/IDLE mode as long as
a WKPND pending bit is pending and enabled. The user has the
responsibility of clearing the pending flags before attempting to
enter the HALT/IDLE mode.
The WKEN register enables (1) or disables (0) each of the port
pins for the Wakeup/Interrupt function. The wakeup I/Os used
for the Wakeup/Interrupt function must also be configured as an
input pin in its associated port configuration register. However,
an interrupt (EDGE1) of the core will not occur unless interrupts
are enabled for the block via bit 7 of the T0CNTRL register (see
Figure 15) and the G (global interrupt enable) bit of the SR is
set.
Upon reset, the WKEDG register is configured to select positivegoing edge sensitivity for all wakeup inputs. If the user wishes to
change the edge sensitivity of a port pin, use the following procedure to avoid false triggering of a Wakeup/Interrupt condition.
The WKPND register contains the pending flags corresponding
to each of the port pins (1 for wakeup/interrupt pending, 0 for
wakeup/interrupt not pending).
1. Clear the WKEN bit associated with the pin to disable that pin.
2. Write the WKEDG register to select the new type of edge sensitivity for the pin.
To use the Multi-Input Wakeup/Interrupt circuit, perform the
steps listed below. Performing the steps in the order shown will
prevent false triggering of a Wakeup/Interrupt condition. This
same procedure should be used following any type of reset
because the wakeup inputs are left floating after resets resulting
in unknown data on the port inputs.
3. Clear the WKPND bit associated with the pin.
4. Set the WKEN bit associated with the pin to re-enable it.
PORTG provides the user with three fully selectable, edge sensitive interrupts that are all vectored into the same service subroutine. The interrupt from PORTG shares logic with the wakeup
circuitry. The WKEN register allows interrupts from PORTG to be
individually enabled or disabled. The WKEDG register specifies the
trigger condition to be either a positive or a negative edge. The
WKPND register latches in the pending trigger conditions.
1. Clear the WKEN register.
-CLR WKEN
2. If necessary, write to the port configuration register to select
the desired port pins to be configured as inputs.
-RBIT 4, PORTGC
;G3, G4, and/or G5
Since PORTG is also used for exiting the device from the HALT/
IDLE mode, the user can elect to exit the HALT/IDLE mode either
with or without the interrupt enabled. If the user elects to disable
the interrupt, then the device restarts execution from the point at
which it was stopped (first instruction cycle of the instruction following HALT/IDLE mode entrance instruction). In the other case, the
device finishes the instruction that was being executed when the
part was stopped and then branches to the interrupt service routine. The device then reverts to normal operation.
3. If necessary, write to the port data register to select the
desired port pins input state.
-SBIT 4, PORTGD
;Pull-up
4. Write the WKEDG register to select the desired type of edge
sensitivity for each of the pins used.
-LD WKEDG, #38H
;Falling edges
5. Clear the WKPND register to cancel any pending bits.
-CLR WKPND
Figure 17: MIW Register Bit Assignments
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
x
x
G5
G4
G3
x
x
x
Figure 18: Multi-input Wakeup (MIW) Block Diagram
Data Bus
5
3
WKEN[5:3]
G3
3
WKOUT
G4
4
EDGEI
G5
5
WKEDG[3:5]
10
4
WKPND[3:5]
WKINTEN 10
WKINTEN: Bit 7 of T0CNTR
21
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
8.0 Multi-Input Wakeup/Interrupt Block
ter (PORTGC), a port data register (PORTGD), and a port input
register (PORTGP). PORTGC is used to configure the pins as
inputs or outputs. A pin may be configured as an input by writing
a 0 or as an output by writing a 1 to its corresponding PORTGC
bit. If a pin is configured as an output, its PORTGD bit represents the state of the pin (1 = logic high, 0 = logic low). If the pin
is configured as an input, its PORTGD bit selects whether the
pin is a weak pull-up or a high-impedence input. Table 11 provides details of the port configuration options. The port configuration and data registers are both read/writable. Reading
PORTGP returns the value of the port pins regardless of how
the pins are configured. Since this device supports multi-input
wakeup/interrupt, the PORTG inputs have Schmitt triggers.
The six I/O pins are bi-directional with the exception of G3
which is always an input with weak pull-up (see Figure 19). The
bi-directional I/O pins can be individually configured by software
to operate as high-impedance inputs, as inputs with weak pullup, or as push-pull outputs. The operating state is determined
by the contents of the corresponding bits in the data and configuration registers. Each bi-directional I/O pin can be used for
general purpose I/O, or in some cases, for a specific alternate
function determined by the on-chip hardware.
9.1 I/O registers
The I/O pins (G0-G5) have three memory-mapped port registers associated with the I/O circuitry: a port configuration regis-
Figure 19: PORTGD Logic Diagram
Weak Pull-up Control
PORTGC
PIN GX
PORTGD
PORTGP
Figure 20: I/O Register bit assignments
Bit 7
x
Bit 6
Bit 5
x
G512
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
G4
G311
G2
G1
G0
Table 11: I/O configuration options
Configuration Bit
Data Bit
Port Pin Configuration
0
0
High-impedence input (TRI-STATE input)
0
1
Input with pull-up (weak one input)
1
0
Push-pull zero output
1
1
Push-pull one output
11G3
is only an input
12G5
is not available on SOIC-8 package with the reset pin option (ACE8000)
22
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
9.0 I/O Port
programmer has sent the second rising edge during the LOAD
= 0V phase (if the timing specifications in Figure 21 are
obeyed).
The ACEx microcontroller supports in-circuit programming of
the internal data EEPROM, code EEPROM, and the initialization registers.
The device will set the R bit of the Status register when the write
operation has completed. The external programmer must wait
for the SHIFT_OUT pin to go high before bringing the LOAD signal to 5V to initiate a normal command cycle.
An externally controlled four wire interface consisting of a LOAD
control pin (G3), a serial data SHIFT-IN input pin (G4), a serial
data SHIFT-OUT output pin (G2), and a CLOCK pin (G1) is
used to access the on-chip memory locations. Communication
between the ACEx microcontroller and the external programmer
is made through a 32-bit command and response word
described in Table 12.
10.2 Read Sequence
When reading the device after a write, the external programmer
must set the LOAD signal to 5V before it sends the new command word. Next, the 32-bit serial command word (for during a
READ) should be shifted into the device using the SHIFT_IN
and the CLOCK signals while the data from the previous command is serially shifted out on the SHIFT_OUT pin. After the
Read command has been shifted into the device, the external
programmer must, once again, set the LOAD signal to 0V and
apply two clock pulses as shown in Figure 21 to complete
READ cycle. Data from the selected memory location, will be
latched into the lower 8 bits of the command word shortly after
the second rising edge of the CLOCK signal.
The serial data timing for the four-wire interface is shown in Figure 22 and the programming protocol is shown in Figure 21.
10.1 Write Sequence
The external programmer brings the ACEx microcontroller into
programming mode by applying a super voltage level to the
LOAD pin. The external programmer then needs to set the
LOAD pin to 5V before shifting in the 32-bit serial command
word using the SHIFT_IN and CLOCK signals. By definition, bit
31 of the command word is shifted in first. At the same time, the
ACEx microcontroller shifts out the 32-bit serial response to the
last command on the SHIFT_OUT pin. It is recommended that
the external programmer samples this signal tACCESS (1µs) after
the rising edge of the CLOCK signal. The serial response word,
sent immediately after entering programming mode, contains
indeterminate data.
Writing a series of bytes to the device is achieved by sending a
series of Write command words while observing the devices
handshaking requirements.
Reading a series of bytes from the device is achieved by sending a series of Read command words with the desired
addresses in sequence and reading the following response
words to verify the correct address and data contents.
After 32 bits have been shifted into the device, the external programmer must set the LOAD signal to 0V, and then apply two
clock pulses as shown in Figure 21 to complete program cycle.
The SHIFT_OUT pin acts as the handshaking signal between
the device and programming hardware once the LOAD signal is
brought low. The device sets SHIFT_OUT low by the time the
The addresses of the data EEPROM and code EEPROM locations are the same as those used in normal operation.
Powering down the device will cause the part to exit programming mode.
Table 12: 32-Bit Command and Response Word
Bit number
Input command word
Output response word
bits 31 – 30
Must be set to 0
X
bit 29
Set to 1 to read/write data EEPROM, or the initializa- X
tion registers, otherwise 0
bit 28
Set to 1 to read/write code EEPROM, otherwise 0
X
bits 27 – 25
Must be set to 0
X
bit 24
Set to 1 to read, 0 to write
X
bits 23 – 18
Must be set to 0
X
bits 17 – 8
Address of the byte to be read or written
Same as Input command word
bits 7 – 0
Data to be programmed or zero if data is to be read
Programmed data or data read at specified address
13
Application Note reference: “How to In-Circuit Program the ACEx Family of Microcontrollers.”
14
During in-circuit programming, G5 must be either not connected or driven high.
23
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
10.0 In-circuit Programming Specification13,14
tSV1
A
tSV2
A
tload1 tload2
LOAD (G3)
enter prog.
mode
tready
tload3
tload4
32 clock pulses
CLOCK (G1)
SHIFT_IN (G4)
bit 31
bit 30
bit 0
bit 31
BUSY low by
2nd clock pulse
SHIFT_OUT (G2)
(in write mode)
READY
BUSY
SHIFT_OUT (G2)
(in read mode)
A: start of programming cycle
Figure 22: Serial Data Timing
tLO
tHI
CLOCK (G1)
tDIS
SHIFT_IN (G4)
tDIH
Valid
tDOS
tDOH
Valid
SHIFT_OUT (G2)
tACCESS
24
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 21: Programming Protocol13
BOR will always be powered-up enabled. Software cannot disable the BOR. The BOR can only be disabled in programming
mode by resetting the BOREN bit as long as the global write
protect (WDIS) feature is not enabled.
The Brown-out Reset (BOR) and Low Battery Detect (LBD) circuits on the ACEx microcontroller have been designed to offer
two types of voltage reference comparators. The sections below
will describe the functionality of both circuits.
11.2 Low Battery Detect
11.1 Brown Out Reset
The Low Battery Detect (LBD) circuit allows software to monitor
the VCC level at the lower voltage ranges. LBD has eight software programmable voltage reference threshold levels ranging
from 2.0V (Bat_tri[2:0] set to zero) to 3.6V (Bat_trim[2:0] set to
one) that can be changed on the fly. Once VCC falls below the
selected threshold, the LBD flag in the LBD control register is
set. The LBD flag will hold its value until VCC rises above the
threshold. (See Figure 23)
The Brown-out Reset (BOR) function is used to hold the device
in reset when VCC drops below a fixed threshold. While in reset,
the device is held in its initial condition until VCC rises above the
threshold value. Shortly after VCC rises above the threshold
value, an internal reset sequence is started. After the reset
sequence, the core fetches the first instruction and starts normal operation.
The LBD bit is read only. If LBD is 0, it indicates that the VCC
level is higher than the selected threshold. If LBD is 1, it indicates that the VCC level is below the selected threshold. The
threshold level can be adjusted up to eight levels using the three
trim bits (Bat_trim[2:0]) of the LBD control register. The LBD flag
does not cause any hardware actions or an interruption of the
processor. It is for software monitoring only.
On the devices, the BOR should be used in situations when VCC
rises and falls slowly and in situations when VCC does not fall to
zero before rising back to operating range. The BOR can be
thought of as a supplement function to the Power-on Reset
when VCC does not fall below ~1.5V. The Power-on Reset circuit
works best when VCC starts from 0V and rises sharply. So in
applications where VCC is not constant, the BOR will give added
device stability.
The LBD function is disabled during HALT/IDLE mode. After
exiting HALT/IDLE, software must wait at lease 10µs before
reading the LBD bit to ensure that the internal circuit has stabilized.
The BOR circuit must be enabled through the BOR enable bit
(BOREN) in the initialization register. The BOREN bit can only
be set while the device is in programming mode. Once set, the
Figure 23: LBD Control Register Definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
X
X
X
LBD
Bat_trim[2:0]
Figure 24: BOR/LBD Block Diagram
Vcc
1.8V
0
2.2V
1
S
_
to RESET logic
BOR
+
BLSEL16
_
Adjust Reference Voltage
LBD
+
7
16
6
5
4
3
2
1
0
LBD
Control
Register
See Figure 13 for information on BLSEL.
25
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
11.0 Brown-out/Low Battery Detect Circuit
14.0 CLOCK
When a RESET sequence is initiated, all I/O registers will be
reset setting all I/Os to high-impedence inputs. The system
clock is restarted after the required clock start-up delay. A reset
is generated by any one of the following three conditions:
The ACEx microcontroller has an on-board oscillator trimmed to
a frequency of 2MHz who is divided down by two yielding a
1MHz frequency.(See AC Electrical Characteristics.) Upon
power-up, the on-chip oscillator runs continuously unless entering HALT mode or using an external clock source. (See Figure
26.)
• Power-on Reset (as described in Section 13.0)
• Brown-out Reset (as described in Section 11.1)
If required, an external oscillator circuit may be used depending
on the states of the CMODE bits of the initialization register.
(See Table 13) When the device is driven using an external
clock, the clock input to the device (G1/CKI) can range between
DC to 4MHz. For external crystal configuration, the output clock
(CKO) is on the G0 pin. If an external crystal or RC is used, to
yield the corresponding instruction clock the input frequency is
internally divided down by four. If the device is configured for an
external square clock, it will not be divided.
• Watchdog Reset (as described in Section 7.0)
• External Reset15 (as described in Section 13.0)
13.0 Power-On-Reset
The Power-On Reset (POR) circuit is guaranteed to work if the
rate of rise of VCC is no slower than 10ms/1volt. The POR circuit
was designed to respond to fast low to high transitions between
0V and VCC. The circuit will not work if VCC does not drop to 0V
before the next power-up sequence. In applications where 1)
the VCC rise is slower than 10ms/1 volt or 2) VCC does not drop
to 0v before the next power-up sequence the external reset
option should be used. The external reset option provides a way
to properly reset the ACEx microcontroller if POR cannot be
used in the application. The external reset pin contains an internal pull-up resistor.
Table 13: CMODE[0:1] Bit Definition
CMODE[0]
CMODE[1]
Clock Type
0
0
Internal 1 MHz clock
1
0
External square clock
1
1
External RC clock
Figure 25: BOR and POR Circuit Relationship Diagram (see AC Electrical Characteristics)
VCC (Pin 8)
BOR
output
VCC
1.75
VCC
0
VCC
0
Time
BOR Output
POR
output
External
Reset
Pin
(14-Pin Only)
VCC
5.0V
(Pin 7)
15Available
Reset
circuit
output
A
1.8V
0
VCC
POR
output 0
Global Reset
to Logic
B
The Reset circuit will trigger
when inputs A or B transition
from High to Low. At that time
the Global Reset signal will go
high which will reset all controller
logic. The Global Reset will go
high and stay high for around 1µs.
POR Output
Pulse
as option on SOIC-8 package only, it replaces the port G5
26
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
12.0 RESET block
CKI
(G1)
CKO
(G0)
R
VCC
C
15.0 HALT Mode
16.0 IDLE Mode
The HALT mode is a power saving feature that almost completely shuts down the device for current conservation. The
device is placed into HALT mode by setting the HALT enable bit
(EHALT) of the HALT register through software using only the
“LD M, #” instruction. EHALT is a write only bit and is automatically cleared upon exiting HALT. When entering HALT, the internal oscillator and all the on-chip systems including the LBD and
the BOR circuits are shut down.
In addition to the HALT mode power saving feature, the device
also supports an IDLE mode operation. The device is placed
into IDLE mode by setting the IDLE enable bit (EIDLE) of the
HALT register through software using only the “LD M, #” instruction. EIDLE is a write only bit and is automatically cleared upon
exiting IDLE. The IDLE mode operation is similar to HALT
except the internal oscillator, the Watchdog, and the Timer 0
remain active while the other on-chip systems including the LBD
and the BOR circuits are shut down.
The device can exit HALT mode only by the MIW circuit. Therefore, prior to entering HALT mode, software must configure the
MIW circuit accordingly. (See Section 8.0) After a wakeup from
HALT, a 64 clock cycle start-up delay is initiated to allow the
internal oscillator to stabilize before normal execution resumes.
Immediately after exiting HALT, software must clear the Power
Mode Clear (PMC) register by only using the “LD M, #” instruction. (See Figure 28)
The device can exit IDLE by a Timer 0 overflow every 8192
cycles or/and by the MIW circuit. If exiting IDLE mode with the
MIW, prior to entering, software must configure the MIW circuit
accordingly. (See Section 8.0) Once a wake from IDLE mode is
triggered, the core will begin normal operation by the next clock
cycle. Immediately after exiting IDLE mode, software must clear
the Power Mode Clear (PMC) register by using only the “LD M,
#” instruction. (See Figure 29)
Figure 27: HALT Register Definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
x
x
x
x
x
x
EIDLE
EHALT
Figure 28: Recommended HALT Flow
Figure 29: Recommended IDLE Flow
Normal Mode
Normal Mode
LD HALT, #01h
LD
HALT, #01H
Timer0
Overflow
Multi-Input
Wakeup
IDLE Mode
Halt
Multi-Input
Wakeup
LD
PMC, #00H
LD PMC, #00h
Resume Normal
Mode
Resume
Normal Mode
27
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Figure 26: RC Oscillator Diagrams
Core
Type
Part Number
0 1 2
Max. #
Program
Operating
I/Os Memory Size Voltage Range
6
1K
2K
1.8 –
5.5V
2.2 –
5.5V
Temperature Range
Package
Tape
0 to -40 to -40 to 8-pin 8-pin
and
70°C +85C +125°C SOIC TSSOP Reel
ACE8001M8
X
X
X
X
X
X
ACE8001M8X
X
X
X
X
X
X
X
ACE8001MT8
X
X
X
X
X
X
ACE8001MT8X
X
X
X
X
X
X
ACE8001EM8
X
X
X
X
X
X
ACE8001EM8X
X
X
X
X
X
X
X
ACE8001EMT8
X
X
X
X
X
X
ACE8001EMT8X
X
X
X
X
X
X
ACE8000M8
X
X
X
X
X
X
ACE8000M8X
X
X
X
X
X
X
ACE8000EM8
X
X
X
X
X
X
ACE8000EM8X
X
X
X
X
X
X
28
ACE8001 Product Family Rev. B.2
X
X
X
X
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Ordering Information
0.189 - 0.197
(4.800 - 5.004)
8 7 6 5
0.228 - 0.244
(5.791 - 6.198)
1 2 3 4
Lead #1
IDENT
0.010 - 0.020
x 45°
(0.254 - 0.508)
0.0075 - 0.0098
(0.190 - 0.249)
Typ. All Leads
0.150 - 0.157
(3.810 - 3.988)
0.053 - 0.069
(1.346 - 1.753)
8° Max, Typ.
All leads
0.004
(0.102)
All lead tips
0.004 - 0.010
(0.102 - 0.254)
Seating
Plane
0.014
(0.356)
0.016 - 0.050
(0.406 - 1.270)
Typ. All Leads
0.050
(1.270)
Typ
0.014 - 0.020 Typ.
(0.356 - 0.508)
Molded Small Out-Line Package (M8)
Order Number ACE8001M8/ACE8001EM8/ACE8000M8/ACE8000EM8
Package Number M08A
29
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Physical Dimensions inches (millimeters) unless otherwise noted
0.114 - 0.122
(2.90 - 3.10)
8
5
(4.16) Typ (7.72) Typ
0.169 - 0.177
(4.30 - 4.50)
0.246 - 0.256
(6.25 - 6.5)
(1.78) Typ
(0.42) Typ
0.123 - 0.128
(3.13 - 3.30)
(0.65) Typ
1
Land pattern recommendation
4
Pin #1 IDENT
0.0433
Max
(1.1)
0.0256 (0.65)
Typ.
0.0035 - 0.0079
See detail A
0.002 - 0.006
(0.05 - 0.15)
0.0075 - 0.0118
(0.19 - 0.30)
Gage
plane
0°-8°
DETAIL A
Typ. Scale: 40X
0.020 - 0.028
(0.50 - 0.70)
Seating
plane
0.0075 - 0.0098
(0.19 - 0.25)
Notes: Unless otherwise specified
1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Pin Molded TSSOP (MT8)
Order Number ACE8001MT8/ACE8001EMT8
Package Number MTC08
30
ACE8001 Product Family Rev. B.2
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
Physical Dimensions inches (millimeters) unless otherwise noted
ACEx Emulator Kit: Fairchild also offers a low cost real-time incircuit emulator kit that includes:
General Information
Emulator board
Emulator software
Assembler and Manuals
Power supply
DIP14 target cable
PC cable
Fairchild Semiconductor offers different possibilities to evaluate
and emulate software written for ACEx.
Simulator: Is a Windows program able to load, assemble, and
debug ACEx programs. It is possible to place as many breakpoints
as needed, trace the program execution in symbolic format, and
program a device with the proper options. The ACEx Simulator is
available free-of-charge and can be downloaded from Fairchild’s
web site at www.fairchildsemi.com/products/micro
The ACEx emulator allows for debugging the program code in a
symbolic format. It is possible to place one breakpoint and
watch various data locations. It also has built-in programming
capability.
Prototype Board Kits: Fairchild offer two solutions for the simplification of the breadboard operation so that ACEx Applications can be quickly tested.
1) ACEDEMO is can be used for general purpose applications
2) ACETXRX for transmitting / receiving (RF, IR, RS232,
RS485) applications.
ACEDEMO has 8 switches, 8 LEDs, RS232 voltage translator,
buzzer, and a lamp with a small breadboard area.
Ordering P/Ns
Programming Adapters:
DIP8 - ACEADAPTN
DIP14 - ACEADAPTN14
TSSOP8 - ACEADAPTMT8
SO8 - ACEADAPTM8
SO14 - ACEADAPTM
Emulator Kit:
ACEICE (110Vac)
ACEICEEU (220Vac)
Prototype Boards:
ACEDEMO
ACETXRX (315MHz)
ACETXRXEU (433MHz)
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written
approval of the President of Fairchild Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body, or (b) support
or sustain life, and whose failure to perform, when properly used
in accordance with instructions for use provided in the labeling,
can be reasonably expected to result in a significant injury to the
user.
Fairchild Semiconductor
Americas
Customer Response Center
Tel. 1-888-522-5372
Fairchild Semiconductor
Europe
Fax: +44 (0) 1793-856858
Deutsch
Tel: +49 (0) 8141-6102-0
English
Tel: +44 (0) 1793-856856
Français
Tel: +33 (0) 1-6930-3696
Italiano
Tel: +39 (0) 2-249111-1
Fairchild Semiconductor
Hong Kong
8/F, Room 808, Empire Centre
68 Mody Road, Tsimshatsui East
Kowloon. Hong Kong
Tel; +852-2722-8338
Fax: +852-2722-8383
31
ACE8001 Product Family Rev. B.2
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
Fairchild Semiconductor
Japan Ltd.
4F, Natsume Bldg.
2-18-6, Yushima, Bunkyo-ku
Tokyo, 113-0034 Japan
Tel: 81-3-3818-8840
Fax: 81-3-3818-8841
www.fairchildsemi.com
ACE8001 Product Family Arithmetic Controller Engine (ACEx™) for Low Power Applications
ACEx Development Tools