1/4 STRUCTURE Silicon Monolithic Integrated Circuit NAME OF PRODUCT DC-AC Inverter Control IC TYPE ＢＤ９８８９ＦＶ FUNCTION ・2ch control with Push-Pull ・Lamp current and voltage sense feed back control ・Sequencing easily achieved with Soft Start Control ・Short circuit protection with Timer Latch ・Under Voltage Lock Out ・Short circuit protection with over voltage ・Mode-selectable the operating or stand-by mode by stand-by pin ・Synchronous operating the other BD9889FV IC’s ・BURST mode controlled by PWM and DC input ○Absolute Maximum Ratings（Ta = 25℃） Parameter Supply Voltage Operating Temperature Range Storage Temperature Range Power Dissipation Maximum Junction Temperature * Symbol VCC Topr Tstg Pd Tjmax Limits 15 -40～+90 -55～+125 850* +125 Unit V ℃ ℃ mW ℃ Pd derate at 8.5mW/℃ for temperature above Ta = 25℃ (When mounted on a PCB 70.0mm×70.0mm×1.6mm) 〇Recommended operating condition Parameter Supply voltage CT oscillation frequency BCT oscillation frequency Symbol VCC fCT fBCT Limits 5.0～14.0 20～150 0.05～0.50 Unit V kHz kHz Status of this document The Japanese version of this document is the official specification. Please use the translation version of this document as a reference to expedite understanding of the official version. If these are any uncertainty in translation version of this document, official version takes priority. REV. A 2/4 ○Electric Characteristics（Ta=25℃，VCC=7V） Parameter （（WHOLE DEVICE） ） Operating current Stand-by current （（OVER VOLTAGE DETECT）） FB overvoltage detect voltage （（STAND BY CONTROL）） MIN. Limits TYP. MAX. Icc1 Icc2 － － 11.0 2 17.0 10 mA μA Vovf 2.20 2.40 2.60 V Symbol Unit Conditions CT=0.5V Stand-by voltage H VstH 1.6 － VCC V System ＯＮ Stand-by voltage L Stand-by hysteresis （（TIMER LATCH）） Timer Latch voltage Timer Latch current （（BURST MODE）） BOSC Max voltage BOSC Min Voltage BOSC constant current BOSC frequency （（OSC BLOCK）） OSC constant current VstL ⊿Vst -0.3 0.08 － 0.18 0.8 0.28 V V System ＯＦＦ Vcp Icp 1.9 0.5 2.0 1.0 2.1 1.5 V μA VburH VburL IBCT FBOSC 1.94 0.4 1.35/BRT 266 2.0 0.5 1.5/BRT 280 2.06 0.6 1.65/BRT 294 V V A Hz fBCT=0.2kHz fBCT=0.2kHz BRT=33kΩ、BCT=0.050μF ICT 1.35/RT 1.5/RT 1.65/RT A OSC Max voltage VoscH 1.8 2.0 2.2 V OSC Min voltage VoscL 0.3 0.5 0.7 V fCT=60kHz MAXDUTY 44 46.5 49 % fCT=60kHz MAX DUTY Soft start current IS COMP detect Voltage SS COMP detect voltage SRT ON resistance （（UVLO BLOCK）） Operating voltage Shut down voltage Operating voltage (External UVLO) Lock out voltage (External UVLO) Hysteresis width （（REG BLOCK）） REG output voltage REG source current VREF input voltage range （（FEED BACK BLOCK）） Iss 1.0 2.0 3.0 μA Visc Vss RSRT 0.45 2.0 － 0.50 2.2 200 0.55 2.4 400 V V Ω VuvloH VuvloL Vuvlo1 Vuvlo2 ⊿Vuvlo 4.100 3.900 2.160 2.242 0.068 4.300 4.100 2.220 2.315 0.095 4.500 4.300 2.280 2.388 0.122 V V V V V VREG IREG VREF 3.038 5.0 0.60 3.100 － － 3.162 － 1.50 V mA V IS threshold voltage Vis － VREF － V VS threshold voltage IS source current 1 IS source current 2 VS source current （（OUTPUT BLOCK） ） NAch output voltage H NBch output voltage H NAch output voltage L NBch output voltage L NAch output sink resistance NAch output source resistance NBch output sink resistance NBch output source resistance Drive output frequency （（COMP BLOCK）） Over voltage detect Under voltage detect Vvs 1.220 1.250 1.280 V Iis1 Iis2 Ivs － 13.0 － － 20.0 － 1.5 27.0 1.0 μA μA μA VoutNAH VoutNBH VoutNAL VoutNBL RsinkNA RsourceNA RsinkNB RsourceNB fOUT VCC-0.3 VCC-0.3 － － － － － － 58.5 VCC-0.1 VCC-0.1 0.1 0.1 5 8 5 8 60.0 － － 0.3 0.3 10 16 10 16 61.5 V V V V Ω Ω Ω Ω KHz VCOMPH VCOMPL 3.0 0.620 3.1 0.640 3.2 0.660 V V VPH VPL 2.9 － 3.1 － 3.3 0.5 V V （（PROTECT CLOCK）） Normal output voltage Protect output voltage （This product is not designed to be radiation-resistant.） REV. A fCT=60kHz VREF voltage DUTY=2.0V DUTY=0V、IS=0.5V Isink = 10mA Isource = 10mA Isink = 10mA Isource = 10mA RT=18kΩ、CT=400pF 3/4 〇Package Dimensions Device Mark BD9889FV １ SSOP-B28 (unit:mm) 〇Block Diagram 〇Pin Description CT REG VREF VCC REG BLOCK STB RT OSC BRT BCT DUTY BOSC DUTY BLOCK 1 Pin Name DUTY 2 BRT 3 BCT 4 RT 5 SRT Pin No. 6 CT 7 GND Control PWM mode and BURST mode External resistor from BRT to GND for adjusting the BURST triangle oscillator External capacitor from BCT to GND for adjusting the BURST triangle oscillator External resistor from SRT to RT for adjusting the triangle oscillator External resistor from SRT to RT for adjusting the triangle oscillator External capacitor from CT to GND for adjusting the triangle oscillator GROUND 8 FB1 Error amplifier output① 9 10 11 12 13 14 15 16 17 18 19 20 IS1 VS1 FB2 IS2 VS2 VREF FAIL STB COMP1 COMP2 UVLO REG 21 SS 22 SCP 23 24 25 26 27 28 NA2 NB2 PGND NB1 NA1 Vcc SYSTEM ON/OFF STB BLOCK VCC UVLO BLOCK UVLO SS FB1 IS1 VS1 VCC F/B BLOCK① SS PWM BLOCK① CT LOGIC BLOCK ① FB2 IS2 VS2 OUTPUT BLOCK① NA1 NB1 VCC F/B BLOCK② SS PWM BLOCK② CT LOGIC BLOCK ② OUTPUT BLOCK② NA2 NB2 PGND GND PROTECT BLOCK COMP1 COMP2 SCP FAIL SRT REV. A Function Error amplifier input① Error amplifier input② Error amplifier output② Error amplifier input③ Error amplifier input④ Reference voltage Protect clock output Stand-by switch Over or under voltage detect for 1ch Over or under voltage detect for 2ch External Under Voltage Lock OUT Internal regulator output External capacitor from SS to GND for Soft Start Control External capacitor from SCP to GND for Timer Latch FET driver for 2ch FET driver for 2ch Ground for FET drivers FET driver for 1ch FET driver for 1ch Supply voltage input 4/4 〇NOTE FOR USE １. When designing the external circuit, including adequate margins for variation between external devices and IC. Use adequate margins for steady state and transient characteristics. ２. The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended operating range. The standard electrical characteristic values cannot be guaranteed at other voltages in the operating ranges, however the variation will be small. ３. Mounting failures, such as misdirection or miscounts, may harm the device. ４. A strong electromagnetic field may cause the IC to malfunction. ５. The GND pin should be the location within ±0.3V compared with the PGND pin. ６. BD9889FV incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation of the thermal shutdown circuit is assumed. ７. Absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become significantly shortened. Moreover, the exact failure mode caused by short or open is not defined. Physical countermeasures, such as a fuse, need to be considered when using a device beyond its maximum ratings. ８. About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching. Make sure to leave adequate margin for this IC variation. ９. On operating Slow Start Control (SS is less than 2.2V), It does not operate Timer Latch. １０. By STB voltage, BD9889FV is changed to 2 states. Therefore, do not input STB pin voltage between one state and the other state (0.8～1.6). １１. The pin connected a connector need to connect to the resistor for electrical surge destruction. This IC is a monolithic IC which (as shown is Fig-1) has P+ substrate and between the various pins. A P-N junction is formed from this P layer of each pin. For example, the relation between each potential is as follows, ○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.) ○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.) Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin. １２．This IC is a monolithic IC which (as shown is Fig-1)has P+ substrate and between the various pins. A P-N junction is formed from this P layer of each pin. For example, the relation between each potential is as follows, ○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.) ○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.) Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin. Transistor (NPN) Resistance (PinA) (PinB) B E C Ｃ GND P P＋ N P＋ N Ｎ N Ｎ P substrate GND Parasitic diode N P substrate GND Parasitic diode (PinB) (PinA) B CＣ Ｂ EＥ Parasitic diode GND GND Other adjacent components Parasitic diode Fig-1 Simplified structure of a Bipolar IC REV. A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. 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