www.fairchildsemi.com TMC2242A/TMC2242B Digital Half-Band Interpolating/Decimating Filter 12-bit In/16-bit Out, 60 MHz Features • TMC2242A and TMC2242B are pin-compatible with TMC2242 • User selectable interpolate gain, -6 dB or 0 dB (2242B) • 30, 40 and 60 MHz speed grades • User selectable 2:1 decimation, 1:2 interpolation, and equal-rate filter modes • Passband ripple < ±0.01 dB • Stopband rejection 59.4 dB from 0.28 to 0.50 x fs • Cascading two TMC2242A or TMC2242B meets CCIR 601 low-pass filter requirement • Dedicated 12-bit 2's complement input data port and 16-bit output data port with user-selectable rounding from 9 to 16 bits • Two's complement or offset binary output format • Built-in limiter prevents overflow • Single +5 Volt power supply operation • Small 44-Lead PLCC and 44-Lead MQFP Applications • • • • • • • • • Low-cost video filtering Chrominance bandwidth limiter Simple, inexpensive video D/A post-filters Reduced cost and complexity for A/D anti-aliasing filters High-performance digital low-pass filters Digital waveform reconstruction post-filtering Telecommunications Direct digital synthesis Radar Description The TMC2242A and TMC2242B are fixed-coefficient linear-phase half-band (low-pass) digital filters. They can be used to halve or double the sampling rate of a digital signal. When used as a decimating post-filter with a double-speed oversampling A/D converter, they greatly reduce the cost and complexity of anti-aliasing filters required ahead of the A/D converter. When used as an interpolating pre-filter with a double-speed oversampling D/A converter, the TMC2242A and TMC2242B significantly reduce the design complexity and production cost of reconstruction filters used on D/A outputs. The TMC2242A and TMC2242B user selects the mode of operation (decimate, interpolate, or equal-rate) and rounding. The TMC2242A and TMC2242B accept 12-bit 2's complement data at up to 60 MHz and output saturated (overflow-protected) 2's complement or offset binary data rounded to from 9 to 16 bits. Within the speed grade I/O limit, the output sample rate may be 1/2, 1, or 2 times the input sample rate. Block Diagram 12 OE 12 12 SI11-0 12 55 Tap FIR Filter Round and Limit 16 16 16 SO15-0 Interpolate 0-1-0-1 Decimate, Equal Rate 1-1-1-1 CLK DEC INT SYNC Control 3 TCO RND2-0 65-2242A-01 Rev. 1.2.0 PRODUCT SPECIFICATION TMC2242A/TMC2242B Description (continued) The filter response is flat to within ±0.01 dB from 0.00 to 0.22 x fs, with stopband attenuation greater than 59.4 dB from 0.28 x fs to the Nyquist frequency. The response is 6 dB down at 0.25 x fs. Symmetric-coefficient filters such as the TMC2242A and TMC2242B have linear phase response. Full compliance with the CCIR-601 standard of 12 dB attenuation at 0.25 x fs is achieved by cascading two parts. The TMC2242A and TMC2242B are fabricated on an advanced submicron CMOS process. They are available in a 44-lead J-lead PLCC package. Performance is guaranteed from 0°C to 70°C. Functional Description The TMC2242A and TMC2242B implement a fixed-coefficient linear-phase Finite Impulse Response (FIR) filter of 55 effective taps, with special rate-matching input and output structures to facilitate 2:1 decimation and 1:2 interpolation. The faster of either the input or output registers will operate at the guaranteed maximum clock rate (speed grade). The total internal pipeline latency from the input of an impulse to the corresponding output peak (digital group delay) is 34 cycles; the 55-value output response begins after 7 clock cycles and ends after 61 cycles. To perform interpolation, the chip slows the effective input register clock rate to half the output rate. It internally inserts zeroes between the incoming data samples to "pad" the input data rate to match the output rate. To perform decimation, the chip sets the output register clock rate to half of the input rate. One output is then obtained for every two inputs. For interpolation, the user should bring SYNC HIGH for at least one clock cycle, returning it LOW with the first desired input data value. When interpolating, the chip will then continue to accept a new data input on each alternate rising edge of the clock. When decimating, the chip will present one output value for every two clock cycles. The user may leave SYNC LOW or toggle it once per rising clock edge, with equivalent performance. The output data format is two's complement if TCO is HIGH, inverted offset binary if LOW. The user can tailor the output data word width to his/her system requirements using the Rounding control. As shown in Table 4, the output is half-LSB rounded to the resolution selected by the value of RND2-0. The asynchronous three-state output enable control simplifies connection to a data bus with other drivers. Table 1. Operating Modes DEC INT TMC2242A TMC2242B 0 0 Equal Rate Interpolate (0 dB) 0 1 Decimate Decimate 1 0 1 1 Interpolate (-6 dB) Interpolate (-6 dB)1 Equal Rate Equal Rate Note: 1. With 15-bit overflow protection. All other modes on both parts limit to 16 bits. 44 Lead PLCC 2 SO13 SO14 SO15 OE TCO DEC INT SYNC CLK GND SI11 34 35 36 37 38 39 40 41 30 5 29 TMC2242A TMC2242B 6 7 28 27 24 11 23 22 25 10 21 26 9 20 8 19 28 27 26 25 29 24 17 23 30 22 16 21 31 20 15 19 32 18 14 31 4 18 33 3 17 13 34 32 16 TMC2242A TMC2242B 12 42 35 33 2 15 36 11 1 14 10 SO12 SO11 SO10 SO9 SO8 GND VDD SO7 SO6 SO5 SO4 43 37 13 9 GND VDD SI10 SI9 SI8 SI7 SI6 SI5 SI4 SI3 VDD 12 38 GND VDD SI10 SI9 SI8 SI7 SI6 SI5 SI4 SI3 VDD 65-2242A-02 65-2242A-02 SO3 SO2 SO1 SO0 RND2 RND1 RND0 SI0 SI1 SI2 GND 39 8 44 40 41 42 43 1 44 2 3 4 7 SO3 SO2 SO1 SO0 RND2 RND1 RND0 SI0 SI1 SI2 GND SO12 SO11 SO10 SO9 SO8 GND VDD SO7 SO6 SO5 SO4 5 6 SO13 SO14 SO15 OE TCO DEC INT SYNC CLK GND SI11 Pin Assignments 44 Lead MQFP TMC2242A/TMC2242B PRODUCT SPECIFICATION Pin Descriptions Pin Number Pin Name PLCC MQFP Pin Function Description Timing Controls INT 44 38 Interpolate. When INT is LOW and DEC is HIGH, the input data register runs at 1/2 the CLK rate and zeros are inserted in the data stream between valid input values, reducing gain by 6dB. The TMC2242A and TMC2242B interpolate and output results at the full CLK rate. DEC 1 39 Decimate. When DEC is LOW and INT is HIGH, the input data register runs at the full CLK rate. In this mode, the TMC2242A and TMC2242B decimate and output results at 1/2 the CLK rate. When INT = DEC, the TMC2242A is in equal rate mode. When both INT and DEC are HIGH, the TMC2242B is likewise in equal-rate mode, but when both INT and DEC are LOW, the TMC2242B interpolates with unity gain. In equal-rate mode, the input and output sample rates equal the chip clock rate. SYNC 43 37 Synchronization. Incoming data are synchronized by holding SYNC HIGH on CLK N–1 and LOW on CLK N when the first input data word is present on SI11-0. If DEC = INT=1 (equal rate mode), SYNC is inactive. SYNC may be held LOW until resynchronization is desired, or it may be toggled at 1/2 the CLK rate. CLK 42 36 Clock. The TMC2242A and TMC2242B operate from a single master clock. All internal registers, except the output register in decimation mode, are strobed on the rising edge of CLK. All timing parameters are referenced to the rising edge of CLK. 40, 37-30, 27-25 34, 31-24, 21-19 Input Data Port. A 12-bit 2's-complement input word is registered by the rising edge of CLK. In Interpolate Mode, SI11-0 is registered on every other CLK (synchronized by SYNC). SI11 is the MSB. 4-11, 14-21 42-44, 1-5, 8-15 Output Data Port. A 16-bit 2's-complement output result is available after the rising edge of CLK. In Decimate Mode, SO15-0 is registered on every other CLK (synchronized by SYNC). SO15-0 is rounded according to the state of RND2-0. SO15 is the MSB. Data Inputs SI11-0 Data Outputs SO15-0 The limiter circuitry ensures that for internal overflow, a valid full-scale output (7FFF or 8000) will be generated. With the TMC2242B in interpolate mode with -6dB gain, limits are 3FFF and C000 (TCO=1). Output Controls OE 3 41 Output Enable. When LOW, SO15-0 are enabled. When HIGH, SO15-0 are in a high-impedance state. OE is asynchronous with respect to CLK. TCO 2 40 Output Format. When TCO is HIGH, output data are in signed 2's-complement format. When LOW, the output is inverted offset binary. RND2-0 22-24 16-18 Rounding Select. These inputs set the position of the effective LSB of the output result. Outputs below the rounding bit are zeroed (Table 4). VDD 13,29, 38 7, 23, 32 Supply Voltage. +5 Volt power inputs. These should come from the same power source and be decoupled to GND. GND 12,28, 39,41 6, 22, 33, 35 Ground. Ground inputs should be connected to the system digital ground plane. Power 3 PRODUCT SPECIFICATION TMC2242A/TMC2242B Absolute Maximum Ratings (beyond which the device may be damaged)1 Parameter Conditions Supply Voltage Input Voltage Output Applied Voltage2 Externally Forced Current3,4 Short Circuit Duration Min Max Units -0.5 7.0 V -0.5 VDD + 0.5 V -0.5 VDD + 0.5 V -3.0 +6.0 mA 1 sec 110 °C 140 °C 300 °C 150 °C Single output in HIGH state to ground Operating Temperature (Case) -20 Junction Temperature Lead Soldering Temperature 10 seconds Storage Temperature -65 Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device. Operating Conditions Parameter 4 VDD Power Supply Voltage fCLK Clock frequency Conditions Min Nom Max Units 4.75 5.0 5.25 V TMC2242A, B 30 MHz TMC2242A-1,B-1 40 MHz TMC2242A-2,B-2 60 MHz tPWH CLK pulse width, HIGH 6 ns tPWL CLK pulse width, LOW 6 ns tS Input Data Set-up Time 6 ns 1 ns 2.0 V tH Input Data Hold Time VIH Input Voltage, Logic HIGH VIL Input Voltage, Logic LOW 0.8 V IOH Output Current, Logic HIGH -2.0 mA IOL Output Current, Logic LOW 4.0 mA TA Ambient Temperature, Still Air 70 °C 0 TMC2242A/TMC2242B PRODUCT SPECIFICATION Electrical Characteristics Parameter Conditions IDD VDD = Max, CLOAD=25pF, fCLK=Max IDDU IDDQ Total Power Supply Current Power Supply Current, Unloaded Power Supply Current, Quiescent Min Typ Max Units TMC2242A,B 150 mA TMC2242A-1,B-1 195 mA TMC2242A-2,B-2 290 mA TMC2242A,B 120 mA TMC2242A-1,B-1 155 mA TMC2242A-2,B-2 230 mA 5 mA VDD = Max, OE = HIGH, fCLK=Max VDD = Max, CLK = LOW CPIN I/O Pin Capacitance IIH Input Current, HIGH VDD = Max, VIN = VDD 5 ±10 mA pF IIL Input Current, LOW VDD = Max, VIN = 0 V ±10 mA IOZH Leakage Current, HIGH OE = HIGH, VOUT = VDD ±10 mA IOZL Leakage Current, LOW OE = HIGH, VOUT = 0 V ±10 mA IOS Short-Circuit Current VDD = Max, Output = HIGH, one pin to ground, one second duration max. -20 -80 mA VOH Output Voltage, HIGH SO15-0, IOH = Max 2.4 VOL Output Voltage, LOW SO15-0, IOL = Max V 0.4 V Switching Characteristics Parameter Conditions Min Typ Max Units 15 ns tDO Output Delay Time CLOAD = 25 pF tHO Output Hold Time CLOAD = 25 pF tENA Output Enable Time CLOAD = 0 pF 12 ns tDIS Output Disable Time CLOAD = 0 pF 12 ns 2.5 ns 5 PRODUCT SPECIFICATION TMC2242A/TMC2242B Table 2. Impulse Response Hex Decimal Equivalent FFF2 -0.000875473 0000 0.0 0017 0.001390457 0000 0.0 FFDB -0.002265930 0000 0.0 0039 0.003501892 0000 start & end INT=1 INT=1 INT=0 INT=1 DEC=1 DEC=1 DEC=1 DEC=0 Input TCO=0 TCO=1 TCO=1 TCO=1 400 xx xx xx xx 400 ... 400 xx ... 3FE7 xx ... 4018 xx ... 2008 xx ... 4018 DC Gain 0.0 400 000 ... 000 3FE7 3FE7 ... 3B90 4018 4018 ... 446F 2010 2008 ... 245F 4018 4018 ... 446F Max Ringing FFA8 -0.006366836 000 3B90 446F 2010 446F 0000 0.0 000 4FEB 3014 1004 1004 007D 0.007621765 000 6FFB 1004 0000 1004 0000 0.0 FF51 -0.01071167 000 ... 000 8456 ... 7FFF FBA9 ... 0000 FBA9 ... 0000 FBA9 ... 0000 0000 0.0 00F3 0.01483154 0000 0.0 FEB5 -0.02018738 0000 0.0 01CA 0.02796364 0000 0.0 FD79 -0.03949928 0000 0.0 03CD 0.05937767 0000 0.0 F95E -0.1036148 0000 0.0 145B 0.3180542 2010 0.5009766 Input = 0, 0, 0, …, 0, 400h, 0, …, 0, 0, 0 INT = DEC = TCO = 1 6 Table 3. Step Response Min Ringing Steady State Table 4a. Input Data Format -20 center 2-1 2-2 … 2-10 2-11 TMC2242A/TMC2242B PRODUCT SPECIFICATION Table 4b. Output Data Formats and Bit Weighting for TCO = 1 Interpolation Mode (TMC2242A and TMC2242B when INT = 0 and DEC = 1) -21 20 2-1 26 … 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 Decimation, Equal Rate Modes (and TMC2242B in unity gain interpolate mode with INT = DEC = 0) -20 2-1 2-2 2-7 … 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 Rounded LSBs as a function of RND2-0 RND2-0 SO15 SO14 SO13 … SO8 SO7 SO6 SO5 SO4 SO3 SO2 SO1 SO0r 000 SO15 SO14 SO13 … SO8 SO7 SO6 SO5 SO4 SO3 SO2 SO1r 0 001 SO15 SO14 SO13 … SO8 SO7 SO6 SO5 SO4 SO3 SO2r 0 0 010 SO15 SO14 SO13 … SO8 SO7 SO6 SO5 SO4 SO3r 0 0 0 011 SO15 SO14 SO13 … SO8 SO7 SO6 SO5 SO4r 0 0 0 0 100 SO15 SO14 SO13 … SO8 SO7 SO6 SO5r 0 0 0 0 0 101 SO15 SO14 SO13 … SO8 SO7 SO6r 0 0 0 0 0 0 110 SO15 SO14 SO13 … SO8 SO7r 0 0 0 0 0 0 0 111 Notes: 1. A leading minus sign denotes the two’s complement sign bit. 2. When TCO=0, the most significant bit of the output is positive instead of negative. 3. In all operating modes except INT = 0 and DEC = 1, the gain is approximately unity. When INT = 0 and DEC = 1, the output gain is -6 dB. 4. The "r" indicates that the trailing significant output bit has been rounded to the nearest 1/2 LSB. (Internally, the chip adds 1 to the next lower bit, to allow the user to obtain a properly rounded output) Table 5. TMC2242A Steady-State Output Values and Limiter Triggers (L) versus Input Data INT = 1 or DEC = 0 INT = 0 and DEC = 1 Input TCO = 0 TCO = 1 TCO = 0 TCO = 1 Interpretation 7FF 0000 (L) 7FFF (L) 3FF7 / 3FE7 4008 / 4018 + full-scale 400 3FE7 4018 5FF7 / 5FEF 2008 / 2010 +1/2 scale 001 7FEF 0010 7FF7 0008 +1 LSB 000 7FFF 0000 7FFF 0000 Zero FFF 800F FFF0 8007 FFF8 -1 LSB C00 C017 BFE8 A007 / A00F DFF8 / DFF0 -1/2 scale 801 FFFF (L) 8000 (L) C007 / C017 BFF8 / BFE8 - full-scale 7 PRODUCT SPECIFICATION TMC2242A/TMC2242B Table 6. TMC2242B Steady-State Output Values and Limiter Triggers (L) versus Input Data Interpolation Modes INT = 0 and DEC = 0 INT = 0 and DEC = 1 Input TCO = 0 TCO = 1 TCO = 0 TCO = 1 Interpretation 7FF 0000 (L) 7FFF (L) 4000 (L) 3FFF (L) + full-scale 400 3FEF / 3FDF 4010 / 4020 5FF7 / 5FEF 2008 / 2010 +1/2 scale 001 7FEF 0010 7FF7 0008 +1 LSB 000 7FFF 0000 7FFF 0000 Zero FFF 800F FFF0 8007 FFF8 -1 LSB C00 C00F / C01F BFF0 / BFE0 A007 / A00F DFF8 / DFF0 -1/2 scale 801 FFFF 8000 (L) BFFF C000 (L) - full-scale Decimation and Equal-Rate Modes INT = 1 Input TCO = 0 TCO = 1 Interpretation 7FF 0000 (L) 7FFF (L) + full-scale 400 3FE7 4018 +1/2 scale 001 7FEF 0010 +1 LSB 000 7FFF 0000 Zero FFF 800F FFF0 -1 LSB C00 C017 BFE8 -1/2 scale 801 FFFF (L) 8000 (L) - full-scale Performance Curves 0 -10 -20 Atten (dB) -30 -40 -50 -60 65-2242A-03 -70 -80 -90 0.00 0.10 0.20 0.30 Normalized Frequency Figure 1. Frequency Response 8 0.40 0.50 TMC2242A/TMC2242B PRODUCT SPECIFICATION Performance Curves (continued) 0.10 0.08 0.06 Atten (dB) 0.04 0.02 0.00 -0.02 65-32242A-04 -0.04 -0.06 -0.08 -0.10 0.00 0.10 0.20 0.30 Normalized Frequency Figure 2. Passband Ripple Response 110 100 90 %/Full Scale 80 70 60 50 40 30 65-2242A-05 20 10 0 -10 0 10 20 30 Sample 40 50 60 Figure 3. Step Response Equivalent Circuits VDD p VDD p Digital Input Digital Output n n GND 65-2242A-09 Figure 7. Equivalent Digital Input Circuit 65-2242A-10 GND Figure 8. Equivalent Digital Output Circuit 9 PRODUCT SPECIFICATION TMC2242A/TMC2242B Timing Diagrams tPWH 1/fC tPWL CLK tS 34 SI11-0 tH 35 36 37 38 SYNC tHO tDO 1 SO15-0 2 3 4 65-2242A-06 OE is LOW. Note: Values at SO15-0 are impulse response centers (peaks) corresponding to same-numbered inputs. Figure 4. Equal Rate Mode tPWH 1/fC 34 CLK 35 tS SI11-0 34 36 tPWL 37 38 tH 35 36 37 38 SYNC tHO 1 SO15-0 3 65-2242A-07 OE is LOW. Figure 5. Decimate Mode tPWH 1/fC 34 CLK 35 tS 36 37 38 tH 35 SI11-0 tPWL 37 SYNC tHO 1 SO15-0 tDO 2 4 65-2242A-08 OE is LOW. Figure 6. Interpolate Mode 10 3 TMC2242A/TMC2242B PRODUCT SPECIFICATION Timing Diagrams (continued) tENA tDIS OE 0.5V Three-State Outputs 2.0V 0.8V 0.5V High Impedance 65-2242A-11 Figure 9. Threshold Levels for Three State Measurements Applications Discussion The TMC2242A and TMC2242B are well-suited for filtering digitized composite NTSC or PAL video. In Figure 10, the TMC1175A 8-bit video A/D converter outputs, D7-0, are connected to the TMC2242B inputs, SI11-4, respectively (grounding SI3-0). The RND2-0 controls are set to 111 for a 9-bit rounded decimated output on SO15-7. In Figure 11, the TMC2242B drives a fast D/A converter to reconstruct analog composite video. The TMC3003 10-bit digital-to-analog converter inputs, D9-0 are connected to the TMC2242B outputs SO15-6, respectively. The TMC2242B RND2-0 controls are set to 110 for rounded 10-bit interpolation operation. TTL Clock 27.000 MHz (D1) 28.636 MHz (NTSC D2) 2 uH Composite Video 75 Ohm 300 pF 2 uH VIN 510 pF 300 pF TMC1175A 8-bit A/D 75 Ohm AGND 65-2242A-12 D7 SI11 MSB TMC2242B SI10-4 7 D6-0 DEC=0 TCO=INT=1 27.000 MHz (D1) 28.636 MHz (NTSC D2) SO15 SO14-7 8 9 13.500 MHz (D1) 14.318 MHz (NTSC D2) Figure 10. Decimating Oversampled Video With a Low Cost 8-bit A/D TTL Clock 27.000 MHz (D1) 28.636 MHz (NTSC D2) MSB SI11 12 11 LSB TMC2242B SO15 SI10-0 SO14-6 9 D9 TMC3003 10-bit D/A D8-0 75 Ohm TCO=1 INT=DEC=0 13.500 MHz (D1) 14.318 MHz (NTSC D2) 2 uH IOUT AGND 510 pF 300 pF 27.000 MHz (D1) 28.636 MHz (NTSC D2) 2 uH 300 pF Composite Video 75 Ohm 65-2242A-13 Note: Data buses are unsigned binarys; TMC2242 input is two’s complement. Figure 11. Interpolating Digital Video Signals before Reconstruction 11 PRODUCT SPECIFICATION Notes: 12 TMC2242A/TMC2242B TMC2242A/TMC2242B PRODUCT SPECIFICATION Notes: 13 PRODUCT SPECIFICATION TMC2242A/TMC2242B Mechanical Dimensions – 44-Pin PLCC Package Inches Symbol Min. A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc Max. .165 .180 .090 .120 .020 — .013 .021 .026 .032 .685 .695 .650 .656 .500 BSC .050 BSC .042 .056 11 44 — .004 Millimeters Min. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982 Max. 4.19 4.57 2.29 3.05 .51 — .33 .53 .66 .81 17.40 17.65 16.51 16.66 12.7 BSC 1.27 BSC 1.07 1.42 11 44 — 0.10 2. Corner and edge chamfer (J) = 45¡ 3. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm) 3 2 E E1 D J D1 D3/E3 B1 J e A A1 A2 B –C– LEAD COPLANARITY ccc C 14 TMC2242A/TMC2242B PRODUCT SPECIFICATION Mechanical Dimensions – 44-Lead MQFP Package Inches Symbol Min. A A1 A2 B C D/E D1/E1 e L N ND a ccc Max. .077 .093 .000 .010 .077 .083 .012 .018 .005 .009 .510 .530 .390 .398 .032 BSC .026 .037 44 11 0¡ 7¡ — .004 Millimeters Min. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. Max. 1.95 2.35 .00 .25 1.95 2.11 .30 .46 .13 .23 12.95 13.45 9.90 10.10 .81 BSC .66 .94 44 11 0¡ 7¡ — 0.10 2. Dimensions "D1" and "E1" do not include mold protrusion. 3. Pin 1 identifier is optional. 4. Dimension N: number of terminals. 5. Dimension ND: Number of terminals per package edge. 7 6. "L" is the length of terminal for soldering to a substrate. 7. "B" includes lead finish thickness. 2 6 4 5 D D1 e PIN 1 IDENTIFIER E E1 C L a 0.063" Ref (1.60mm) See Lead Detail A Base Plane A2 B A1 -C- Seating Plane LEAD COPLANARITY ccc 44 Lead Metric Quad Flat Pack (MQFP) – 3.2mm Footprint Rev 1.0 C 11/28/95 15 TMC2242A/TMC2242B PRODUCT SPECIFICATION Ordering Information Product Number Temperature Range Speed Grade Screening Package Package Marking TMC2242AR2C 0°C to 70°C 30 MHz Commercial 44-Lead PLCC 2242AR2C TMC2242AR2C1 0°C to 70°C 40 MHz Commercial 44-Lead PLCC 2242AR2C1 TMC2242AR2C2 0°C to 70°C 60 MHz Commercial 44-Lead PLCC 2242AR2C2 TMC2242BR2C 0°C to 70°C 30 MHz Commercial 44-Lead PLCC 2242BR2C TMC2242BR2C1 0°C to 70°C 40 MHz Commercial 44-Lead PLCC 2242BR2C1 TMC2242BR2C2 0°C to 70°C 60 MHz Commercial 44-Lead PLCC 2242BR2C2 TMC2242AKTC 0°C to 70°C 30 MHz Commercial 44-Lead MQFP 2242AKTC TMC2242AKTC1 0°C to 70°C 40 MHz Commercial 44-Lead MQFP 2242AKTC1 TMC2242AKTC2 0°C to 70°C 60 MHz Commercial 44-Lead MQFP 2242AKTC2 TMC2242BKTC 0°C to 70°C 30 MHz Commercial 44-Lead MQFP 2242BKTC TMC2242BKTC1 0°C to 70°C 40 MHz Commercial 44-Lead MQFP 2242BKTC1 TMC2242BKTC2 0°C to 70°C 60 MHz Commercial 44-Lead MQFP 2242BKTC2 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS7002242A Ó 1998 Fairchild Semiconductor Corporation