TI DAC5686IPZP

DAC5686
www.ti.com
SLWS147B – APRIL 2003 – REVISED AUGUST 2004
16-BIT, 500-MSPS, 2×–16× INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG
CONVERTER
FEATURES
•
•
•
•
•
•
500 MSPS Maximum Update Rate DAC
WCDMA ACPR
– 1 Carrier: 76 dB Centered at 30.72-MHz IF,
245.76 MSPS
– 1 Carrier: 73 dB Centered at 61.44-MHz IF,
245.76 MSPS
– 2 Carrier: 72 dB Centered at 30.72-MHz IF,
245.76 MSPS
– 4 Carrier: 64 dB Centered at 92.16-MHz IF,
491.52 MSPS
Selectable 2×, 4×, 8×, and 16× Interpolation
– Linear Phase
– 0.05-dB Pass-Band Ripple
– 80-dB Stop-Band Attenuation
– Stop-Band Transition 0.4–0.6 fDATA
32-Bit Programmable NCO
On-Chip 2×–16× PLL Clock Multiplier With
Bypass Mode
Differential Scalable Current Outputs: 2 mA to
20 mA
•
•
•
•
•
On-Chip 1.2-V Reference
1.8-V Digital and 3.3-V Analog Supplies
1.8-V/3.3-V CMOS Compatible Interface
Power Dissipation: 950 mW at Full Maximum
Operating Conditions
Package: 100-Pin HTQFP
APPLICATIONS
•
•
•
•
•
•
Cellular Base Transceiver Station Transmit
Channel
– CDMA: W-CDMA, CDMA2000, IS-95
– TDMA: GSM, IS-136, EDGE/UWC-136
Baseband I and Q Transmit
Input Interface: Quadrature Modulation for
Interfacing With Baseband Complex Mixing
ASICs
Single-Sideband Up-Conversion
Diversity Transmit
Cable Modem Termination System
DESCRIPTION
The DAC5686 is a dual-channel 16-bit high-speed digital-to-analog converter (DAC) with integrated 2×, 4×, 8×,
and 16× interpolation filters, a numerically controlled oscillator (NCO), onboard clock multiplier, and on-chip
voltage reference. The DAC5686 has been specifically designed to allow for low input data rates between the
DAC and ASIC, or FPGA, and high output transmit intermediate frequencies (IF). Target applications include
high-speed digital data transmission in wired and wireless communication systems and high-frequency
direct-digital synthesis DDS.
The DAC5686 provides three modes of operation: dual-channel, single-sideband, and quadrature modulation. In
dual-channel mode, interpolation filtering increases the DAC update rate, which reduces sinx/x rolloff and
enables the use of relaxed analog post-filtering.
Single-sideband mode provides an alternative interface to the analog quadrature modulators. Channel carrier
selection is performed at baseband by mixing in the ASIC/FPGA. Baseband I and Q from the ASIC/FPGA are
input to the DAC5686, which in turn performs a complex mix resulting in Hilbert transform pairs at the outputs of
the DAC5686's two DACs. An external RF quadrature modulator then performs the final single-sideband
up-conversion. The DAC5686's complex mixing frequencies are flexibly chosen with the 32-bit programmable
NCO.
Unmatched gains and offsets at the RF quadrature modulator result in unwanted sideband and local oscillator
feedthrough. Each DAC in the DAC5686 has an 11-bit offset adjustment and 12-bit gain adjustment, which
compensate for quadrature modulator input imbalances, thus reducing RF filtering requirements.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2004, Texas Instruments Incorporated
DAC5686
www.ti.com
SLWS147B – APRIL 2003 – REVISED AUGUST 2004
In quadrature modulation mode, on-chip mixing provides baseband-to-IF up-conversion. Mixing frequencies are
flexibly chosen with a 32-bit programmable NCO. Channel carrier selection is performed at baseband by complex
mixing in the ASIC/FPGA. Baseband I and Q from the ASIC/FPGA are input to the DAC5686, which interpolates
the low data-rate signal to higher data rates. The single DAC output from the DAC5686 is the final IF
single-sideband spectrum presented to RF.
The 2×, 4×, 8×, and 16× interpolation filters are implemented as a cascade of half-band 2× interpolation filters.
Unused filters for interpolation rates of less than 16× are shut off to reduce power consumption. The DAC5686
provides a full bypass mode, which enables the user to bypass all the interpolation and mixing.
The DAC5686 PLL clock multiplier controls all internal clocks for the digital filters and the DAC cores. The
differential clock input and internal clock circuitry provides for optimum jitter performance. Sine wave clock input
signal is supported. The PLL can be bypassed by an external clock running at the DAC core update rate. The
clock divider of the PLL ensures that the digital filters operate at the correct clock frequencies.
The DAC5686 operates with an analog supply voltage of 3.3 V and a digital supply voltage of 1.8 V. Digital I/Os
are 1.8-V and 3.3-V CMOS compatible. Power dissipation is 950 mW at maximum operating conditions. The
DAC5686 provides a nominal full-scale differential current output of 20 mA, supporting both single-ended and
differential applications. The output current can be directly fed to the load with no additional external output buffer
required. The device has been specifically designed for a differential transformer-coupled output with a 50-Ω
doubly terminated load. For a 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an output
power of 4 dBm) and 1:1 impedance ratio transformer (–2-dBm output power) are supported.
The DAC5686 operational modes are configured by programming registers through a serial interface. The serial
interface can be configured to either a 3- or 4-pin interface allowing it to communicate with many
industry-standard microprocessors and microcontrollers. Data (I and Q) can be input to the DAC5686 as
separate parallel streams on two data buses, or as a single interleaved data stream on one data bus.
An accurate on-chip 1.2-V temperature-compensated band-gap reference and control amplifier allows the user to
adjust the full-scale output current from 20 mA down to 2 mA. This provides 20-dB gain range control
capabilities. Alternatively, an external reference voltage can be applied for maximum flexibility. The device
features a SLEEP mode, which reduces the standby power to approximately 10 mW, thereby minimizing the
system power consumption.
The DAC5686 is available in a 100-pin HTQFP package. The device is characterized for operation over the
industrial temperature range of –40°C to 85°C.
ORDERING INFORMATION
TA
–40°C to 85°C
(1)
2
Thermal pad size: 6 mm × 6 mm
PACKAGE DEVICES
100 HTQFP (1) (PZP) PowerPAD™ Plastic Quad Flatpack
DAC5686IPZP
DAC5686
www.ti.com
SLWS147B – APRIL 2003 – REVISED AUGUST 2004
FUNCTIONAL BLOCK DIAGRAM
Block Diagram of the DAC5686
CLKVDD
CLKGND
PLLLOCK
LPF
PLLGND
PLLVDD
PHSTR
SLEEP
DVDD
CLK1
1.2 V
Reference
CLK1C
CLK2C
A
Offset
FIR1
2
FIR2
2
FIR3
2
2
2
A Gain
FIR5
FIR4
2
DB[15:0]
2
EXTLO
BIASJ
Fdata
DEMUX
EXTIO
2 – 16 Fdata
Internal Clock Generation
2 – 16 PLL Clock Multiplier
CLK2
DA[15:0]
DGND
2
x
sin(x)
16-Bit
DAC
x
sin(x)
16-Bit
DAC
TxENABLE
IOUTA1
IOUTA2
IOUTB1
IOUTB2
IOGND
cos
RESETB
SIF
sin
B
Offset
IOVDD
B Gain
NCO
100-Pin HTQFP
SDIO
SDO SDENB SCLK
AVDD
AGND
3
DAC5686
www.ti.com
SLWS147B – APRIL 2003 – REVISED AUGUST 2004
IOVDD
IOGND
DB7
DB6
DB5
79
78
77
76
DB8
83
AGND
1
75
DB4
AVDD
2
74
DB3
AVDD
3
73
DB2
AGND
4
72
DB1
IOUTB1
5
71
DB0 (LSB)
IOUTB2
6
70
PLLLOCK
AGND
7
69
DGND
AVDD
8
68
DVDD
AGND
9
67
PLLVDD
AVDD
10
66
LPF
EXTIO
11
65
PLLGND
AGND
12
64
CLKGND
BIASJ
13
63
CLK2C
AVDD
14
62
CLK2
EXTLO
15
61
CLKVDD
AVDD
16
60
CLK1C
AGND
17
59
CLK1
Top View 100 HTQFP
DAC5686
TERMINAL
NAME
NO.
I/O
AGND
1, 4, 7, 9,
12, 17, 19,
22, 25
I
Analog ground return
AVDD
2, 3, 8, 10,
14, 16, 18,
23, 24
I
Analog supply voltage
46
47
48
49
50
DA7
DA6
DA5
43
DA8
DESCRIPTION
IOVDD
42
DA9
Terminal Functions
IOGND
41
DA10
45
40
DA11
44
39
DA12
DVDD
38
DGND
37
DVDD
DGND
DA4
36
51
35
25
DA13
AGND
DA14
DA3
34
DA2
52
33
53
24
TxENABLE
23
AVDD
DA15 (MSB)
AVDD
32
DA1
DVDD
DA0 (LSB)
54
31
55
22
30
21
AGND
SDO
IOUTA1
SDIO
DVDD
29
56
SCLK
20
28
IOUTA2
27
DGND
DGND
CLKGND
57
SDENB
58
19
26
18
DVDD
AVDD
AGND
DEVICE INFORMATION
4
80
DB9
84
DVDD
DB10
85
DGND
DB11
86
82
DB12
87
81
DVDD
DGND
88
DB13
89
DB14
90
94
91
PHSTR
95
DGND
RESETB
96
DB15 (MSB)
SLEEP
97
92
TESTMODE
98
93
DGND
QFLAG
99
DVDD
100
PIN ASSIGNMENTS FOR THE DAC5686
DAC5686
www.ti.com
SLWS147B – APRIL 2003 – REVISED AUGUST 2004
DEVICE INFORMATION (continued)
Terminal Functions (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
BIASJ
13
CLK1
59
I/O Full-scale output current bias
I
External clock input; data clock input
CLK1C
60
I
Complementary external clock input; data clock input
CLK2
62
I
External clock input; sample clock for the DAC (optional if PLL disabled)
CLK2C
63
I
Complementary external clock input; sample clock for the DAC (optional if PLL disabled)
CLKGND
58, 64
CLKVDD
61
DA[15:0]
34–36,
39–43,
48–55
I
A-channel data bits 0 through 15
DA15 is most significant data bit (MSB).
DA0 is least significant data bit (LSB).
DB[0:15]
71–78,
83–87,
90–92
I
B-channel data bits 0 through 15
DB15 is most significant data bit (MSB).
DB0 is least significant data bit (LSB).
Note: The order of the B data bus can be reversed by register rev_bbus.
DGND
27, 38, 45,
57, 69, 81,
88, 93, 99
Digital ground return
DVDD
26, 32, 37,
44, 56, 68,
82, 89, 100
Digital supply voltage
EXTIO
11
EXTLO
IOUTA1
Ground return for internal clock buffer
Internal clock buffer supply voltage
I
Used as external reference input when internal reference is disabled (i.e., EXTLO connected to AVDD).
Used as internal reference output when EXTLO = AGND, requires a 0.1-µF decoupling capacitor to
AGND when used as reference output
15
I
Internal reference ground. Connect to AVDD to disable the internal reference
21
O
A-channel DAC current output. Full scale when all input bits are set to 1
IOUTA2
20
O
A-channel DAC complementary current output. Full scale when all input bits are set to 0
IOUTB1
5
O
B-channel DAC current output. Full scale when all input bits are set to 1
IOUTB2
6
O
B-channel DAC complementary current output. Full scale when all input bits are set to 0
IOGND
47, 79
IOVDD
46, 80
LPF
66
PHSTR
94
PLLGND
65
PLLVDD
67
PLLLOCK
70
O
PLL lock status bit. In PLL clock mode, PLLLOCK is high when PLL is locked to the input clock. In
external clock mode, PLLLOCK outputs the input rate clock.
QFLAG
98
O
Used in the interleaved data input mode: When the qflag register bit is 1, the QFLAG pin is used as an
output to identify the interleaved data sequence. QFLAG high identifies the data as channel B. Pin can
be left open when not used.
RESETB
95
I
Resets the chip when low
SCLK
29
I
Serial interface clock
SDENB
28
I
Active-low serial data enable, always an input to the DAC5686
SDIO
30
I/O Bidirectional serial-port data in the three-pin serial interface mode. Input-only serial data in the four-pin
serial interface mode.
SDO
31
O
High-impedance state (the pin is not used) in the three-pin serial interface mode. Serial-port output data
in the four-pin serial interface mode.
SLEEP
96
I
Asynchronous hardware power-down input. Active high. Internal pulldown
TESTMODE
97
I
TESTMODE is DGND for the user.
Digital I/O ground return
Digital I/O supply voltage
I/O PLL loop filter connection. Can be left open or connected to GND if PLL is not used (PLLVDD = 0 V).
I
The PHSTR pin has two functions. When the sync_phstr register is 0, a high on the PHSTR pin resets
the NCO phase accumulator. When the sync_phstr register is 1, a PHSTR pin low-to-high transition
sets the divided clock phase in external clock mode, and a high on the PHSTR pin resets the NCO
phase accumulator.
Ground return for internal PLL
PLL supply voltage. When PLLVDD is 0 V, the PLL is disabled.
5
DAC5686
www.ti.com
SLWS147B – APRIL 2003 – REVISED AUGUST 2004
DEVICE INFORMATION (continued)
Terminal Functions (continued)
TERMINAL
NAME
NO.
TxENABLE
I/O
DESCRIPTION
I
TxENABLE is used in interleaved mode. The rising edge of TxENABLE synchronizes the data of
channels A and B. The first data after the rising edge of TxENABLE is treated as A data, while the next
data is treated as B data and so on. In any mode, TxENABLE being low sets DAC outputs to midscale.
Internal pulldown
33
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
Supply voltage range
AVDD (2)
–0.5 V to 4 V
DVDD (3)
–0.5 V to 2.3 V
CLKVDD (2)
–0.5 V to 4 V
IOVDD (2)
–0.5 V to 4 V
PLLVDD (2)
–0.5 V to 4 V
Voltage between AGND, DGND, CLKGND, PLLGND, and IOGND
–0.5 V to 0.5 V
AVDD to DVDD
–0.5 V to 2.6 V
DA[15:0] (3)
–0.5 V to IOVDD + 0.5 V
DB[15:0] (3)
–0.5 V to IOVDD + 0.5 V
SLEEP (3)
–0.5 V to IOVDD + 0.5 V
CLK1, CLK2, CLK1C, CLK2C (3)
Supply voltage range
–0.5 V to CLKVDD + 0.5 V
RESETB (3)
–0.5 V to IOVDD + 0.5 V
LPF (3)
–0.5 V to PLLVDD + 0.5 V
IOUT1, IOUT2 (2)
–1 V to AVDD + 0.5 V
EXTIO, BIASJ (2)
–0.5 V to AVDD + 0.5 V
EXTLO (2)
–0.5 V to IOVDD + 0.5 V
±20 mA
Peak input current (any input)
Operating free-air temperature range, TA: DAC5686I
–40°C to 85°C
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds
(1)
(2)
(3)
260°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Measured with respect to AGND
Measured with respect to DGND
ELECTRICAL CHARACTERISTICS (DC SPECIFICATIONS) (1)
over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V,
DVDD = 1.8 V, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Resolution
MIN
TYP
MAX
UNIT
16
DC Accuracy (2)
INL
Integral nonlinearity
±12
1 LSB = IOUTFS/216, TMIN to TMAX
1.84e–4
DNL
±9
Differential nonlinearity
1.37e–4
(1)
(2)
6
Specifications subject to change without notice.
Measured differential across IOUTA1 and IOUTA2 or IOUTB1 and IOUTB2 with 25 Ω each to AVDD
LSB
IOUTFS
LSB
IOUTFS
DAC5686
www.ti.com
SLWS147B – APRIL 2003 – REVISED AUGUST 2004
ELECTRICAL CHARACTERISTICS (DC SPECIFICATIONS) (continued)
over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V,
DVDD = 1.8 V, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog Output
Coarse gain linearity (INL)
±0.016
LSB = 1/10th of full scale
±3
Fine gain linearity (INL)
Offset error
Gain error
Gain mismatch
Mid-code offset
0.7
With internal reference
0.7
With internal reference, dual DAC,
SSB mode
IOUTFS = 20 mA
LSB
0.003
Without internal reference
Full-scale output current (3)
Output compliance range (4)
LSB
–2
%FSR
%FSR
2
%FSR
2
20
mA
AVDD – 0.5
AVDD + 0.5
Output resistance
Output capacitance
V
300
kΩ
5
pF
Reference Output
Reference voltage
1.14
Reference output current (5)
1.2
1.26
100
V
nA
Reference Input
VEXTIO
Input voltage range
0.1
Input resistance
1.25
V
1
MΩ
Small-signal bandwidth
2.5
kHz
Input capacitance
100
pF
±3
ppm of
FSR/°C
Temperature Coefficients
Offset drift
Gain drift
Without internal reference
±15
With internal reference
±40
ppm of
FSR/°C
±25
ppm/°C
Reference voltage drift
Power Supply
AVDD
Analog supply voltage
DVDD
Digital supply voltage
CLKVDD Clock supply voltage
IOVDD
I/O supply voltage
PLLVDD
PLL supply voltage
IAVDD
Analog supply current
IDVDD
Digital supply current
ICLKVDD
Clock supply current
IPLLVDD
PLL supply current
IIOVDD
IO supply current
(3)
(4)
(5)
3
3.3
3.6
V
1.65
1.8
1.95
V
3
3.3
3.6
V
3.6
V
3.6
V
1.65
3
Single (quad) DAC mode;
including output current through
load resistor, mode 7
3.3
30
mA
Dual DAC mode; including output
current through load resistor,
mode 11
fDATA = 125 MSPS, SSB mode,
Fupdate = 500 MSPS, 40-MHz IF
55
242
mA
10
mA
28
mA
<3
mA
Nominal full-scale current, IOUTFS , equals 16× the IBIAS current.
The upper limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown,
resulting in reduced reliability of the DAC5686 device. The lower limit of the output compliance is determined by the load resistors and
full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.
Use an external buffer amplifier with high-impedance input to drive any external load.
7
DAC5686
www.ti.com
SLWS147B – APRIL 2003 – REVISED AUGUST 2004
ELECTRICAL CHARACTERISTICS (DC SPECIFICATIONS) (continued)
over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V,
DVDD = 1.8 V, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IAVDD
Sleep mode, AVDD supply current
1
mA
IDVDD
Sleep mode, DVDD supply current
4
mA
ICLKVDD
Sleep mode, CLKVDD supply
current
2
mA
0.5
mA
0.25
mA
Sleep mode
IPLLVDD
Sleep mode, PLLVDD supply
current
IIOVDD
Sleep mode, IOVDD supply current
PD
Power dissipation
Mode 1 (6) AVDD = 3.3 V,
DVDD = 1.8 V
215
Mode 2 (7) AVDD = 3.3 V,
DVDD = 1.8 V
495
Mode 5 (8) AVDD = 3.3 V,
DVDD = 1.8 V
445
Mode 7 (9) AVDD = 3.3 V,
DVDD = 1.8 V
754
Mode 9 (10) AVDD = 3.3 V,
DVDD = 1.8 V
547
Mode 11 (11) AVDD = 3.3 V,
DVDD = 1.8 V
855
mW
950
APSRR
Power supply rejection ratio
–0.2
0.2
%FSR/V
DPSRR
Power supply rejection ratio
–0.2
0.2
%FSR/V
(6)
(7)
(8)
(9)
(10)
(11)
Mode 1: Dual DAC mode, fully bypassed, FDAC = 160 MSPS, fOUT = 20 MHz
Mode 2: Dual DAC mode, 2× interpolation, FDAC = 320 MSPS, fOUT = 20 MHz
Mode 5: Quadrature modulation mode, 4× interpolation, fs/4 mixing, FDAC = 320 MSPS, fOUT = 100 MHz
Mode 7: Quadrature modulation mode, 4× interpolation, NCO running at 320 MHz, FDAC = 320 MSPS, fOUT = 100 MHz
Mode 9: SSB modulation mode, 4× interpolation, fs/4 mixing, FDAC = 320 MSPS, fOUT = 100 MHz
Mode 11: SSB modulation mode, 4× interpolation, NCO running at 320 MHz, fOUT = 100 MHz, maximum operating condition
ELECTRICAL CHARACTERISTICS (AC SPECIFICATIONS) (1)
over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, IOVDD = 3.3 V, DVDD = 1.8 V,
IOUTFS = 20 mA, external clock mode, differential transformer-coupled output, 50-Ω doubly terminated load (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog Output
fCLK
Maximum output update rate
ts(DAC)
Output settling time to 0.1%
tpd
tr(IOUT)
(2)
tf(IOUT) (2)
500
Mid-scale transition
MSPS
12
ns
Output propagation delay
2.5
ns
Output rise time 10% to 90%
2.5
ns
Output fall time 90% to 10%
2.5
ns
AC Performance—1:1 Impedance-Ratio Transformer
First Nyquist zone < fDATA/2, 4× interpolation, dual DAC mode,
fDATA = 52 MSPS, fOUT = 14 MHz, TA = 25°C
SFDR
First Nyquist zone < fDATA/2, 4× interpolation, dual DAC mode,
fDATA = 160 MSPS, fOUT = 20 MHz, full bypass,TA = TMIN to
Spurious free dynamic range TMAX for MIN, 25°C for TYP, IOVDD = 1.8 V for TYP
2× interpolation, dual DAC mode, fDATA = 160 MSPS, fOUT =
41 MHz, TA = 25°C, IOVDD = 1.8 V
2× interpolation, dual DAC mode, fDATA = 160 MSPS, fOUT =
61 MHz, TA = 25°C, IOVDD = 1.8 V
(1)
(2)
8
Specifications subject to change without notice
Measured single-ended into 50-Ω load
89
68
79
dBc
72
68
DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
ELECTRICAL CHARACTERISTICS (AC SPECIFICATIONS) (continued)
over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, IOVDD = 3.3 V, DVDD = 1.8 V,
IOUTFS = 20 mA, external clock mode, differential transformer-coupled output, 50-Ω doubly terminated load (unless otherwise
noted)
PARAMETER
SNR
ACLR
IMD3
IMD
Signal-to-noise ratio
Adjacent channel power ratio
Third-order two-tone
intermodulation
Four-tone intermodulation
TEST CONDITIONS
MIN
TYP
First Nyquist zone < fDATA/2, fDATA = 100 MSPS,
fOUT = 5 MHz, IOVDD = 1.8 V, fDAC = 400 MSPS
80
First Nyquist zone < fDATA/2, fDATA = 78 MSPS,
fOUT = 15.6 MHz, 15.8 MHz, 16.2 MHz, 16.4 MHz,
IOVDD = 1.8 V, fDAC = 314 MSPS
72
Single carrier W-CDMA with 3.84-MHz BW, 5-MHz spacing,
centered at IF, TESTMODEL 1, 10 ms, fDATA = 122.88 MSPS,
baseband, dual DAC, 2× interpolation,
fOUT = 245 MSPS
72
Single carrier W-CDMA with 3.84-MHz BW, 5-MHz spacing,
centered at IF, TESTMODEL 1, 10 ms, fDATA = 76.8 MSPS, IF
= 19.2 MHz, dual DAC, 2× interpolation,
fOUT = 153.6 MSPS
77
Single carrier W-CDMA with 3.84-MHz BW, 5-MHz spacing,
centered at IF, TESTMODEL 1, 10 ms, fDATA = 122.88 MSPS,
IF = 30.72 MHz, dual DAC, 2× interpolation, fDAC = 245 MSPS
76
Single carrier W-CDMA with 3.84-MHz BW, 5-MHz spacing,
centered at IF, TESTMODEL 1, 10 ms, fDATA = 61.44 MSPS,
IF = 61.44 MHz, quad mode, fs/4, 4×
interpolation, fDAC = 245 MSPS
73
Two-carrier W-CDMA with 3.84-MHz BW, 5-MHz spacing,
centered at IF, TESTMODEL 1, 10 ms, fDATA = 122.88 MSPS,
IF = 30.72 MHz, dual DAC, 2× interpolation, fDAC = 245 MSPS
72
Four-carrier W-CDMA with 3.84-MHz BW, 5-MHz spacing,
centered at IF, TESTMODEL 1, 10 ms, fDATA = 121.88 MSPS,
complex IF - 30.72 MHz, quad mode, fs/4, 4× interpolation, IF
= 92.16 MHz
64
fDATA = 160 MSPS, fOUT = 60.1 and 61.1 MHz, 2× interpolation,
320 MSPS, IOVDD = 1.8 V, each tone at –6 dBFS
74
fDATA = 100 MSPS, fOUT = 15.1 and 16.1 MHz, 2× interpolation,
200 MSPS, IOVDD = 1.8 V, each tone at –6 dBFS
84
fDATA = 100 MSPS, fOUT = 15.6 MHz, 15.8 MHz, 16.2 MHz,
16.4 MHz, 4× interpolation, 400 MSPS, IOVDD = 1.8 V, each
tone at –12 dBFS
85
MAX
UNIT
dB
dB
dBc
dBc
ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) (1)
over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8
V, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CMOS Interface
VIH
High-level input voltage
2
3
VIL
Low-level input voltage
0
0
IIH
High-level input current
IIL
Low-level input current
V
–40
40
µA
–40
40
µA
Input capacitance
VOH
(1)
High-level output voltage,
PLLLOCK, SDO, SDIO (I/O)
V
0.8
5
IL = –100 µA
IOVDD – 0.2
IL = –8 mA
0.8 × IOVDD
pF
V
Specifications subject to change without notice.
9
DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) (continued)
over operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8
V, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER
VOL
Low-level output voltage,
PLLLOCK, SDO, SDIO (I/O)
TEST CONDITIONS
MIN
TYP
IL = 100 µA
MAX
0.2
0.22 × IOVDD
IL = 8 mA
UNIT
V
PLL
Input data rate supported
Phase noise
1
160
At 600-kHz offset, measured at
DAC output, 25-MHz 0-dBFS tone,
fDATA = 125 MSPS, 4× interpolation
128
At 6-MHz offset, measured at DAC
output, 25-MHz 0-dBFS tone, fDATA
= 125 MSPS, 4× interpolation
151
VCO minimum frequency
PLL_rng = 00 (nominal)
VCO maximum frequency
PLL_rng = 00 (nominal)
MSPS
dBc/Hz
120
500
MHz
MHz
NCO
NCO clock (DAC update rate)
320
MHz
Serial Port Timing
tsu(SDENB)
Setup time, SDENB to rising edge
of SCLK
20
ns
tsu(SDIO)
Setup time, SDIO valid to rising
edge of SCLK
10
ns
th(SDIO)
Hold time, SDIO valid to rising
edge of SCLK
5
ns
tSCLK
Period of SCLK
100
ns
tSCLKH
High time of SCLK
40
ns
tSCLKL
Low time of SCLK
40
ns
td(Data)
Data output delay after falling
edge of SCLK
10
ns
Parallel Data Input Timing (PLL Mode, CLK1 Input)
tsu(DATA)
Setup time, data valid to rising
edge of CLK1
0.3
–0.4
ns
th(DATA)
Hold time, data valid after rising
edge of CLK1
1.2
0.6
ns
–0.4
ns
0.6
ns
Parallel Data Input Timing (Dual Clock Mode, CLK1 and CLK2 Input)
tsu(DATA)
Setup time, data valid to rising
edge of CLK1
th(DATA)
Hold time, data valid after rising
edge of CLK1
Timing Parallel Data Input (External Clock Mode, CLK2 Input)
tsu(DATA)
Setup time, DATA valid to rising
edge of PLLLOCK
High-impedance load on PLLLOCK.
Note that tsu increases with a
lower-impedance load.
4.6
3
ns
th(DATA)
Hold time, DATA valid after rising
edge of PLLLOCK
High-impedance load on PLLLOCK.
Note that th decreases (becomes
more negative) with a
lower-impedance load.
–0.8
–2.4
ns
td(PLLLock)
Delay from CLK2 rising edge to
PLLLOCK rising edge
High-impedance load on PLLLOCK.
Note that PLLLOCK delay increases with a lower-impedance
load.
2.5
4.2
10
6.5
ns
DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
TYPICAL CHARACTERISTICS
INL – Integral Nonlinearity Error – LSB
INTEGRAL NONLINEARITY
vs
INPUT CODE
10
8
6
4
2
0
−2
−4
−6
−8
−10
0
10000
20000
30000
40000
50000
60000
70000
50000
60000
70000
Input Code
Figure 1.
DNL – Differential Nonlinearity Error – LSB
DIFFERENTIAL NONLINEARITY
vs
INPUT CODE
15
13
11
9
7
5
3
1
−1
0
10000
20000
30000
40000
Input Code
Figure 2.
11
DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
TYPICAL CHARACTERISTICS (continued)
IN-BAND SPURIOUS-FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY
SFDR – In-Band Spurious-Free Dynamic Range – dBc
SINGLE-TONE SPECTRUM
10
fdata = 125 MSPS
fIN = 20 MHz
Dual DAC Mode
4 Interpolation
0
−10
Power – dBm
−20
−30
−40
−50
−60
−70
−80
−90
12
50
100
150
200
250
fdata = 125 MSPS
Dual DAC Mode
4 Interpolation
In-band = 0–62.5 MHz
85
80
0 dBfS
–6 dBfS
–12 dBfS
75
70
65
60
55
50
10
15
20
25
30
35
40
f – Frequency – MHz
fO – Output Frequency – MHz
Figure 3.
Figure 4.
OUT-OF-BAND SPURIOUS-FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY
SINGLE-TONE SPECTRUM
45
50
10
80
fdata = 125 MSPS
Dual DAC Mode
4 Interpolation
Out-of-Band = 62.5 MHz–250 MHz
75
fdata = 75 MSPS
fIN = None
NCO On
fOUT = 100 MHz
Quad Mode
4 Interpolation
0
−10
70
−20
0 dBfS
65
Power – dBm
SFDR – Out-of-Band Spurious-Free Dynamic Range – dBc
0
90
–6 dBfS
60
–12 dBfS
55
−30
−40
−50
−60
50
−70
45
−80
−90
40
10
15
20
25
30
35
40
45
50
0
25
50
75
100
fO – Output Frequency – MHz
f – Frequency – MHz
Figure 5.
Figure 6.
125
150
DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
TYPICAL CHARACTERISTICS (continued)
TWO-TONE IMD3
vs
OUTPUT FREQUENCY
TWO-TONE IMD PERFORMANCE
0
95
fdata = 150 MSPS
Dual DAC Mode
2 Interpolation
−20
± 0.5 MHz
85
80
−30
Power – dBm
Two-Tone IMD3 – dBc
90
−10
± 2 MHz
75
fdata = 150 MSPS
fIN1 = 19.5 MHz
fIN2 = 20.5 MHz
Dual DAC Mode
2 Interpolation
−40
−50
−60
−70
−80
70
−90
−100
10
65
10
15
20
25
30
35
40
45
50
55
60
15
25
Figure 7.
Figure 8.
TWO-TONE IMD3
vs
OUTPUT FREQUENCY
TWO-TONE IMD PERFORMANCE
30
0
90
fdata = 80 MSPS
NCO On
Quad Mode
4 Interpolation
85
−10
−20
80
−30
Power – dBm
Two-Tone IMD3 – dBc
20
f – Frequency – MHz
fO – Output Frequency – MHz
75
± 0.5 MHz
70
± 2 MHz
fdata = 80 MSPS
fIN1 = –0.5 MHz
fIN2 = 0.5 MHz
NCO = 70 MHz
Quad Mode
4 Interpolation
−40
−50
−60
−70
65
−80
60
−90
55
10
30
50
70
90
110
fO – Output Frequency – MHz
Figure 9.
130
150
−100
60
65
70
75
80
f – Frequency – MHz
Figure 10.
13
DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
TYPICAL CHARACTERISTICS (continued)
TWO-TONE IMD PERFORMANCE
WCDMA TEST MODEL 1: SINGLE CARRIER
−20
0
fdata = 80 MSPS
fIN1 = –0.5 MHz
fIN2 = 0.5 MHz
NCO = 150 MHz
Quad Mode
4 Interpolation
−10
−20
−40
fdata = 122.88 MSPS
fIN = 30.72 MHz
ACLR = 78.6 dB
4 Interpolation
Dual DAC Mode
−50
Power – dBm
Power – dBm
−30
−30
−40
−50
−60
−70
−60
−70
−80
−90
−100
−80
−110
−90
−120
−100
140
145
150
155
−130
18
160
22
−40
38
WCDMA TEST MODEL 1: DUAL CARRIER
WCDMA TEST MODEL 1: DUAL CARRIER
42
−20
fdata = 122.88 MSPS
fIN = 30.72 MHz
ACLR = 71.69 dB
4 Interpolation
Dual DAC Mode
−30
−40
−70
−80
−90
−60
−70
−80
−90
−100
−110
−100
−120
−110
−130
15
fdata = 122.88 MSPS
fIN = Baseband Complex
ACLR = 69.08 dB
2 Interpolation
Quad Mode
−50
−60
Power – dBm
Power – dBm
34
Figure 12.
−50
20
25
30
35
f – Frequency – MHz
Figure 13.
14
30
Figure 11.
−20
−30
26
f – Frequency – MHz
f – Frequency – MHz
40
45
−120
46
51
56
61
66
f – Frequency – MHz
Figure 14.
71
76
DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
TYPICAL CHARACTERISTICS (continued)
WCDMA TEST MODEL 1: FOUR CARRIER
WCDMA TEST MODEL 1: DUAL CARRIER
−10
−20
−30
−10
fdata = 122.88 MSPS
fIN = –30.72 MHz Complex
ACLR = 63.29 dB
4 Interpolation
Quad Mode
fdata = 122.88 MSPS
fIN = 30.72 MHz Complex
ACLR = 58.58 dB
4 Interpolation
Quad Mode
−30
Power – dBm
−50
−60
−70
−50
−70
−80
−90
−90
−100
−110
72
77
82
87
92
97
102
107
−110
138
112
143
148
153
158
f – Frequency – MHz
f – Frequency – MHz
Figure 15.
Figure 16.
163
168
VCO GAIN
vs
VCO FREQUENCY
600
Boost for 0%
500
GVCO – VCO Gain – MHz/V
Power – dBm
−40
400
300
Boost for 45%
200
100
Boost for 30%
Boost for 15%
0
0
100
200
300
400
500
600
700
fVCO – VCO Frequency – MHz
Figure 17.
15
DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
DETAILED DESCRIPTION
Dual-Channel Mode
In dual-channel mode, interpolation filtering increases the DAC update rate, thereby reducing sinx/x rolloff and
enabling relaxed analog post-filtering, and is useful for baseband I and Q modulation or two-channel low-IF
signals. The dual-channel mode is set by mode[1:0] = 00 in the config_lsb register. Figure 18 shows the data
path architecture in dual-channel mode. The A- and B-data paths, which are independent, consist of four
cascaded half-band interpolation filters, followed by an optional inverse sinc filter. Interpolation filtering is
selected as 2×, 4×, 8×, or 16× by sel[1:0] in the config_lsb register. Magnitude spectral responses of each filter
are presented following in the section on digital filtering. Full bypass of all the interpolation filters is selected by
fbypass in the config_lsb register. The inverse sinc filter is intended for use in single-sideband and quadrature
modulation modes and is of limited benefit in dual-channel mode.
A
Offset
Fdata
DEMUX
FIR1
FIR2
2Fdata
DA[15:0]
FIR3
4Fdata
FIR4
FIR5
16Fdata
8Fdata
2 – 16 Fdata
2
x
sin(x)
16-Bit
DAC
IOUTA1
16-Bit
DAC
IOUTB1
IOUTA2
A Gain
B Gain
FIR1
FIR2
2Fdata
DB[15:0]
2
FIR3
4Fdata
FIR4
8Fdata
FIR5
16Fdata
x
sin(x)
IOUTB2
B
Offset
Figure 18. Data Path in Dual-Channel Mode
Single-Sideband Mode
Single-sideband (SSB) mode provides optimum interfacing to analog quadrature modulators. The SSB mode is
selected by mode[1:0] = 01 in the config_lsb register. Figure 19 shows the data path architecture in
single-sideband mode. Complex baseband I and Q are input to the DAC5686, which in turn performs a complex
mix, resulting in Hilbert transform pairs at the outputs of the DAC5686's two DACs. NCO mixing frequencies are
programmed through 32-bit freq (4 registers); 16-bit phase adjustments are programmed through phase (2
registers). The NCO operates at the DAC update rate; thus, increased amounts of interpolation allow for higher
IFs. More details for the NCO are provided as follows. For mixing to Fdac/4, DAC5686 provides a specific
architecture that exploits the {… –1 0 1 0 …} resultant streams from sin and cos; the NCO is shut off in this mode
to conserve power. Fdac/4 mix mode is implemented by deasserting nco in register config_msb while in
single-sideband or quadrature modulation mode.
16
DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
DETAILED DESCRIPTION (continued)
Fdata
cos
DEMUX
A
Offset
+
DA[15:0]
2 – 16
2 – 16 Fdata
FIR5
A
sin
DB[15:0]
x
sin(x)
+/−
A Gain
+
B Gain
16-Bit
DAC
IOUTA1
16-Bit
DAC
IOUTB1
IOUTA2
2 – 16
sin
B
cos
x
sin(x)
IOUTB2
+
B
Offset
Figure 19. Data Path in SSB Mode
Figure 20 shows the DAC5686 interfaced to an RF quadrature modulator. The outputs of the complex mixer
stage can be expressed as:
A(t) = I(t)cos(ωct) – Q(t)sin(ωct) = m(t)
B(t) = I(t)sin(ωct) + Q(t)cos(ωct) = mh(t)
where m(t) and mh(t) connote a Hilbert transform pair. Upper single-sideband up-conversion is achieved at the
output of the analog quadrature modulator, whose output is expressed as:
IF(t) = A(t)cos(ωc+ ω1)t – B(t)sin(ωc+ ω1)t
Flexibility is provided to the user by allowing for the selection of –B(t) out, which results in lower-sideband
up-conversion. This option is selected by ssb in the config_msb register. Figure 21 depicts the magnitude
spectrum along the signal path during single-sideband up-conversion for real input. Further flexibility is provided
to the user by allowing for the inverse of sin to be used in the complex mixer by programming rspect in the
config_usb register. The four combinations of rspect and ssb allow the user to select one of four complex
spectral bands to input to a quadrature modulator (see Figure 22).
17
DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
DETAILED DESCRIPTION (continued)
cos(ωct)
I
DAC5686
+
A(t) = I(t)cos(ωct) – Q(t)sin(ωct)
A
sin(ωct)
DAC
−
Q
cos(ωLOt)
IF(t) = I(t)cos(ωc+ ωLO)t
– Q(t)sin(ωc+ ωLO)t
–sin(ωct)
DAC
+
0°
–cos(ωct)
sin(ωLOt) 90°
B
+
Quadrature
Modulator
LO
B(t) = –I(t)sin(ωct) – Q(t)cos(ωct)
Figure 20. DAC5686 in SSB Mode With Quadrature Modulator
Real Input
Spectrum
to DAC5686
ω
0
Complex Input
Spectrum
to Quadrature Modulator
0
ωc
ω
ωLO + ωc
ω
Output Spectrum
to Quadrature Modulator
ωLO – ωc
ωLO
Figure 21. Spectrum After First and Second Up-Converson for Real Input
18
DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
DETAILED DESCRIPTION (continued)
Complex Input
Spectrum
to DAC5686
0
Complex Input
Spectrums
to Quadrature
Modulator
–ωc
–ωc
–ωc
0
0
0
ω
ωc
ωc
ωc
ω
ω
ω
rspect = 0
ssb = 0
rspect = 0
ssb = 1
rspect = 1
ssb = 1
rspect = 1
–ωc
0
ωc
ω
ssb = 0
Figure 22. Spectrum After First and Second Up-Converson for Complex Input
To compensate for the sinx/x rolloff of the zero-order hold of the DACs, the DAC5686 provides an inverse sinc
FIR, which provides high-frequency boost. The magnitude spectral response of this filter is presented in the
Digital Filters section.
DAC Gain and Offset Control
Unmatched gains and offsets at the RF quadrature modulator result in unwanted sideband and local-oscillator
feedthrough. Gain and offset imbalances between the two DACs are compensated for by programming
daca_gain, dacb_gain, daca_offset, and dacb_offset in registers 0x0A through 0x0F (see the following
register descriptions). The DAC gain value controls the full-scale output current. The DAC offset value adds a
digital offset to the digital data before digital-to-analog conversion. Care must be taken when using the offset by
restricting the dynamic range of the digital signal to prevent saturation when the offset value is added to the
digital signal.
Quadrature Modulation Mode
In quadrature modulation mode, on-chip mixing of complex I and Q inputs provides the final baseband-to-IF
up-conversion. Quadrature modulation mode is selected by mode[1:0] = 10 in the config_lsb register. Figure 23
shows the data path architecture in quadrature modulation mode. Complex baseband I and Q from the
ASIC/FPGA are input to the DAC5686, which in turn quadrature modulates I and Q to produce the final IF
single-sideband spectrum. DAC A is held constant, while DAC B presents the DAC5686 quadrature modulator
mode output.
19
DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
DETAILED DESCRIPTION (continued)
NCO mixing frequencies are programmed through 32-bit freq (4 registers); 16-bit phase adjustments are
programmed through phase (2 registers). The NCO operates at the DAC update rate; thus, increased amounts
of interpolation allow for higher IFs. More details for the NCO are provided in the NCO section. For mixing to
Fdac/4, the DAC5686 provides a specific architecture that exploits the {… –1 0 1 0 …} resultant streams from sin
and cos; the NCO is shut off in this mode to conserve power. Fdac/4 mix mode is implemented by deasserting
nco in register config_msb while in single-sideband or quadrature modulation mode.
cos
sin
Fdata
DEMUX
FIR1
FIR2
FIR3
FIR4
2 – 16 Fdata
DA[15:0]
2
2
2
2
+
FIR5
x
sin(x)
FIR1
FIR2
FIR3
FIR4
16-Bit
DAC
B
Offset
2
2
IOUTB2
+/−
DB[15:0]
2
IOUTB1
B Gain
2
sin
cos
Figure 23. Data Path in Quadrature Modulation Mode
In quadrature modulation mode, only one output from the complex mixer stage is routed to the B DAC. The
output can be expressed as:
B(t) = I(t)sin(ωct) + Q(t)cos(ωct)
or
B(t) = I(t)cos(ωct) – Q(t)sin(ωct)
Single-sideband up-conversion is achieved when I and Q are Hilbert transform pairs. Upper- or lower-sideband
up-conversion is selected by ssb in the config_msb register, which selects the output from the mixer stage that
is routed out.
The offset and gain features for the B DAC, as previously described, are functional in the quadrature mode.
Serial Interface
The serial port of the DAC5686 is a flexible serial interface that communicates with industry-standard
microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the
operating modes of the DAC5686. It is compatible with most synchronous transfer formats and can be configured
as a 3- or 4-pin interface by sif4 in register config_msb. In both configurations, SCLK is the serial-interface
input clock and SDENB is the serial-interface enable. For the 3-pin configuration, SDIO is a bidirectional pin for
both data-in and data-out. For the 4-pin configuration, SDIO is data-in only and SDO is data-out only.
20
DAC5686
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DETAILED DESCRIPTION (continued)
Each read/write operation is framed by signal SDENB (serial data enable bar) asserted low for 2 to 5 bytes,
depending on the data length to be transferred (1–4 bytes). The first frame byte is the instruction cycle, which
identifies the following data transfer cycle as read or write, how many bytes to transfer, and the address to/from
which to transfer the data. Table 1 indicates the function of each bit in the instruction cycle and is followed by a
detailed description of each bit. Frame bytes 2 through 5 comprise the data to be transferred.
Table 1. Instruction Byte of the Serial Interface
MSB
LSB
Bit
7
6
5
4
3
2
1
0
Description
R/W
N1
N0
–
A3
A2
A1
A0
R/W: Identifies the following data transfer cycle as a read or write operation. A high indicates a read operation
from the DAC5686 and a low indicates a write operation to the DAC5686.
N[1:0]: Identifies the number of data bytes to be transferred per Table 2. Data is transferred MSB-first.
Table 2. Number of Transferred Bytes Within One
Communication Frame
N1
N0
0
0
DESCRIPTION
Transfer 1 byte
0
1
Transfer 2 bytes
1
0
Transfer 3 bytes
1
1
Transfer 4 bytes
A4: Unused
A[3:0]: Identifies the address of the register to be accessed during the read or write operation. For multibyte
transfers, this address is the starting address and the address decrements. Note that the address is written to the
DAC5686 MSB-first.
Serial-Port Timing Diagrams
Figure 24 shows the serial-interface timing diagram for a DAC5686 write operation. SCLK is the serial-interface
clock input to the DAC5686. Serial data enable SDENB is an active-low input to the DAC5686. SDIO is serial
data-in. Input data to the DAC5686 is clocked on the rising edges of SCLK.
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DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
Instruction Cycle
SDENB
Data Transfer Cycle(s)
SCLK
SDIO
R/W N1 N0
−
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
ts(SDENB)
tSCLK
SDENB
SCLK
SDIO
tSCLKL
ts(SDIO)
th(SDIO)
tSCLKH
Figure 24. Serial-Interface Write Timing Diagram
Figure 25 shows the serial-interface timing diagram for a DAC5686 read operation. SCLK is the serial-interface
clock input to the DAC5686. Serial data enable SDENB is an active-low input to the DAC5686. SDIO is serial
data-in during the instruction cycle. In the 3-pin configuration, SDIO is data-out from the DAC5686 during the
data transfer cycle(s), while SDO is in a high-impedance state. In the 4-pin configuration, SDO is data-out from
the DAC5686 during the data transfer cycle(s). SDO is never placed in the high-impedance state in the four-pin
configuration.
Data Transfer Cycle(s)
Instruction Cycle
SDENB
SCLK
SDIO
R/W N1 N0
−
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0
D7 D6 D5 D4 D3 D2 D1 D0 0
SDO
4-Pin Configuration
Output
3-Pin Configuration
Output
SDENB
SCLK
SDIO
SDO
Data n
Data n−1
td(Data)
Figure 25. Serial-Interface Read Timing Diagram
22
DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
Clock Generation
In the DAC5686, the internal clocks (1×, 2×, 4×, 8×, and 16×, as needed) for the logic, FIR interpolation filters,
and DAC are derived from a clock at either the input data rate using an internal PLL (PLL clock mode) or the
DAC output sample rate (external clock mode). Power for the internal PLL blocks (PLLVDD and PLLGND) is
separate from power for the other clock generation blocks (CLKVDD and CLKGND), thus minimizing phase noise
within the PLL.
The DAC5686 has three clock modes for generating the internal clocks (1×, 2×, 4×, 8×, and 16×, as needed) for
the logic, FIR interpolation filters, and DACs. The clock mode is set using the PLLVDD pin and dual_clk in
register config_usb. A block diagram for the clock generation circuit is shown in Figure 27.
1. PLLVDD = 0V and dual_clk = 0: EXTERNAL CLOCK MODE
In EXTERNAL CLOCK MODE, the user provides a clock signal at the DAC output sample rate through
CLK2/CLK2C. CLK1/CLK1C and the internal PLL are not used, so the LPF circuit is not applicable. The input
data rate clock and interpolation rate are selected by the registers sel[1:0], and are output through the
PLLLOCK pin. It is common to use the PLLLOCK clock to drive the chip that sends the data to the DAC;
otherwise, there is phase ambiguity regarding how the DAC divides down to the input sample rate clock and
an external clock divider divides down. (For a divide by N, there are N possible phases.) The phase
ambiguity can also be solved by using PHSTR pin with a synchronization signal.
2. PLLVDD = 3.3V (dual_clk can be 0 or 1 and is ignored): PLL CLOCK MODE
Power for the internal PLL blocks (PLLVDD and PLLGND) is separate from power for the other clock
generation blocks (CLKVDD and CLKGND), thus minimizing PLL phase noise.
In PLL CLOCK MODE, the DAC is driven at the input sample rate (unless the data is multiplexed) through
CLK1/CLK1C. CLK2/CLK2C is not used. In this case, there is no phase ambiguity on the clock. The DAC
generates the higher speed DAC sample rate clock using an internal PLL/VCO. In PLL clock mode, the user
provides a differential external reference clock on CLK1/CLK1C.
A type-4 phase-frequency detector (PFD) in the internal PLL compares this reference clock to a feedback
clock and drives the PLL to maintain synchronization between the two clocks. The feedback clock is
generated by dividing the VCO output by 1×, 2×, 4×, or 8× as selected by the prescaler (div[1:0]). The output
of the prescaler is the DAC sample rate clock and is divided down to generate clocks at ÷2, ÷4, ÷8, and ÷16.
The feedback clock is selected by the registers sel[1:0], an then is fed back to the PFD for synchronization
to the input clock. The feedback clock is also used for the data input rate, so the ratio of DAC output clock to
feedback clock sets the interpolation rate of the DAC5686. The PLLLOCK pin is an output that indicates
when the PLL has achieved lock. An external RC low-pass PLL filter is provided by the user at pin LPF. See
the low-pass filter section for filter setting calculations. This is the only mode where the LPF filter applies.
3. PLLVDD = 0V and dual_clk = 1: DUAL CLOCK MODE
In DUAL CLOCK MODE, the DAC is driven at the DAC sample rate through CLK2/CLK2C and at the input
data rate through CLK1/CLK1C. The DUAL CLOCK MODE has the advantage of a clean external clock for
the DAC sampling without the phase ambiguity. The edges of CLK1 and CLK2 must be aligned to within
±t_align (See Figure 26), defined as
t _align 1 0.5 ns
2F CLK2
where FCLK2 is the clock frequency of CLK2. For example, t_align = 0.5 ns at FCLK2 = 500 MHz and 1.5 ns at
FCLK2 = 250 MHz.
23
DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
CLK2
CLK1
∆ < talign
D[0:15]
th
ts
T0002-01
Figure 26. DAC and Data Clock Mode
The CDC7005 from Texas Instruments is recommended for providing phase-aligned clocks at different
frequencies for this application.
Table 3 provides a summary of the clock configurations with corresponding data rate ranges.
LPF
DIV[1:0]
CLK1
CLK1C
Charge
Pump
pfd
Clk Buffer
/1
/2
/4
/8
vco
CLK2
CLK2C
PLLVDD
clk_16x
DAC
Sample
Clock
Clk Buffer
/2
clk_8x
/2
clk_4x
/2
clk_2x
/2
clk_1x
PLLVDD
PLLGND
0
CLKVDD
CLKGND
1
s
PLLLOCK
PLLVDD
Data
D[15:0]
SEL[1:0]
Figure 27. Clock-Generation Architecture
Table 3. Clock-Mode Configuration
CLOCK MODE
PLLVDD
DIV[1:0]
SEL[1:0]
DATA RATE (MSPS)
PLLLOCK PIN FUNCTION
Non-interleaved input data; internal PLL off; DA[15:0] data rate matches DB[15:0] data rate.
24
DC to 160
External clk2/clk2c clock ÷ 2
01
DC to 125
External clk2/clk2c clock ÷ 4
10
DC to 62.5
External clk2/clk2c clock ÷ 8
XX
11
DC to 31.25
External clk2/clk2c clock ÷ 16
0V
XX
00
DC to 160
None - held low
0V
XX
01
DC to 125
None - held low
External 2×
0V
XX
00
External 4×
0V
XX
External 8×
0V
XX
External 16×
0V
External dual clock 2×
External dual clock 4×
DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
Table 3. Clock-Mode Configuration (continued)
CLOCK MODE
PLLVDD
DIV[1:0]
SEL[1:0]
DATA RATE (MSPS)
PLLLOCK PIN FUNCTION
External dual clock 8×
0V
XX
10
DC to 62.5
None - held low
External dual clock 16×
0V
XX
11
DC to 31.25
None - held low
External 2×
0V
XX
00
DC to 80
External clk2/clk2c clock ÷ 2
External 4×
0V
XX
01
DC to 80
External clk2/clk2c clock ÷ 4
Interleaved input data on the DA[15:0] input pins; internal PLL off
External 8×
0V
XX
10
DC to 62.5
External clk2/clk2c clock ÷ 8
External 16×
0V
XX
11
DC to 31.25
External clk2/clk2c clock ÷ 16
External dual clock 2×
0V
XX
00
DC to 80
None - held low
External dual clock 4×
0V
XX
01
DC to 62.5
None - held low
External dual clock 8×
0V
XX
10
DC to 31.25
None - held low
External dual clock 16×
0V
XX
11
DC to 15.625
None - held low
Non-interleaved input data; internal PLL on; DA[15:0] data rate matches DB[15:0] data rate.
Internal 2×
3.3 V
00
00
125 to 160
Internal PLL lock indicator
Internal 2×
3.3 V
01
00
62.5 to 125
Internal PLL lock indicator
Internal 2×
3.3 V
10
00
31.25 to 62.5
Internal PLL lock indicator
Internal 2×
3.3 V
11
00
15.63 to 31.25
Internal PLL lock indicator
Internal 4×
3.3 V
00
01
62.5 to 125
Internal PLL lock indicator
Internal 4×
3.3 V
01
01
31.25 to 62.5
Internal PLL lock indicator
Internal 4×
3.3 V
10
01
15.63 to 31.25
Internal PLL lock indicator
Internal 4×
3.3 V
11
01
7.8125 to 15.625
Internal PLL lock indicator
Internal 8×
3.3 V
00
10
31.25 to 62.5
Internal PLL lock indicator
Internal 8×
3.3 V
01
10
15.63 to 31.25
Internal PLL lock indicator
Internal 8×
3.3 V
10
10
7.8125 to 15.625
Internal PLL lock indicator
Internal 8×
3.3 V
11
10
3.9 to 7.8125
Internal PLL lock indicator
Internal 16×
3.3 V
00
11
15.625 to 31.25
Internal PLL lock indicator
Internal 16×
3.3 V
01
11
7.8125 to 15.625
Internal PLL lock indicator
Internal 16×
3.3 V
10
11
3.9062 to 7.8125
Internal PLL lock indicator
Interleaved input data on the DA[15:0] input pins; internal PLL on
Internal 2×
3.3 V
00
00
Not recommended
Internal PLL lock indicator
Internal 2×
3.3 V
01
00
62.5 to 80
Internal PLL lock indicator
Internal 2×
3.3 V
10
00
31.25 to 62.5
Internal PLL lock indicator
Internal 2×
3.3 V
11
00
15.625 to 31.25
Internal PLL lock indicator
Internal 4×
3.3 V
00
01
62.5 to 80
Internal PLL lock indicator
Internal 4×
3.3 V
01
01
31.25 to 62.5
Internal PLL lock indicator
Internal 4×
3.3 V
10
01
15.625 to 31.25
Internal PLL lock indicator
Internal 4×
3.3 V
11
01
7.8125 to 15.625
Internal PLL lock indicator
Internal 8×
3.3 V
00
10
31.25 to 62.5
Internal PLL lock indicator
Internal 8×
3.3 V
01
10
15.625 to 31.25
Internal PLL lock indicator
Internal 8×
3.3 V
10
10
7.8125 to 15.625
Internal PLL lock indicator
Internal 8×
3.3 V
11
10
3.9062 to 7.8125
Internal PLL lock indicator
Internal 16×
3.3 V
00
11
15.625 to 31.25
Internal PLL lock indicator
Internal 16×
3.3 V
01
11
7.8125 to 15.625
Internal PLL lock indicator
Internal 16×
3.3 V
10
11
3.9062 to 7.8125
Internal PLL lock indicator
Internal 16×
3.3 V
11
11
1.9531 to 3.9062
Internal PLL lock indicator
25
DAC5686
www.ti.com
SLWS147B – APRIL 2003 – REVISED AUGUST 2004
Dual-Bus Mode
In dual-bus mode, two separate parallel data streams (I and Q) are input to the DAC5686 on data bus DA and
data bus DB. Dual-bus mode is selected by setting INTERL to 0 in the config_msb register. Figure 28 shows
the DAC5686 data path in dual-bus mode. The dual-bus mode timing diagram is shown in Figure 29 for the PLL
clock mode and in Figure 30 for the external clock mode.
2 – 16 Fdata
Fdata
FIR1
DEMUX
2Fdata
•••
16-Bit
DAC
IOUTA1
16-Bit
DAC
IOUTB1
IOUTA2
2
DA[15:0]
Edge Triggered
Input Latches
2Fdata
DB[15:0]
•••
IOUTB2
2
Figure 28. Dual-Bus Mode Data Path
CLK1
ts(DATA)
th(DATA)
DA[15:0]
A0
A1
A2
A3
AN
AN+1
DB[15:0]
B0
B1
B2
B3
BN
BN+1
Figure 29. Dual-Bus Mode Timing Diagram (PLL Mode)
PLLLOCK
td(PLLLOCK)
CLK2
ts(DATA)
th(DATA)
DA[15:0]
A0
A1
A2
A3
AN
AN+1
DB[15:0]
B0
B1
B2
B3
BN
BN+1
Figure 30. Dual-Bus Mode Timing Diagram (External Clock Mode)
26
DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
Interleave Bus Mode
In interleave bus mode, one parallel data stream with interleaved data (I and Q) is input to the DAC5686 on data
bus DA. Interleave bus mode is selected by setting INTERL to 1 in the config_msb register. Figure 31 shows
the DAC5686 data path in interleave bus mode. The interleave bus mode timing diagram is shown in Figure 32.
2 – 16 Fdata
Fdata
FIR1
2Fdata
•••
16-Bit
DAC
IOUTA1
16-Bit
DAC
IOUTB1
IOUTA2
2
DEMUX
DA[15:0]
Edge Triggered
Input Latches
2Fdata
•••
IOUTB2
2
Figure 31. Interleave Bus Mode Data Path
TxENABLE
ts(TxENABLE)
CLK1 or
PLLLOCK
ts(DATA)
DA[15:0]
th(DATA)
A0
B0
A1
B1
AN
BN
Figure 32. Interleave Bus Mode Timing Diagram Using TxENABLE
Interleaved user data on data bus DA is alternately multiplexed to internal data channels A and B. Data channels
A and B can be synchronized using either the QFLAG pin or the TxENABLE pin. When qflag in register
config_usb is 0, transitions on TxENABLE identify the interleaved data sequence. The first data after the rising
edge of TxENABLE is latched with the rising edge of CLK as channel-A data. Data is then alternately distributed
to B and A channels with successive rising edges of CLK. When qflag is 1, the QFLAG pin is used as an output
to identify the interleaved data sequence. QFLAG high identifies data as channel B (see Figure 33).
27
DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
QFLAG
CLK1 or
PLLLOCK
th(DATA)
ts(DATA)
DA[15:0]
A0
B0
A1
B1
AN
BN
T0001-01
Figure 33. Interleave Bus Mode Timing Diagram Using QFLAG
The dual-clock mode is selected by setting dualclk high in the config_usb register. In this mode, the DAC5686
uses both clock inputs; CLK1/CLK1C is the input data clock, and CLK2/CLK2C is the external clock. The edges
of the two input clocks must be phase-aligned within ±500 ps to function properly.
Clock Synchronization Using the PHSTR Pin in External Clock Mode
In external clock mode, the DAC5686 is clocked at the DAC output sample frequency (CLK2 and CLK2C). For an
interpolation rate N, there are N possible phases for the DAC input clock on the PLLLOCK pin (see Figure 34 for
N = 4).
CLK2
CLK2C
PLLLOCK
T0003-01
Figure 34. Four Possible PLLLOCK Phases for N = 4 in External Clock Mode
To synchronize PLLLOCK input clocks across multiple DAC5686 chips, a sync signal on the PHSTR pin is used.
During configuration of the DAC5686 chips, address sync_phstr in config_msb is set high to enable the
PHSTR input pin as a sync input to the clock dividers generating the input clock. A simultaneous low-to-high
transition on the PHSTR pin for each DAC5686 then forces the input clock on PLLLOCK to start in phase on
each DAC. See Figure 35.
28
DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
1/FPLLLOCK = N/FCLK2
CLK2
CLK2C
PHSTR
th_PHSTR
td_CLK
ts_PHSTR
PLLLOCK
DAC1
D[0:15]
th
ts
T0004-01
Figure 35. Using PHSTR to Synchronize PLLLOCK Input Clock for Multiple DACs in External Clock Mode
The PHSTR transition has a setup and hold time relative to the DAC output sample clock (ts_PHSTR and th_PHSTR)
equal to 50% of the DAC output sample clock period up to a maximum of 1 ns. At 500 MHz, the setup and hold
times are therefore 0.5 ns. The PHSTR signal can remain high after synchronization, or can return low. A new
low-to-high transition resynchronizes the input clock. Note that the PHSTR transition also resets the NCO
accumulator.
Digital Filters
Figure 36 through Figure 39 show magnitude spectrum responses for 2×, 4×, 8×, and 16× FIR interpolation
filtering. The transition band is from 0.4 to 0.6 fDATA with < 0.002-dB pass-band ripple and > 80-dB stop-band
attenuation for all four configurations. The filters are linear phase. The sel field in register config_lsb selects the
interpolation filtering rate as 2×, 4×, 8×, or 16×; interpolation filtering can be completely bypassed by setting
fullbypass in register config_lsb.
Figure 40 shows the spectral correction of the DAC sinx/x rolloff achieved with use of inverse sinc filtering.
Pass-band ripple from 0 to 0.4 fDATA is < 0.03 dB. Inverse sinc filtering is enabled by sinc in register
config_msb.
29
DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
MAGNITUDE
vs
FREQUENCY
20
20
0
0
−20
−20
−40
−40
Magnitude – dB
Magnitude – dB
MAGNITUDE
vs
FREQUENCY
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
−160
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
f/FData
f/FData
Figure 36. Magnitude Spectrum for
2× Interpolation (dB)
Figure 37. Magnitude Spectrum for
4× Interpolation (dB)
MAGNITUDE
vs
FREQUENCY
20
20
0
0
−20
−20
−40
−40
Magnitude – dB
Magnitude – dB
MAGNITUDE
vs
FREQUENCY
−60
−80
−100
−80
−100
−120
−120
−140
−140
−160
0.0
−160
0.5
1.0
1.5
2.0
2.5
3.0
3.5
f/FData
Figure 38. Magnitude Spectrum for
8× Interpolation (dB)
30
−60
4.0
0
1
2
3
4
5
6
f/FData
Figure 39. Magnitude Spectrum for
16× Interpolation (dB)
7
8
DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
MAGNITUDE
vs
FREQUENCY
5
4
3
FIR
Magnitude – dB
2
Corrected
1
0
−1
−2
Rolloff
−3
−4
−5
0.0
0.1
0.2
0.3
0.4
0.5
f/FDAC
Figure 40. Magnitude Spectrum for Inverse Sinc Filtering
The filter taps for interpolation filters FIR1 - FIR4 and inverse sinc filter FIR5 are listed in Table 4.
Table 4. Filter Taps for FIR1–FIR5
FIR1
FIR2
FIR3
FIR4
FIR5 (INVSINC)
8
9
31
-33
1
0
0
0
0
–3
–24
–58
–219
289
9
0
0
0
512
–34
58
214
1212
289
400
0
0
2048
0
–34
–120
–638
1212
–33
9
0
0
0
–3
221
2521
–219
1
0
4096
0
–380
2521
31
0
0
619
–638
0
0
-971
214
0
0
1490
–58
0
0
–2288
9
0
3649
0
–6628
0
31
DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
Table 4. Filter Taps for FIR1–FIR5 (continued)
FIR1
FIR2
FIR3
FIR4
FIR5 (INVSINC)
20750
32768
20750
0
–6628
0
3649
0
–2288
0
1490
0
–971
0
619
0
–380
0
221
0
–120
0
58
0
–24
0
8
NCO
The DAC5686 uses a numerically controlled oscillator (NCO) with a 32-bit frequency register and a 16-bit phase
register. The NCO is used in quadrature-modulation and single-sideband modes to provide sin and cos for
mixing. The NCO tuning frequency is programmed in registers 0x1 through 0x4. Phase offset is programmed is
registers 0x5 and 0x6. A block diagram of the NCO is shown in Figure 41.
32
16
32
Frequency
Register
Σ
32
Accumulator
32
16
16
Σ
16
FDAC
Phase
Register
Figure 41. Block Diagram of the NCO
32
16
cos
CLK RESET
PHSTR
sin
Look-Up
Table
DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
The NCO accumulator is reset to zero when the PHSTR pin is high and remains at zero until PHSTR is set low.
Frequency word freq in the frequency register is added to the accumulator every clock cycle. The output
frequency of the NCO is:
freq F DAC
f NCO 2 32
While the maximum clock frequency of the DACs is 500 MSPS, the maximum clock frequency the NCO can
operate at is 320 MHz; mixing at DAC rates higher than 320 MSPS requires using the fs/4 mixing option.
Register Bit Allocation Map
NAME
R/W
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
chip_ver
R/W
0x00
freq_lsb
R/W
0x01
freq_int[7:0]
freq_lmidsb
R/W
0x02
freq_int[15:8]
freq_umidsb
R/W
0x03
freq_int[23:16]
freq_msb
R/W
0x04
freq_int[31:24]
phase_lsb
R/W
0x05
phase_int[7:0]
phase_msb
R/W
0x06
config_lsb
R/W
0x07
config_msb
R/W
0x08
ssb
config_usb
R/W
0x09
dual clk
daca_offset_lsb
R/W
0x0A
daca_gain_lsb
R/W
0x0B
daca_offset_gain_
msb
R/W
0x0C
dacb_offset_lsb
R/W
0x0D
dacb_offset[7:0]
dacb_gain_lsb
R/W
0x0E
dacb_gain[7:0]
dacb_offset_gain_
msb
R/W
0x0F
BIT 2
atest[4:0]
BIT 1
BIT 0
version[2:0] read only
phase_int[15:8]
mode[1:0]
div[1:0]
interl
sinc
dds_gain[1:0]
sel[1:0]
dith
sync_phstr
rspect
qflag
nco
counter
fbypass
sif4
twos
pll_rng[1:0]
rev_bbus
daca_offset[7:0]
daca_gain[7:0]
daca_offset[10:8]
sleepA
dacb_offset[10:8]
daca_gain[11:8]
sleepB
dacb_gain[11:8]
REGISTER DESCRIPTIONS
Register Name: chip_ver
MSB
LSB
atest[4:0]
0
0
0
chip_ver[2:0] read only
0
0
1
0
1
chip_ver[3:0]: chip_ver [3:0] stores the device version, initially 0x5. The user can find out which version of the
DAC5686 is in the system by reading this byte.
a_test[4:0]: must be 0 for proper operation.
Register Name: freq_lsb
MSB
LSB
freq_int[7:0]
0
0
0
0
0
0
0
0
33
DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
freq_int[7:0]: The lower 8 bits of the frequency register in the DDS block
Register Name: freq_lmidsb
MSB
LSB
freq_int[15:8]
0
0
0
0
0
0
0
0
freq_int[15:8]: The lower mid 8 bits of the frequency register in the DDS block
Register Name: freq_umidsb
MSB
LSB
freq_int[23:16]
0
0
0
0
0
0
0
0
freq_int[23:16]: The upper mid 8 bits of the frequency register in the DDS block
Register Name: freq_msb
MSB
LSB
freq_int[31:24]
0
0
1
0
0
0
0
0
freq_int[31:24]: The most significant 8 bits of the frequency register in the DDS block
Register Name: phase_lsb
MSB
LSB
phase_int[7:0]
0
0
0
0
0
0
0
0
phase_int[7:0]: The lower 8 bits of the phase register in the DDS block
Register Name: phase_msb
MSB
LSB
phase_int[15:8]
0
0
0
0
0
0
0
0
counter
Full_bypass
0
1
phase_int[15:8]: The most significant 8 bits of the phase register in the DDS block
Register Name: config_lsb
MSB
LSB
mode[1:0]
0
div[1:0]
0
0
sel[1:0]
0
0
mode[1:0]: Controls the mode of the DAC5686; summarized in Table 5.
Table 5. DAC5686 Modes
34
mode[1:0]
DAC5686 MODE
00
Dual-DAC
01
Single-sideband
10
Quadrature
11
Dual-DAC
0
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
div[1:0]: Controls the PLL divider value; summarized in Table 6.
Table 6. PLL Divide Ratios
div[1:0]
PLL DIVIDE RATIO
00
1× divider
01
2× divider
10
4× divider
11
8× divider
sel[1:0]: Controls the selection of interpolating filters used; summarized in Table 7.
Table 7. DAC5686 Filter Configuration
sel[1:0]
INTERP. FIR SETTING
00
×2
01
×4
10
×8
11
× 16
counter: When asserted, the DAC5686 goes into counter mode and uses an internal counter as a ramp input to
the DAC. The count range is determined by the A-side input data DA[2:0], as summarized in Table 8.
Table 8. DAC5686 Counter Mode Count Range
DA[2:0]
COUNT RANGE
000
All bits D[15:0]
001
Lower 7 bits D[6:0]
010
Mid 4 bits D[10:7]
100
Upper 5 bits D[15:11]
Full_bypass: When asserted, the interpolation filters and mixer logic are bypassed and the data inputs DA[15:0]
and DB[15:0] go straight to the DAC inputs.
Register Name: config_msb
MSB
LSB
ssb
interl
sinc
dith
sync_phstr
nco
sif4
twos
0
0
0
0
0
0
0
0
ssb: In single-sideband mode, assertion inverts the B data; in quadrature modulation mode, assertion routes the
A data path to DACB instead of the B data path.
interl: When asserted, data input to the DAC5686 on channel DA[15:0] is interpreted as a single interleaved
stream (I/Q); channel DB[15:0] is unused.
sinc: Assertion enables the INVSINC filter.
dith: Assertion enables dithering in the PLL.
sync_phstr: Assertion enables the PHSTR input as a sync input to the clock dividers in external single-clock
mode.
nco: Assertion enables the NCO.
sif4: When asserted, the sif interface becomes a 4-pin interface instead of a 3-pin interface. The SDIO pin
becomes an input only and the SDO is the output.
twos: When asserted, the chip interprets the input data as 2s complement form instead of binary offset.
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Register Name: config_usb
MSB
LSB
dualclk
0
DDS_gain[1:0]
0
rspect
qflag
0
0
0
pll_rng[1:0]
0
rev_bbus
0
0
dualclk: When asserted, the DAC5686 uses both clock inputs; CLK1/CLK1C is the input data clock and
CLK2/CLK2C is the DAC output clock. These two clocks must be phase-aligned within ±500 ps to function
properly. When deasserted, CLK2/CLK2C is the DAC output clock and is divided down to generate the input data
clock, which is output on PLLLOCK. Dual clock mode is only available when PLLVDD = 0.
DDS_gain[1:0]: Controls the gain of the DDS so that the overall gain of the DDS is unity. It is important to
ensure that max(abs(cos(ωt) + sin(ωt))) < 1. At different frequencies, the summation produces different maximum
outputs and must be reduced. The simplest is fs/4 mode where the maximum is 1 and the gain multiply should
be 1 to maintain unity. However, due to the fact that the digital logic does a divide-by-two in this summation, the
gain necessary to achieve unity must be double (DDS_gain[1:0] = 01). Table 9 shows the digital gain necessary
and the actual signal gain needed to make the above equation have a maximum value of 1.
Table 9. Digital Gain for DDS
DDS_gain [1:0]
DIGITAL GAIN
SIGNAL GAIN FOR UNITY
00
1.40625
0.703125
01
2
1
10
1.59375
0.7936
11
1.40625
0.703125
rspect: When asserted, the sin term is negated before being used in mixing. This gives the reverse spectrum in
single-sideband mode.
qflag: When asserted, the QFLAG pin is used during interleaved data input mode to identify the Q sample. When
deasserted, the TXENABLE pin transition is used to start an internal toggling signal, which is used to interpret
the interleaved data sequence; the first sample clocked into the DAC5686 after TXENABLE goes high is routed
through the A data path.
PLL_rng[1:0]: Increases the PLL VCO VtoI current, summarized in Table 10. See Figure 17 for the effect on
VCO gain and range.
Table 10. PLL VCO Vtol Current Increase
PLL_rng[1:0]
VtoI CURRENT INCREASE
00
nominal
01
15%
10
30%
11
45%
rev_bbus[1:0]: When asserted, pin 92 changes from DB15 to DB0, pin 91 changes from DB14 to DB1, etc.,
reversing the order of the DB[15:0] pins.
Register Name: daca_offset_lsb (2s complement)
MSB
LSB
daca_offset[7:0]
0
36
0
0
0
0
0
0
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DAC5686
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SLWS147B – APRIL 2003 – REVISED AUGUST 2004
daca_offset[7:0]: The lower 8 bits of the DACA offset
Register Name: daca_gain_lsb (2s complement)
MSB
LSB
daca_gain[7:0]
0
0
0
0
0
0
0
0
daca_gain[7:0]: The lower 8 bits of the DACA gain control register. These lower 8 bits are for fine gain control.
This word is a 2s complement value that adjusts the full-scale output current over an approximate 4% to –4%
range.
Register Name: daca_offset_gain_msb (2s complement)
MSB
LSB
daca_offset[10:8]
0
0
sleepa
0
0
daca_gain[11:8]
0
0
0
0
daca_offset[10:8]: The upper 3 bits of the DACA _offset
sleepa: When asserted, DACA is put into the sleep mode.
daca_gain[11:8]: Coarse gain control for DACA; the full-scale output current is:
I fullscale 16Vextio (GAINCODE 1)
1 FINEGAIN
16
3072
R biasj
where GAINCODE is the decimal equivalent of daca_gain [11:8] {0…15} and the FINEGAIN is daca_gain [1:0] as
2s complement [–127…128].
Register Name: dacb_offset_lsb (2s complement)
MSB
LSB
dacb_offset[7:0]
0
0
0
0
0
0
0
0
dacb_offset[7:0]: The lower 8 bits of the DACB offset
Register Name: dacb_gain_lsb (2s complement)
MSB
LSB
dacb_gain[7:0]
0
0
0
0
0
0
0
0
dacb_gain[7:0]: The lower 8 bits of the DACB gain control register. These lower 8 bits are for fine gain control.
This word is a 2s complement value that adjusts the full-scale output current over an approximate 4% to –4%
range.
Register Name: dacb_offset_gain_msb (2s complement)
MSB
LSB
dacb_offset[10:8]
0
0
sleepb
0
0
dacb_gain[11:8]
0
0
0
0
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dacb_offset[10:8]: The upper 3 bits of the DACA _offset
sleepb: When asserted, DACB is put into the sleep mode.
dacb_gain[11:8]: Coarse gain control for DACB; the full-scale output current is:
I fullscale 16Vextio (GAINCODE 1)
1 FINEGAIN
16
3072
R biasj
where GAINCODE is the decimal equivalent of dacb_gain [11:8] {0…15} and the FINEGAIN is dacb_gain [1:0] as
2s complement [–127…128].
DIGITAL INPUTS
Figure 42 shows a schematic of the equivalent CMOS digital inputs of the DAC5686. DA[0:15], DB[0:15], SLEEP,
PHSTR, TxENABLE, QFLAG, SDIO, SCLK, and SDENB have pulldown resistors and RESETB has a pullup
resistor internal to the DAC5686. See the specification table for logic thresholds.
IOVDD
IOVDD
DA[15:0]
DB[15:0]
SLEEP
PHSTR
TxENABLE
QFLAG
SDIO
SCLK
SDENB
Internal
Digital In
Internal
Digital In
RESETB
IOGND
IOGND
Figure 42. CMOS/TTL Digital Equivalent Input
CLOCK INPUT AND TIMING
Figure 43 shows an equivalent circuit for the clock input.
CLKVDD
CLKVDD
R1
10 kΩ
Internal
Digital In
CLKVDD
R1
10 kΩ
CLK
CLKC
R2
10 kΩ
R2
10 kΩ
CLKGND
Figure 43. Clock Input Equivalent Circuit
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CLOCK INPUT AND TIMING (continued)
Figure 44, Figure 45, and Figure 46 show various input configurations for driving the differential clock input
(CLK/CLKC).
Optional, May Be Bypassed
for Sine Wave Input
Swing Limitation
CAC
0.1 µF
1:4
CLK
RT
200 Ω
CLKC
Termination Resistor
Figure 44. Preferred Clock Input Configuration
Ropt
22 Ω
CAC
0.01 µF
Ropt
22 Ω
1:1
TTL/CMOS
Source
TTL/CMOS
Source
CLK
Optional, Reduces
Clock Feed-Through
CLKC
CLK
CLKC
0.01 µF
Node CLKC Internally Biased
to CLKVDD2
Figure 45. Driving the DAC5686 With a Single-Ended TTL/CMOS Clock Source
CAC
0.1 µF
Differential
ECL
or
(LV)PECL
Source
+
CLK
CAC
0.1 µF
–
100 Ω
CLKC
RT
130 Ω
RT
130 Ω
RT
82.5 Ω
RT
82.5 Ω
VTT
Figure 46. Driving the DAC5686 With a Differential ECL/PECL Clock Source
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www.ti.com
CLOCK INPUT AND TIMING (continued)
DAC Transfer Function
The CMOS DACs consist of a segmented array of NMOS current sources, capable of delivering a full-scale
output current up to 20 mA. Differential current switches direct the current of each current source to either one of
the complementary output nodes IOUT1 or IOUT2. Complementary output currents enable differential operation,
thus canceling out common-mode noise sources (digital feed-through, on-chip, and PCB noise), dc offsets,
even-order distortion components, and increasing signal output power by a factor of two.
The full-scale output current is set using external resistor RBIAS in combination with an on-chip band-gap voltage
reference source (1.2 V) and control amplifier. Current IBIAS through resistor RBIAS is mirrored internally to provide
a full-scale output current equal to 16 times IBIAS. The full-scale current can be adjusted from 20 mA down to 2
mA.
The DAC5686 delivers complementary output currents IOUT1 and IOUT2. Output current IOUT1 equals the
approximate full-scale output current when all bits (after the digital processing) are high. Full-scale output current
flows through terminal IOUT2 when all input bits are low. The relation between IOUT1 and IOUT2 can thus be
expressed as:
IOUT1 = IOUTFS – IOUT2
where IOUTFS is the full-scale output current. The output currents can be expressed as:
IOUT1 IOUT FS CODE
65536
(65536 CODE)
IOUT2 IOUT FS 65536
where CODE is the decimal representation of the DAC data input word. Output currents IOUT1 and IOUT2 drive
resistor loads RL or a transformer with equivalent input load resistance (RL). This translates into single-ended
voltages VOUT1 and VOUT2 at terminals IOUT1 and IOUT2, respectively, of:
CODE
VOUT1 IOUT1 RL 65536 IOUTFS RL
VOUT2 IOUT2 RL (65536 CODE)
65536 IOUTFS RL
The differential output voltage VOUTDIFF can thus be expressed as:
(2CODE 65536)
VOUT DIFF IOUT1 VOUT2 65536 IOUTFS RL
The latter equation shows that applying the differential output results in doubling of the signal power delivered to
the load. Because the output currents IOUT1 and IOUT2 are complementary, they become additive when
processed differentially. Note that care should be taken not to exceed the compliance voltages at nodes IOUT1
and IOUT2, which would lead to increased signal distortion.
Reference Operation
The DAC5686 comprises a band-gap reference and control amplifier for biasing the full-scale output current. The
full-scale output current is set by applying an external resistor RBIAS. The bias current IBIAS through resistor RBIAS
is defined by the on-chip band-gap reference voltage and control amplifier. The full-scale output current equals
16 times this bias current. The full-scale output current IOUTFS can thus be expressed as (coarse gain = 15, fine
gain = 0):
16 V EXTIO
IOUT FS R BIAS
,
where VEXTIO is the voltage at terminal EXTIO. The band-gap reference voltage delivers an accurate voltage of
1.2 V. This reference is active when terminal EXTLO is connected to AGND. An external decoupling capacitor
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CLOCK INPUT AND TIMING (continued)
CEXT of 0.1 µF should be connected externally to terminal EXTIO for compensation. The band-gap reference
additionally can be used for external reference operation. In that case, an external buffer with a high-impedance
input should be used in order to limit the band-gap load current to a maximum of 100 nA. The internal reference
can be disabled and overridden by an external reference by connecting EXTLO to AVDD. Capacitor CEXT may
hence be omitted. Terminal EXTIO serves as either input or output node.
The full-scale output current can be adjusted from 20 mA down to 2 mA by varying resistor RBIAS or changing the
externally applied reference voltage. The internal control amplifier has a wide input range supporting the
full-scale output current range of 20 dB.
Analog Current Outputs
Figure 47 shows a simplified schematic of the current source array with corresponding switches. Differential
switches direct the current of each individual NMOS current source to either the positive output node IOUT1 or
its complementary negative output node IOUT2. The output impedance is determined by the stack of the current
sources and differential switches, and is typically >300 kΩ in parallel with an output capacitance of 5 pF.
The external output resistors are terminated to AVDD. The maximum output compliance at nodes IOUT1 and
IOUT2 is limited to AVDD + 0.5 V, determined by the CMOS process. Beyond this value, transistor breakdown
can occur, resulting in reduced reliability of the DAC5686 device. The minimum output compliance voltage at
nodes IOUT1 and IOUT2 equals AVDD – 0.5 V. Exceeding the minimum output compliance voltage adversely
affects distortion performance and integral nonlinearity. The optimum distortion performance for a single-ended
or differential output is achieved when the maximum full-scale signal at IOUT1 and IOUT2 does not exceed
0.5 V.
AVDD
RLOAD
IOUT1
S(1)
RLOAD
IOUT2
S(1)C
S(2)
S(2)C
S(N)
S(N)C
Figure 47. Equivalent Analog Current Output
The DAC5686 can be easily configured to drive a doubly terminated 50-Ω cable using a properly selected RF
transformer. Figure 48 and Figure 49 show the 50-Ω doubly terminated transformer configuration with 1:1 and
4:1 impedance ratios, respectively. Note that the center tap of the primary input of the transformer must be
connected to AVDD to enable a dc current flow. Applying a 20-mA full-scale output current would lead to a
0.5-Vpp output for a 1:1 transformer and a 1-Vpp output for a 4:1 transformer.
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CLOCK INPUT AND TIMING (continued)
AVDD (3.3 V)
50 Ω
1:1
IOUT1
RLOAD
50 Ω
100 Ω
IOUT2
50 Ω
AVDD (3.3 V)
Figure 48. Driving a Doubly Terminated 50-Ω Cable Using a 1:1 Impedance-Ratio Transformer
AVDD (3.3 V)
100 Ω
4:1
IOUT1
RLOAD
50 Ω
IOUT2
100 Ω
AVDD (3.3 V)
Figure 49. Driving a Doubly Terminated 50-Ω Cable Using a 4:1 Impedance-Ratio Transformer
SLEEP MODE
The DAC5686 features a power-down mode that turns off the output current and reduces the supply current to
less than 5 mA over the supply range of 3 V to 3.6 V and temperature range of –40°C to 85°C. The power-down
mode is activated by applying a logic level 1 to the SLEEP pin (e.g., by connecting pin SLEEP to IOVDD). An
internal pulldown circuit at node SLEEP ensures that the DAC5686 is enabled if the input is left disconnected.
Power-up and power-down activation times depend on the value of the external capacitor at node SLEEP. For a
nominal capacitor value of 0.1 mF, it takes less than 5 ms to power down and approximately 3 ms to power up.
POWER-UP SEQUENCE
In all conditions, bring up DVDD first. If PLLVDD is powered (PLL on), CLKVDD should be powered before or
simultaneously with PLLVDD. AVDD, CLKVDD and IOVDD can be powered simultaneously or in any order.
Within AVDD, the multiple AVDD pins should be powered simultaneously.
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DAC5686 EVALUATION BOARD
There is a combination EVM board for the DAC5686 digital-to-analog converter for evaluation. This board allows
the user the flexibility to operate the DAC5686 in various configurations. Possible output configurations include
transformer-coupled, resistor-terminated, inverting/non-inverting and differential amplifier outputs. The digital
inputs are designed to be driven directly from various pattern generators with the onboard option to add a
resistor network for proper load termination.
Appendix A. PLL LOOP FILTER COMPONENTS
For the external second-order filter shown in Figure 50, the components R, C1, and C2 are calculated for a
desired phase margin and loop bandwidth. Resistor R3 = 200 Ω and capacitor C3 = 8 pF are internal to the
DAC5686.
External
Internal
R3
C1
C2
C3
R1
S0006-01
Figure 50. DAC5686 Loop Filter
The VCO gain (Gvco) as a function of VCO frequency for the DAC5686 is shown in Figure 17. For a desired
VCO frequency, the loop filter values can be calculated using the following equations.
Nominal PLL design parameters include:
Charge pump current:
iqp = 1 mA
VCO gain:
KVCO = 2π × GVCO rad/A
PLL divide ratio × interpolation:
N = {2, 4, 8, 16, 32}
Phase detector gain:
Kd = iqp × (2πN)–1 A/rad
Let
Desired loop bandwidth = ωd
Desired phase margin = φd
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DAC5686 EVALUATION BOARD (continued)
Then
C1 1 1 2
3
C2 1 2
3
3 2
R
1(3 2)
where
1 K dKVCO
(tan d sec d)
2d
2 1
d(tan d sec d)
3 tan d sec d
d
Example: φd = 70°, ωd = 1 MHz, GVCO = 300e6 MHz/A
N
R (Ω)
C1 (µF)
C2 (pF)
2
43
0.02
670
4
86
0.01
335
8
173
0.005
167
16
346
0.002
84
32
692
0.001
42
The calculated phase margin and loop bandwidth can be verified by plotting the gain and phase of the open-loop
transfer function given by
K K (1 sRC1)
H(s) 3 VCO d
s RC1C2 s 2(C1 C2)
Figure 51 shows the open-loop gain and phase for the DAC5686 evaluation-board loop filter.
−100
60
N = 2, 4, 8, 16, 32
40
−120
Phase − °
Gain − dB
20
0
−140
−20
−160
−40
−60
0.01
0.1
1
f − Frequency − MHz
10
100
−180
0.01
0.1
1
10
100
f − Frequency − MHz
G005
Figure 51. Open-Loop Phase and Gain Plots for DAC5686 Evaluation Board
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The phase error (φerr) phase and frequency step responses are given by the following equations and are plotted
in Figure 52 for the DAC5686 evaluation-board loop filter.
err [1 nt ( nt) 2] e nt
phase step response
2
nt
err [ nt ( nt) ] e
frequency step response
n
1.0
1.0
Response to a Phase Step at Time 0
Response to a Frequency Step at Time 0
N = 2, 4, 8, 16, 32
0.8
Normalized Phase Error
Normalized Phase Error
N = 2, 4, 8, 16, 32
Increasing N
0.5
0.0
Increasing N
0.6
0.4
0.2
−0.5
0.0
0.5
1.0
1.5
2.0
2.5
t − Time − µs
3.0
3.5
4.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
t − Time − µs
3.5
4.0
G006
Figure 52. Phase and Frequency Step Responses for DAC5686 Evaluation Board
45
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