FAIRCHILD TMC2246AKEC2

www.fairchildsemi.com
TMC2246A
Image Filter
11 x 10 bit, 60 MHz
Features
Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
60 MHz computation rate
60 MHz data and coefficient input
Four 11 x 10-bit multipliers
Individual data and coefficient inputs
25-Bit accumulator
Fractional and integer two’s complement data formats
Input and output data latches with user-configurable
enables
• Selectable 16-bit rounded output
• Internal 1/2 LSB rounding
• Available in 120-pin CPGA, PPGA, MPGA, or MQFP
Fast pixel interpolation
Fast image manipulation
Image mixing and keying
High-performance FIR filters
Adaptive digital filters
One- and two-dimensional image processing
Description
The TMC2246A is a video-speed convolutional array composed of four 11 x 10 bit registered multipliers followed by a
summer and an accumulator. All eight multiplier inputs are
accessible to the user and may be updated every clock cycle
with integer or fractional two’s complement data. A pipelined architecture, fully registered input and output ports,
and asynchronous three-state output enable control simplify
the design of complex systems.
Logic Symbol
TMC2246A
Image Filter
D19-0
C110-0
D29-0
C210-0
D39-0
C310-0
D49-0
C410-0
ENB1-4
ENSEL
ACC
FSEL
S15-0
OCEN
OEN
The data or coefficient inputs to the multipliers may be held
over multiple clock cycles, providing storage for mixing and
filtering coefficients. The 25-bit internal accumulator path
allows two bits of cumulative word growth and may be internally rounded to 16 bits. Output data are updated every clock
cycle, or may be held under user control. All data inputs, outputs, and controls are TTL compatible and (except for the
three-state output enable) are registered on the rising edge of
CLK.
The TMC2246A is uniquely suited to performing pixel interpolation in image manipulation and filtering applications. As
a companion to the Fairchild Semiconductor TMC2301 and
TMC2302 Image Manipulation Sequencers, the TMC2246A
can execute a bilinear interpolation of an image (4-pixel kernels) at real-time video rates. Larger kernels or other, more
complex, functions can be realized with no loss in performance
by utilizing multiple devices.
With unrestricted access to all data and coefficient input
ports, the TMC2246A offers considerable flexibility in applications performing digital filtering, adaptive FIR filters, mixers, and other similar systems requiring high-speed
processing.
CLK
Fabricated in a submicron CMOS process, the TMC2246A
operates at a guaranteed clock rate of 60 MHz over the full
temperature and supply voltage ranges. It is pin- and function-compatible with Fairchild’s TMC2246, while providing
higher speed operation and lower power dissipation. It is
available in a 120 pin Plastic Pin Grid Array (PPGA), 120
pin Ceramic Pin Grid Array (CPGA), 120 lead MQFP to
PPGA (MPGA), and a 120 lead Metric Quad FlatPack
(MQFP).
REV. 1.0.3 9/11/00
PRODUCT SPECIFICATION
TMC2246A
Block Diagram
D19-0 C110-0 ENB1 D29-0 C210-0 ENB2 D39-0 C310-0 ENB3 D4 9-0 C410-0 ENB4
ENSEL
ACC
FSEL
*
2 -10
25
OCEN
LSB
MSB
CLK
OEN
*Automatic rounding function
S15-0
Functional Description
The TMC2246A Image Filter is a flexible multiplier-summer
array which computes the accumulated sum of four 11x10
bit products, allowing word growth up to 25 bits.
The inputs are user-configurable, allowing latching of either
the 10- or 11-bit input data. The data format is user-selectable
between integer or fractional two’s complement arithmetic.
Total latency from input registers to output data port is 5
clocks.
2
The output data path is 16 bits wide, providing the lower 16
bits of the accumulator when in integer format or the upper
16 bits of the 25-bit accumulator path when fractional two’s
complement notation is selected. One-time rounding to 16
bits is performed automatically when accumulating fractional data, but is disabled when operating in integer format
to maintain the integrity of the least-significant bits.
REV. 1.0.3 9/11/00
TMC2246A
PRODUCT SPECIFICATION
Pin Assignments
120 Pin Plastic Pin Grid Array, H5 Package, 120 Pin Ceramic Pin Grid Array, G1 Package, and
120 Pin Metric Quad FlatPack to 120 Pin Plastic Pin Array, H6 Package
1
2
3
4
5
6
7
8
A
B
C
D
E
KEY
F
G
H
J
K
L
M
N
REV. 1.0.3 9/11/00
Top View
Cavity Up
9
10 11 12 13
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
C1
C2
C3
C4
Name
ENSEL
ENB2
ENB3
D47
D45
D42
D41
C410
C48
C46
C43
C40
C32
ACC
FSEL
ENB4
D49
D46
D43
D40
C49
C47
C44
C42
C30
C35
S15
OEN
CLK
ENB1
Pin
C5
C6
C7
C8
C9
C10
C11
C12
C13
D1
D2
D3
D11
D12
D13
E1
E2
E3
E11
E12
E13
F1
F2
F3
F11
F12
F13
G1
G2
G3
Name
D48
D44
GND
VDD
C45
C41
C31
C33
C36
S13
S14
OCEN
C34
C37
C39
S11
S12
GND
C38
C310
D30
S9
S10
VDD
D31
D32
D33
S7
S8
GND
Pin
G11
G12
G13
H1
H2
H3
H11
H12
H13
J1
J2
J3
J11
J12
J13
K1
K2
K3
K11
K12
K13
L1
L2
L3
L4
L5
L6
L7
L8
L9
Name
D35
D36
D34
S6
S5
VDD
GND
D38
D37
S4
S3
GND
D27
D29
D39
S2
S1
D18
D23
D26
D28
S0
D17
D15
D12
C19
GND
VDD
C20
C24
Pin
L10
L11
L12
L13
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
Name
C28
D20
D24
D25
D19
D14
D11
C110
C17
C15
C13
C10
C22
C25
C29
D21
D22
D16
D13
D10
C18
C16
C14
C12
C11
C21
C23
C26
C27
C210
3
PRODUCT SPECIFICATION
TMC2246A
Pin Assignments
120 Lead Metric Quad Flat Pack (KE) Package
120
1
4
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
CLK
FSEL
ACC
OCEN
OEN
S15
S14
GND
S13
S12
S11
VDD
S10
S9
S8
GND
S7
S6
S5
VDD
S4
S3
S2
GND
Pin
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Name
S1
S0
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
C110
C19
C18
C17
C16
GND
C15
C14
C13
VDD
C12
C11
Pin
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Name
C10
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C210
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D39
GND
Pin
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Name
D38
D37
D36
D35
D34
D33
D32
D31
D30
C310
C39
C38
C37
C36
C35
C34
C33
C32
C31
C30
C40
C41
C42
C43
Pin
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Name
C44
C45
C46
C47
C48
VDD
C49
C410
D40
GND
D41
D42
D43
D44
D45
D46
D47
D48
D49
ENB3
ENB2
ENB1
ENB4
ENSEL
REV. 1.0.3 9/11/00
TMC2246A
PRODUCT SPECIFICATION
Pin Descriptions
Pin Number
Pin Name
CPGA/PPGA/
MPGA
MQFP
Pin Function Description
Power
VDD
F3, H3, L7, C8
12, 20, 46, 102 Supply Voltage. The TMC2246A operates from a single +5V
supply. All power and ground pins must be connected.
GND
E3, G3, J3, L6,
H11, C7
8, 16, 24, 42,
72, 106
Ground. The TMC2246A operates from a single +5V supply. All
power and ground pins must be connected.
C3
1
System Clock. The TMC2246A operates from a single master
clock input. The rising edge of clock strobes all enabled registers.
All timing specifications are referenced to the rising edge of CLK.
Clock
CLK
Inputs
D19-0
M1, K3, L2, N1, 27, 28, 29, 30,
L3, M2, N2, L4, 31, 32, 33, 34,
M3, N3
35, 36
D29-0
J12, K13, J11, 70, 69, 68, 67,
K12, L13, L12, 66, 65, 64, 63,
K11, M13, M12,
62, 61
L11
D39-0
J13, H12, H13, 71, 73, 74, 75,
G12, G11, G13, 76, 77, 78, 79,
F13, F12, F11,
80, 81
E13
D49-0
B4, C5, A4, B5, 115, 114, 113,
A5, C6, B6, A6, 112, 111, 110,
A7, B7
109, 108, 107,
105
C110-0
M4, L5, N4, M5, 37, 38, 39, 40,
N5, M6, N6, M7, 41, 43, 44, 45,
N7, N8, M8
47, 48, 49
C210-0
N13, M11, L10, 60, 59, 58, 57,
N12, N11, M10, 56, 55, 54, 53,
L9, N10, M9,
52, 51, 50
N9, L8
C310-0
E12, D13, E11,
D12, C13, B13,
D11, C12, A13,
C11, B12
C410-0
A8, B8, A9, B9, 104, 103, 101,
A10, C9, B10, 100, 99, 98, 97,
A11, B11, C10, 96, 95, 94, 93
A12
Data Input Ports. D1 through D4 are the 10-bit data input ports.
The LSB is Dx0.
Coefficient Input Ports. C1 through C4 are the 11-bit coefficient
input ports. The LSB is Cx0.
82, 83, 84, 85,
86, 87, 88, 89,
90, 91, 92
Outputs
S15-0
C1, D2, D1, E2, 6, 7, 9, 10, 11,
E1, F2, F1, G2, 13, 14, 15, 17,
G1, H1, H2, J1, 18, 19, 21, 22,
J2, K1, K2, L1
23, 25, 26
REV. 1.0.3 9/11/00
Sum Output. The current 16-bit result is available at the Sum
output. The LSB is S0. See the Functional Block Diagram.
5
PRODUCT SPECIFICATION
TMC2246A
Pin Descriptions (continued)
Pin Number
Pin Name
Pin Function Description
CPGA/PPGA/
MPGA
MQFP
FSEL
B2
2
Format Select. Coefficients input during the current clock are
assumed to be in fractional two's complement format. Rounding to
16 bits is performed as determined by the accumulator control,
ACC, and the upper 16 bits of the accumulator are output when
the registered Format Select input (FSEL) is LOW. When FSEL is
HIGH, two's complement integer format is assumed, and the
lower 16 bits of the accumulator are presented at the output. No
rounding is performed when operating in integer mode. See the
Functional Block Diagram and the Applications Discussion.
ENSEL
A1
120
Enable Select. The registered Enable Select determines whether
the data or the coefficient input registers may be held on the next
rising edge of clock, in conjunction with the individual input
enables ENB1–ENB4. See Table 1.
ENB1–
ENB4
C4, A2, A3, B3
118, 117, 116,
119
Input Enables. When ENBi (i=1, 2, 3, or 4) is LOW, registers Ci
and Di are both strobed by the next rising edge of CLK. When
ENBi is HIGH and ENSEL is LOW, Di is strobed, but Ci is held.
When ENBi and ENSEL are both HIGH, Di is held and Ci is
strobed. See Table 1. Thus, either or both input registers to each
multiplier are updated on each clock cycle.
B1
3
Accumulate. When the registered ACCumulator control is LOW,
no internal accumulation will be performed on the data input
during the current clock, effectively clearing the prior accumulated
sum. If operating in fractional two's complement format (FSEL =
LOW), one-half LSB rounding to 16 bits is performed on the result.
This allows the user to perform summations without propagating
roundoff errors.
Controls
ACC
When ACC is HIGH, the internal accumulator adds the emerging
products to the sum of previous products, without performing
additional rounding.
OCEN
D3
4
Output Register Enable. The output of the accumulator is
latched into the output register on the next clock when the Output
Register Clock Enable is LOW. When OCEN is HIGH the contents
of the output register remain unchanged; however, accumulation
will continue internally if ACC remains HIGH.
OEN
C2
5
Output Enable. Data currently in the output registers is available
at the output bus S15-0 when the asynchronous Output Enable is
LOW. When OEN is HIGH, the outputs are in the high-impedance
state.
No Connect
NC
D4 (Index Pin)
Not Connected. (Optional)
Note:
1. X denotes a "Don't Care" condition.
2. Any register not explicitly held is updated on the next rising edge of CLK.
6
REV. 1.0.3 9/11/00
TMC2246A
PRODUCT SPECIFICATION
Table 1. Input Register Control
ENB1-4
ENSEL
Input Register Held
1
1
Data i
1
0
Coefficient i
0
X
None
Data Formats
Fractional Two’s Complement Format (FSEL = LOW)
15
14
13
12
11
10
9
8
0
-2 .
1
2.
1
0
-2
6
-2
5
2
4
2
3
2
2
2
2
0
2.
-1
2
-1
2
-1
2
7
-2
2
-2
2
-2
2
6
-3
2
-3
2
-3
2
5
-4
2
-4
2
-4
2
4
2
-5
2
-5
2
-5
3
-6
2
-6
2
-6
2
2
-7
2
-7
2
-7
2
1
-8
2
-8
2
-8
2
0
BIT
-9
DATA (D1-4)
-9
COEFFICIENT (C1-4)
-9
2
SUM
BIT
2
2
Integer Two’s Complement Format (FSEL = HIGH)
15
14
13
12
11
10
9
9
-2
10
-2
15
-2
14
2
13
2
12
2
11
2
10
2
9
2
9
2
8
7
6
5
4
3
2
1
0
8
2
7
2
6
2
5
2
4
23
22
21
20.
4
3
2
1
0
2.
COEFFICIENT (C1-4)
1
0
SUM
2
8
2
8
2
7
2
7
2
6
2
6
2
5
2
5
2
2
4
2
2
3
2
2
2
2
2
2
2.
DATA (D1-4)
Integer Two’s Complement Data / Fractional Two’s Complement Coefficient Format (FSEL = LOW)
15
14
13
12
11
10
9
9
-2
1
2.
10
9
-2
15
-2
14
2
13
2
12
2
11
2
2
0
2
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
2.
DATA (D1-4)
-8
-9
COEFFICIENT (C1-4)
0
SUM
2
-1
2
8
2
2
-2
2
7
2
2
-3
2
6
2
2
-4
2
5
2
2
2
-5
4
2
2
-6
2
3
2
2
-7
2
2
2
2
2
1
2
2
2.
BIT
Note: A minus sign indicates the sign bit.
Figure 1. Data Formats
Equivalent Circuits and Threshold
Levels
VDD
VDD
p
p
Output
Data or
Control
Input
n
n
GND
GND
Figure 2. Equivalent Digital Input Circuit
REV. 1.0.3 9/11/00
Figure 3. Equivalent Digital Output Circuit
7
PRODUCT SPECIFICATION
TMC2246A
tENA
OEN
tDIS
0.5V
2.0V
0.8V
Three-State
Outputs
0.5V
High Impedance
Figure 4. Threshold Levels for Three-State Measurement
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter
Min
Max
Unit
Supply Voltage
-0.5
7.0
V
-0.5
VDD + 0.5
V
-0.5
VDD + 0.5
V
-3.0
6.0
mA
1
sec
-20
110
°C
140
°C
150
°C
300
°C
Input Voltage
Output, Applied
Voltage2
Output, Externally Forced
Current3,4
Output, Short Circuit Duration (single output in HIGH state to ground)
Operating, Ambient Temperature
Junction Temperature
Storage Temperature
-65
Lead Soldering (10 seconds)
Notes:
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if
Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
Operating Conditions
Parameter
Min
Nom
Max
Units
VDD
Power Supply Voltage
4.75
5.0
5.25
V
fCLK
Clock frequency
TMC2246A
30
MHz
TMC2246A-1
40
MHz
60
MHz
TMC2246A-2
8
tPWH
CLK pulse width, HIGH
8
ns
tPWL
CLK pulse width, LOW
6
ns
tS
Input Data Set-up Time
6
ns
tH
Input Data Hold Time
1.5
ns
VIH
Input Voltage, Logic HIGH
2.0
VIL
Input Voltage, Logic LOW
0.8
V
IOH
Output Current, Logic HIGH
-2.0
mA
IOL
Output Current, Logic LOW
4.0
mA
TA
Ambient Temperature, Still Air
70
°C
0
V
REV. 1.0.3 9/11/00
TMC2246A
PRODUCT SPECIFICATION
Electrical Characteristics
Parameter
IDD
IDDU
Total Power Supply Current
Power Supply Current,
Unloaded
IDDQ
Power Supply Current,
Quiescent
Conditions
Min
Typ
Max
Units
TMC2246A
95
mA
TMC2246A-1
120
mA
TMC2246A-2
170
mA
TMC2246A
80
mA
TMC2246A-1
100
mA
TMC2246A-2
140
mA
5
mA
VDD = Max, CLOAD = 25pF, fCLK = Max
VDD = Max, OEN = HIGH, fCLK = Max
VDD = Max, CLK = LOW
CPIN
I/O Pin Capacitance
IIH
Input Current, HIGH
VDD = Max, VIN = VDD
5
±10
µA
IIL
Input Current, LOW
VDD = Max, VIN = 0 V
±10
µA
IOZH
Hi-Z Output Leakage Current, VDD = Max, VIN = VDD
Output HIGH
±10
µA
IOZL
Hi-Z Output Leakage Current, VDD = Max, VIN = 0 V
Output LOW
±10
µA
IOS
Short-Circuit Current
-80
mA
VOH
Output Voltage, HIGH
S15-0, IOH = Max
VOL
Output Voltage, LOW
S15-0, IOL = Max
-20
pF
2.4
V
0.4
V
Max
Units
Switching Characteristics
Parameter
Conditions1
Min
Typ
tDO
Output Delay Time
CLOAD = 25 pF
tHO
Output Hold Time
CLOAD = 25 pF
14
tENA
Three-State Output Enable Delay
CLOAD = 0 pF
10
ns
tDIS
Three-State Output Disable Delay
CLOAD = 0 pF
10
ns
4
ns
ns
Note:
1. All transitions are measured at a 1.5V level except for tENA and tDIS.
REV. 1.0.3 9/11/00
9
PRODUCT SPECIFICATION
TMC2246A
Timing Diagram
tPWH
1/fCLK
CLK
1
tS
2
tH
D1-49-0
DA
DB
C1-410-0
CA
CB
3
4
tPWKL
6
5
CONTROLS1
tDO
S15-0
2
tHO
SA
Notes:
1. Except OEN.
2. Assumes OEN = LOW.
Application Notes
Using the TMC2246A for Pixel Interpolation
Typical Operation
As a companion product to the TMC2301 Image Resampling
Sequencer, the TMC2246A offers an excellent tool for performing high-speed pixel interpolation and image filtering.
The versatile input clock enables and unrestricted data and
coefficient inputs provided on the TMC2246A allow considerable flexibility in numerous image and signal processing
architectures.
Table 2 shows a typical sequence of operations which clarifies the inherent latencies of the device and illustrates fixed
coefficient storage, product accumulation, and device reconfiguration prior to beginning a new accumulation. This
assumes that the device is set to fractional two’s complement
mode (FSEL = LOW) with OCEN = LOW, OEN = LOW,
and the input registers configured to hold coefficients only
(ENSEL = LOW). X= “don’t care.”
10
Any pixel resampling operation with multiple-pixel kernels
must utilize some parallel-processing technique, such as
memory banding, to maintain high-speed image throughput
rates. Memory banding utilizes adders to generate parallel
offset addresses, allowing the user to access multiple pixel
locations simultaneously. Using such techniques, one
TMC2246A can perform bilinear interpolation (four-pixel
kernel) with no loss in system performance.
Larger kernels can be realized in similar systems with additional TMC2246As. Figure 5 illustrates a basic pixel interpolation application.
REV. 1.0.3 9/11/00
TMC2246A
PRODUCT SPECIFICATION
Table 2. Typical TMC2246A Operation Sequence
CLK
D1
C1
ENB1
D2
C2
ENB2
D3
C3
ENB3
D4
C4
0
-
-
0
-
-
0
-
-
0
-
-
ENB4 ACC
0
-
Sum
-
1
D1(1) C1(1)
1
D2(1) C2(1)
1
D3(1) C3(1)
1
D4(1) C4(1)
1
0
-
2
D1(2)
0
D2(2) C2(2)
0
D3(2)
X
1
D4(2)
X
1
1
-
3
D1(3) C1(3)
0
D2(3) C2(3)
0
D3(3)
X
0
D4(3)
X
0
1
4
D1(4) C1(4)
-
D2(4) C2(4)
-
D3(4) C3(4)
-
D4(4) C4(4)
-
0
X
5
S(5)=D1(1)C1(1)+D2(1)C2(1)
+D3(1)C3(1)+D4(1)C4(1)+ 2-10
6
S(6)=S(5)+D1(2)C1(1)+D2(2)C2(1)
+D3(2)C3(1)+D4(2)C4(1)
7
S(7)=S(6)+D1(3)C1(3)+D2(3)C2(3)
+D3(3)C3(1)+D4(3)C4(1)
8
S(8)=D1(4)C1(4)+D2(4)C2(4)
+D3(4)C3(4)+D4(4)C4(4)+2-10
Notice in this example, operating in fractional two’s complement mode, that rounding is imposed on the first cycle only of an
accumulation. This avoids the propagation of accumulated roundoff errors.
REV. 1.0.3 9/11/00
11
PRODUCT SPECIFICATION
TMC2246A
“X”
“Y”
TMC2302A
SADR23-8
TMC2302A
SADR7-4
SADR7-4
TADR11-0
SADR23-8 TADR11-0
Address
Offset
Adders
+1
+1
Banded
Source
Image
RAM
ADDR
ADDR
X,Y
X+1,Y
DOUT
D1
ADDR
X,Y+1
DOUT
C1
D2
DOUT
C2
D3
ADDR
X+1,Y+1
Banded
Interpolation
Coefficient
ROM
DOUT
C3
D4
C4
TMC2011A
TMC2246A
Pipeline
Delay
Register
S15-0
Interpolated Pixel Data
D IN
Target
Image
RAM
U,VAddress
ADDR
D OUT
To Display
Figure 5. Bilinear Interpolation Using the TMC2246A
TMC2246A Applications in Digital
Filtering
Unrestricted access to all input ports of the TMC2246A
allows the user considerable flexibility in realizing numerous
digital filter architectures. Figure 6 illustrates how the device
may be utilized as a flexible high-speed FIR filter with the
ability to modify all of the filter coefficients dynamically or
to store a fixed set if desired.
12
Longer filters, with more taps, are realized by including an
external adder (such as the common 74381 type) to cascade
multiple TMC2246As. Alternatively, two additional taps and
a cascading adder are available in the Fairchild TMC2249A
Digital Mixer.
REV. 1.0.3 9/11/00
TMC2246A
PRODUCT SPECIFICATION
Data
Coefficients
Select
+
+
TMC2246A
TMC2246A
S15-0
S15-0
+
Filter Output
Figure 6. Using the TMC2246A For FIR Filtering
Related Products
•
•
•
•
TMC2301 Image Resampling Sequencer
TMC2302A Image Manipulation Sequencer
TMC2249A Video Mixer
TMC2242B Half-Band Filter
REV. 1.0.3 9/11/00
13
PRODUCT SPECIFICATION
TMC2246A
Mechanical Dimensions
120-Lead CPGA Package
Symbol
Inches
Min.
A
A1
A2
øB
øB2
D
D1
e
L
L1
M
N
P
Max.
Millimeters
Min.
Notes:
Notes
1. Pin #1 identifier shall be within shaded area shown.
Max.
.080
.160
.040
.060
.125
.215
.016
.020
.050 NOM.
1.340
1.380
2.03
4.06
1.01
1.53
3.17
5.46
0.40
0.51
1.27 NOM.
33.27
35.05
1.200 BSC
.100 BSC
.110
.145
.170
.190
13
120
.003
—
30.48 BSC
2.54 BSC
2.79
3.68
4.31
4.83
13
120
.076
—
2. Pin diameter excludes solder dip finish.
3. Dimension "M" defines matrix size.
4. Dimension "N" defines the maximum possible number of pins.
5. Orientation pin is at supplier's option.
2
2
SQ
6. Controlling dimension: inch.
3
4
A
A2
A1
øB
L
D
øB2
P
e
Top View
Cavity Up
D1
Pin 1 Identifier
14
REV. 1.0.3 9/11/00
TMC2246A
PRODUCT SPECIFICATION
Mechanical Dimensions
120-Lead PPGA Package
Symbol
Inches
Min.
A
A1
A2
øB
øB2
D
D1
e
L
L1
M
N
P
Max.
Millimeters
Min.
Notes:
Notes
1. Pin #1 identifier shall be within shaded area shown.
Max.
.080
.160
.040
.060
.125
.215
.016
.020
.050 NOM.
1.340
1.380
2.03
4.06
1.01
1.53
3.17
5.46
0.40
0.51
1.27 NOM.
33.27
35.05
1.200 BSC
.100 BSC
.110
.145
.170
.190
13
120
.003
—
30.48 BSC
2.54 BSC
2.79
3.68
4.31
4.83
13
120
.076
—
2. Pin diameter excludes solder dip finish.
3. Dimension "M" defines matrix size.
4. Dimension "N" defines the maximum possible number of pins.
5. Orientation pin is at supplier's option.
2
2
SQ
6. Controlling dimension: inch.
3
4
A
A2
A1
øB
L
D
øB2
P
e
Top View
Cavity Up
D1
Pin 1 Identifier
REV. 1.0.3 9/11/00
15
PRODUCT SPECIFICATION
TMC2246A
Mechanical Dimensions
120-Lead Metric Quad Flat Package to Pin Grid Array Package (MPGA)
Symbol
Inches
Min.
A
A1
A2
A3
øB
øB2
D
D1
e
L
M
N
Max.
Millimeters
Min.
Notes:
Notes
1. Pin #1 identifier shall be within shaded area shown.
Max.
2. Pin diameter excludes solder dip finish.
.309
.311
.145
.155
.080
.090
.050 TYP.
.016
.020
.050 NOM.
1.355
1.365
7.85
7.90
3.68
3.94
2.03
2.29
1.27 TYP.
0.40
0.51
1.27 NOM.
34.42
34.67
2
2
SQ
1.200 BSC
.100 BSC
.175
.185
13
120
30.48 BSC
2.54 BSC
4.45
4.70
13
120
3
4
3. Dimension "M" defines matrix size.
4. Dimension "N" defines the maximum possible number of pins.
5. Orientation pin is at supplier's option.
6. Controlling dimension: inch.
A
A1
A2
L
A3
øB2
øB
e
D
e
Fairchild
TMC2249A
D1
Pin 1 Identifier
16
REV. 1.0.3 9/11/00
TMC2246A
PRODUCT SPECIFICATION
Mechanical Dimensions
120-Lead MQFP Package
Inches
Symbol
Min.
A
A1
A2
B
C
D/E
D1/E1
e
L
N
ND
α
ccc
Max.
—
.154
.010
—
.125
.144
.018
.012
.009
.005
1.219
1.238
1.098
1.106
.0315 BSC
.026
.037
120
30
0°
—
7°
.004
Millimeters
Min.
1. All dimensions and tolerances conform to ANSI Y14.5M-1982.
Max.
—
3.92
.25
—
3.17
3.67
.45
.30
.23
.13
30.95
31.45
27.90
28.10
.80 BSC
.65
.95
120
30
0°
—
Notes:
Notes
2. Controlling dimension is millimeters.
3. Dimension "B" does not include dambar protrusion. Allowable
dambar protrusion shall be .08mm (.003in.) maximum in excess
of the "B" dimension. Dambar cannot be located on the lower
radius or the foot.
3, 5
5
4. "L" is the length of terminal for soldering to a substrate.
5. "B" & "C" includes lead finish thickness.
4
7°
.10
.20 (.008) Min.
0° Min.
.13 (.005) R Min.
.13/.30
R
.005/.012
D
D1
e
C
PIN 1 IDENTIFIER
E
0.063" Ref (1.60mm)
L
α
Lead Detail
E1
See Lead Detail
Base Plane
A A2
B
A1
REV. 1.0.3 9/11/00
Seating Plane
-CLEAD COPLANARITY
ccc C
17
PRODUCT SPECIFICATION
TMC2246A
Ordering Information
Product
Number
Temperature
Range
Speed
Grade
Screening
Package
Package
Marking
TMC2246AG1C
0°C to 70°C
30 MHz
Commercial
120 Pin Ceramic Pin Grid Array
2246AG1C
TMC2246AG1C1
0°C to 70°C
40 MHz
Commercial
120 Pin Ceramic Pin Grid Array
2246AG1C1
TMC2246AG1C2
0°C to 70°C
60 MHz
Commercial
120 Pin Ceramic Pin Grid Array
2246AG1C2
TMC2246AH5C
0°C to 70°C
30 MHz
Commercial
120 Pin Plastic Pin Grid Array
2246AH5C
TMC2246AH5C1
0°C to 70°C
40 MHz
Commercial
120 Pin Plastic Pin Grid Array
2246AH5C1
TMC2246AH5C2
0°C to 70°C
60 MHz
Commercial
120 Pin Plastic Pin Grid Array
2246AH5C2
TMC2246AH6C
0°C to 70°C
30 MHz
Commercial
120 Lead Metric Quad Flat Pack
to Pin Grid Array
N/A
TMC2246AH6C1
0°C to 70°C
40 MHz
Commercial
120 Lead Metric Quad Flat Pack
to Pin Grid Array
N/A
TMC2246AH6C2
0°C to 70°C
60 MHz
Commercial
120 Lead Metric Quad Flat Pack
to Pin Grid Array
N/A
TMC2246AKEC
0°C to 70°C
30 MHz
Commercial
120 Lead Metric Quad FlatPack
2246AKEC
TMC2246AKEC1
0°C to 70°C
40 MHz
Commercial
120 Lead Metric Quad FlatPack
2246AKEC1
TMC2246AKEC2
0°C to 70°C
60 MHz
Commercial
120 Lead Metric Quad FlatPack
2246AKEC2
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
9/11/00 0.0m 002
Stock#DS30002246A
 2000 Fairchild Semiconductor Corporation