1/4 S t r u c t u r e Product name M o d e l Silicon monolithic integrated circuit Strobe capacitor charging control IC BD4215NUV N o . F e a t u r e s 1. 2. Built-in power transistor Adjustable transformer primary-side peak current to linear current with the I_PEAK pin 3. Charging control switching with the CHARGE_ON pin 4. Includes high precision full charge voltage detection circuit and output pin 5. Various built-in protective circuits (TSD, UVLO, SDP) 6. Built-in IGBT driver 7. Employs small package: VSON010V3030 (3.0 mm×3.0 mm×1.0 mm) ○ Absolute Maximum Ratings（Ta=25°C） Parameter VCC supply voltage Voltage SW pin Current *1 Symbol Rating Unit VCC -0.3 to 7 V VSW 50 V ISW 3 A VOUT pin voltage VVOUT -14 to 50 V Input pin voltage (CHARGE_ON, I_PEAK, FLASH_ON, IGBT_EN) VI -0.3 to 7 V Operating temperature range Topr -20 to +85 °C Storage temperature range Tstg -55 to +150 °C Junction temperature Tjmax 150 °C Power dissipation Pd 1270*2 mW Parameter Symbol Rating Unit VCC supply voltage range VCC 2.6 to 5.5 V ○ Operating Conditions（Ta=25°C） SW pin Voltage VSW 45 V Current *3 ISW 2.5 A VI 0 to VCC V *1 Pulse width: 100 μs *2: Reduced by 10.16 mW/°C at Ta=25°C or more (When mounted on a 74.2 mm×74.2 mm×1.6 mm glass epoxy, 4-layer board: Surface radiating copper foil of 6.28mm2, copper foil laminated in each layer) Input pin voltage (CHARGE_ON, I_PEAK, FLASH_ON, IGBT_EN) ○ Outside marking and dimension (UNIT:mm) ○ Pin No. PIN No. 1 2 3 4 5 6 7 8 9 10 Pin Name PGND IGBT_OUT FLASH_ON XFULL I_PEAK IGBT_EN CHARGE_ON VCC VOUT SW Function Power GND pin IGBT Driver output pin IGBT Driver output start signal input pin Full charge detection signal output pin Ipeak current control signal input pin IGBT Driver operation restriction input pin Charge start signal input pin VCC supply pin Secondary voltage detection pin Switching pin This is not designed for radiation resistance. Notes on this document The Japanese version of this document is the formal specifications. The translated version of the document should be used for reference. If there is any difference between the formal specifications and the translated version, the formal specifications shall take priority. Fig.1 Outside marking and dimension REV. B 2/4 ○ Electrical Characteristics (Ta=25°C,VCC=V(CHARGE_ON)=3.3V, V( I_PEAK)=1.0V,V(FLASH_ON)=0V, V(IGBT_EN)=0V, unless otherwise specified.） Parameter Symbol Min [Overall device] VCC current consumption 1 VCC current consumption 2 VCC current consumption 3 Circuit current during standby operation [Standby control CHARGE_ON pin] CHARGE_ON pin high voltage CHARGE_ON pin low voltage CHARGE_ON pin sink current Unresponsive time when CHARGE_ON shorted IC startup time [Transformer primary-side driver block] SW pin leak peak current SW pin peak current 1 SW pin peak current 2 SW saturation voltage [Charging characteristics adjustment block] I_PEAK sink current Maximum ON time Maximum OFF time [Transformer secondary-side detection block] Full charge detection voltage Full charge detection voltage AC1 XFULL reaction time Full charge detection voltage AC2 VOUT pin sink current OFF detection voltage XFULL pin high side ON resistance XFULL pin low side ON resistance [Protective circuit block] UVLO detection voltage UVLO hysteresis width [IGBT driver block] High-level output short circuit current Low-level output short circuit current FLASH_ON high-level input voltage range FLASH_ON low-level input voltage range FLASH_ON sink current IGBT_EN high-level input voltage range IGBT_EN low-level input voltage range IGBT_EN sink current Target Value Standard Max. Unit Condition Icc1 Icc2 Icc3 ISTB 65 75 115 - 90 95 140 - 145 150 200 1 mA mA mA μA At Output ON, V(I_PEAK)=0V At Output ON, V(I_PEAK)=1V At Output ON, V(I_PEAK)=3V V(CHARGE_ON)=0V VchH VchL I(CHARGE ON) T(CHARGE_ON) TOP 2 12 6 17.5 24 12.5 60 0.6 36 25 130 V V μA μs μs V(CHARGE_ON)=3.3V Time for V(CHARGE_ON)="H"→VSW="L" ISWL IPEAK1 IPEAK2 VSAT 0.77 1.57 - 0.87 1.67 0.3 1 0.97 1.77 0.6 μA A A V V(SW)=45V V(I_PEAK)=0V V(I_PEAK)=3V I(SW)=0.5A I(I PEAK) T(ONMAX) T(OFFMAX) 25 12 2.5 50 25 5 100 50 μA μs μs VOUTTH VOUTTH_AC1 29.7 29.66 30 30.27 30.3 30.87 V V T(XFULL) 160 360 480 nsec VOUTTH_AC2 30.11 30.72 31.33 V I(VOUT) VOFFL RXFULLH RXFULLL 1 -1.3 - 2 -0.5 1 1 4 -0.2 2 2 mA V kΩ kΩ VUVLOL VUVLOHYS 1.9 150 2.05 200 2.2 250 V mV VCC detection (falling) Ioso 90 140 200 mA Iosi 25 40 55 mA VFLASH_ONH VFLASH ONL I(FLASH ON) VIGBT_ENH VIGBT ENL I(IGBT EN) 2 12 2 4.5 24 6.5 0.6 36 0.6 10 V V μA V V μA V(FLASH_ON)=3.3V, V(IGBT_OUT)=0V, V(IGBT_EN)=3.3V, V(CHARGE_ON)=0V V(FLASH_ON)=0V, V(IGBT_OUT)=3.3V, V(IGBT_EN)=3.3V V(IGBT_EN)=3.3V, V(CHARGE_ON)=0V V(IGBT_EN)=3.3V, V(CHARGE_ON)=0V V(FLASH_ON)=3.3V V(FLASH_ON)=3.3V, V(CHARGE_ON)=0V V(FLASH_ON)=3.3V, V(CHARGE_ON)=0V V(IGBT_EN)=3.3V ○ Measurement Circuit Diagram for Full Charge Detection Voltage AC1 ○ Measured according to Fig. 2-1 Measurement Circuit Diagram. Measured according to Fig. 2-1 Measurement Circuit Diagram. Measured according to Fig. 2-2 Measurement Circuit Diagram. V(VOUT)=30V V(XFULL)=VCC-0.5V V(XFULL)=0.5V, V(VOUT)>VOUTTH Measurement Circuit Diagram for Full Charge Detection Voltage AC2 The time lapsed till the XFULL voltage becomes H→L after the VOUT voltage exceeds 30V (XFULL reaction time) and the VCOUT voltage at the time are measured. The VCOUT voltage is measured when the XFULL voltage becomes H→L. XFULL reaction time When the VOUT voltage is 30V or more: Pulse width=1usec Fig.2-1 Measurement Circuit Diagram and Timing Chart ○ When the VF voltage is 3V or more: Pulse width=340nsec Fig.2-2 Measurement Circuit Diagram and Timing Chart Block Diagram REV. B 3/4 OFF time detection Fig.3. Block Diagram ○ UVLO, TSD and SDP VCC OperationUVLO検出により動作停止 stops due to UVLO detection Operation restarts due to UVLO release UVLO解除により動作復帰 ヒステリシス Hysteresis UVLO検出電圧 UVLO detection voltage t V（CHARGE＿ON） t V（VOUT） Operation restarts due to decrease of chip temperature Operation stops due チップ温度上昇により動作停止 to increase of chip チップ温度下降により動作復帰 TSDP t V（cap） Voltage at completion充電完了電圧 of charge t I（ＶＢＡＴ） t A B C D E F G H I Fig.4 Timing Chart: Under Protective Circuit Operation UVLO If the VCC voltage is reduced to the UVLO detection voltage specified in the electrical characteristics or less, the UVLO protective circuit is activated and the charging operation temporarily stops. (See Time ○ C and ○ E in Fig.4.) After that, when the VCC voltage becomes the UVLO release voltage or more, the charging operation automatically restarts. (See Time ○ D and ○ F in Fig.4.) This UVLO also works for the IGBT_OUT pin. If the VCC voltage becomes the UVLO detection voltage or less, the IGBT_OUT voltage is forced to be set to "L". Thermal Shut Down (TSD) It protects the IC against thermal runaway due to excessive temperature rise (Tj>185°C, [TYP]). After detection, the charging operation temporarily stops (See time ○ G in Fig.4.), and when the chip temperature decreases, (Tj<155°C, [TYP]), it automatically restarts. (See Time ○ H in Fig.4.) VOUT pin short detection (SDP) 16 If the VOUT pin becomes the GND level due to any failure and the PowerTr repeats switching 2 (=65536) times which is the SDP count number (TSDP) at the maximum OFF time, it is judged as an error and the charging operation is forced to be stopped. (See Time ○ B in Fig.4.) If the CHARGE_ON pin is changed from "L" to "H" and the UVLO detection is released, it restarts. REV. B 4/4 ○ Precautions for Use 1. Absolute Maximum Rating When impressed voltage, operating temperature range, etc., exceed the absolute maximum rating, the possibility of deterioration or destruction may exist. In addition, it is impossible to assume a destructive situation, such as short circuit mode, open circuit mode, etc. If a special mode exceeding the absolute maximum rating is assumed, please review to provide physical safety means such as fuse, etc. 2. PGND potential (excluding SW, VOUT pins) Maintain the PGND pin potential at the minimum level under the operating conditions. Furthermore, keep the pin except the PGND pin at a voltage higher than the PGND pin voltage including an actual transient phenomenon. However, keep the VOUT pin at a voltage higher than the voltage specified in the absolute maximum ratings. 3. Thermal Design Work out the thermal design with sufficient margin taking power dissipation (Pd) at the actual operation condition into account. 4. Protective circuit The output circuit of this IC does not have a built-in protective circuit against abnormal conditions such as overcurrent protection. Therefore, if a load exceeding the package power is applied or a short circuit occurs, the IC may be damaged. Before use, carefully design the circuit around the set. 5. Short Circuit between Pins and Wrong Mounting Sufficient caution is required for IC direction or displacement when installing IC on PCB. If IC is installed incorrectly, it may be broken. Also, the threat of destruction may exist in short circuits caused by foreign object invasion between outputs or output and GND of the power supply. 6. Common Impedance When providing a power supply and GND wirings, give sufficient consideration to lowering common impedance, reducing ripple (i.e. making thick and short wiring, reducing ripple by LC, etc.) as much as possible. 7. IC Pin Input This is the monolithic IC and has P+ isolation and P substrate for element isolation between each element. By the P layer and N layer of each element, a P-N junction is formed and various parasitic elements are configured. For example, resistor and transistor are connected to a pin as shown in Fig.-5; ○P-N junction operates as a parasitic diode when GND > (Pin A) in the case of the resistor, and when GND > (Pin B) in the case of the transistor (NPN). ○Also, a parasitic NPN transistor operates by the N layer of another element adjacent to the previous diode in the case of a transistor (NPN) when GND > (Pin B). The parasitic element consequently emerges through the potential relationship because of IC’s structure. The parasitic element pulls interference out of the circuit which may be the cause of malfunction or destruction. Therefore, excessive caution is required to avoid operation of the parasitic element which is caused by applying voltage to the input pin lower than GND (P board), etc. Transistor (NPN) B E C （Pin A） ～ ～ Resistor （Pin B） GND P N + P N N N P substrate P P+ P N P substrate Parasitic element Parasitic element N N Parasitic element （Pin A） + ～ ～ P + GND Fig.5 Simplified Structure Example, Bipolar IC REV. B GND Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. 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