Digital Multi-Phase GPU Buck Controller FEATURES CHL8266 DESCRIPTION GPU-compliant Digital PWM Controller Programmable 1-phase to 6-phase operation Configurable switching frequency from 200 kHz to 1MHz per phase with accuracy better than 2% IR Dynamic Phase Control 1-phase to 2-phase PSI for Light Loads Adaptive Transient Algorithm minimizes output bulk capacitors Enables Thermal Phase Balancing SMBus interface for configuring and monitoring Compatible with IR ATL Drivers and Tri-state Drivers Nine bytes of NVM storage available for customer use The CHL8266 is a 6-phase digital synchronous buck controller for regulation of high-performance GPU platforms. The CHL8266 output VID table is fully compliant with VR11.1 specifications. The CHL8266 deploys a number of efficiency shaping features. PSI can be programmed to be up to four phases for optimum light-load efficiency, and the controller can autonomously add/drop phases from mid to high and back to mid current ranges to deliver 90+% efficiency across the entire load range. IR’s unique Adaptive Transient Algorithm, based on nonlinear digital PWM algorithms, minimizes output bulk capacitors. CHL8266 supports NTC temperature sense to report temperature and trigger VR HOT and OTP faults. Digital thermal balancing allows proportional current imbalance between phases. +3.3V supply voltage; 0ºC to 85ºC Ambient operation RoHS Compliant, MSL level 1 package The CHL8266 provides extensive OVP, UVP, OCP and OTP fault protection. Device and fault configuration parameters are easily defined using the IR Digital Power Design Center (DPDC) GUI and stored in on-chip non-volatile memory (NVM). APPLICATIONS High performance GPU Voltage Regulation solutions High Current and High-Efficiency Applications The 2-pin SMBus interface can be used to monitor a variety of operating parameters on CHL8266 based VRs. The CHL8266 truly simplifies VRD design and enables fastest time-to-market with its “set-and-forget” methodology. PWM1_L2 Power Stage 6 ISEN1_L2 IRTN1_L2 Figure 1: CHL8266 Basic Application Circuit 1 October 12, 2011 | FINAL | V1.05 ISEN6 IRTN6 ISEN5 IRTN5 ISEN4 IRTN4 ISEN3 ISEN2 IRTN3 IRTN2 ISEN1 33 PWM4 VRTN 5 32 PWM3 31 PWM2 30 PWM1 29 28 NC 27 SADDR 6 TP2 7 RRES 8 VINSEN 9 TSEN CHL8266 48 Pin 7mmx 7mm QFN TOP VIEW GND 10 PWM5 VCC EN 11 26 NC VR_HOT V18A 12 25 VR_READY 13 14 15 16 17 18 19 20 21 22 23 24 TP3 VCC 3.3V 4 VID1 ISEN4 IRTN4 PWM6 VGPU VID2 Power Stage 5 35 34 VID3 PWM4 ... VCC 3 TP4 SV_DIO SDA V_GPU 36 2 VID4 SCL Power Stage 2 1 VID5 SV_CLK PWM2 ISEN2 IRTN2 RCSP RCSM VCC TP5 ENABLE ISEN1 IRTN1 PSI# ENABLE 48 47 46 45 44 43 42 41 40 39 38 37 TP1 VR_HOT# VR_HOT# 12V Power Stage 1 SCL PWM1 SDA CHL8266 VR_RDY VR_RDY IRTN1 PIN DIAGRAM BASIC APPLICATION Figure 2: CHL8266 Package Top View Digital Multi-Phase GPU Buck Controller CHL8266 ORDERING INFORMATION CHL8266 - Package QFN Tape & Reel Qty 3000 Part Number CHL8266-CRT QFN 3000 CHL8266-xxCRT T – Tape and Reel ISEN6 IRTN6 ISEN5 IRTN5 ISEN4 ISEN3 ISEN2 IRTN3 IRTN2 ISEN1 IRTN1 C – Operating Temperature (Commercial Standard) XX – Configuration File ID IRTN4 Notes: 1. “xx” indicates customer specific configuration file. R – Package Type (DFN) 48 47 46 45 44 43 42 41 40 39 38 37 RCSP 1 36 VCC RCSM VCC 2 PWM6 3 35 34 VGPU 4 33 PWM4 VRTN 5 32 PWM3 SADDR 6 31 PWM2 TP2 7 30 PWM1 RRES 8 NC VINSEN 9 29 28 27 CHL8266 48 Pin 7mmx 7mm QFN TOP VIEW GND VCC TSEN 10 EN 11 26 NC VR_HOT V18A 12 25 VR_READY TP3 VID1 VID2 VID3 VID4 TP4 VID5 TP5 PSI# SCL TP1 SDA 13 14 15 16 17 18 19 20 21 22 23 24 Figure 3: CHL8266 Top View Enlarged 2 PWM5 October 12, 2011 | FINAL | V1.05 1