Preliminary Data Sheet No. PD60034-J IR2151 (NOTE: For new designs, we recommend IR’s new products IR2153 and IR21531) SELF-OSCILLATING HALF-BRIDGE DRIVER Features Product Summary • Floating channel designed for bootstrap operation • • Fully operational to +600V Tolerant to negative transient voltage dV/dt immune Undervoltage lockout Programmable oscillator frequency f= 1 1.4 × (RT + 75Ω) × CT • Matched propagation delay for both channels • Low side output in phase with RT VOFFSET 600V max. Duty Cycle 50% IO+/- 100 mA / 210 mA VOUT 10 - 20V Deadtime (typ.) 1.2 µs Packages Description The IR2151 is a high voltage, high speed, self-oscillating power MOSFET and IGBT driver with both high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The front end features a programmable oscillator which is similar to the 555 timer. The output drivers feature a high pulse current buffer stage and an internal deadtime designed for minimum driver cross-conduction. Propagation delays for the two channels are matched to simplify use in 50% duty cycle applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration that operates off a high voltage rail up to 600 volts. 8 Lead PDIP 8 Lead SOIC Typical Connection up to 600V VCC VB RT HO CT VS COM LO TO LOAD (Refer to Lead Assignment diagram for correct pin configuration) 1 IR2151 Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition VB High side floating supply voltage Min. Max. -0.3 625 VB + 0.3 VS High side floating supply offset voltage VB - 25 VHO High side floating output voltage VS - 0.3 VB + 0.3 VLO Low side output voltage -0.3 VCC + 0.3 VRT RT voltage -0.3 VCC + 0.3 VCT CT voltage -0.3 VCC + 0.3 ICC Supply current (note 1) — 25 IRT RT output current -5 5 Allowable offset supply voltage transient — 50 dV s/dt Package power dissipation @ TA ≤ +25°C PD RθJA Thermal resistance, junction to ambient (8 lead DIP) — 1.0 (8 lead SOIC) — 0.625 (8 lead DIP) — 125 (8 lead SOIC) 200 150 TJ Junction temperature — — TS Storage temperature -55 150 TL Lead temperature (soldering, 10 seconds) — 300 Units V mA V/ns W °C/W °C Recommended Operating Conditions The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The VS offset rating is tested with all supplies biased at 15V differential. Symbol Definition Min. Max. Units VB High side sloating supply absolute voltage VS + 10 VS + 20 VS High side floating supply offset voltage — 600 VHO High side floating output voltage VS VB VLO Low side output voltage 0 VCC ICC Supply current (note 1) — 5 mA TA Ambient temperature -40 125 °C Note 1: V Because of the IR2151’s application specificity toward off-line supply systems, this IC contains a zener clamp structure between the chip VCC and COM which has a nominal breakdown voltage of 15.6V. Therefore, the IC supply voltage is normally derived by forcing current into the supply lead (typically by means of a high value resistor connected between the chip VCC and the rectified line voltage and a local decoupling capacitor from VCC to COM) and allowing the internal zener clamp circuit to determine the nominal supply voltage. Therefore, this circuit should not be driven by a DC, low impedance power source of greater than VCLAMP . 2 IR2151 Dynamic Electrical Characteristics VBIAS (VCC, VBS) = 12V, C L = 1000 pF and TA = 25°C unless otherwise specified. Symbol Definition Min. Typ. Max. Units Test Conditions tr Turn-on rise time — 80 120 tf Turn-off fall time — 40 70 0.50 1.20 2.25 µs 48 50 52 % DT D Deadtime RT duty cycle ns Static Electrical Characteristics VBIAS (VCC, VBS) = 12V, CL = 1000 pF, CT = 1 nF and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to COM. The VO and I O parameters are referenced to COM and are applicable to the respective output leads: HO or LO. Symbol fOSC VCLAMP Definition Min. Typ. Max. Units Test Conditions Oscillator frequency 19.4 20.0 20.6 94 100 106 kHz RT = 35.7 kΩ RT = 7.04 kΩ VCC zener shunt clamp voltage 14.4 15.6 16.8 VCT+ 2/3 VCC threshold 7.8 8.0 8.2 VCT- 1/3 VCC threshold 3.8 4.0 4.2 CT undervoltage lockout — 20 50 2.5V<VCC<VCCUV+ RT high level output voltage, VCC - RT — 0 100 IRT = -100 µA — 200 300 IRT = -1 mA VCTUV VRT+ VRTVRTUV RT Low Level Output Voltage — 20 50 — 200 300 ICC = 5 mA V IRT = 100 µA mV IRT = 1 mA RT Undervoltage Lockout, VCC - RT — 0 100 2.5V<VCC<VCCUV+ VOH High Level Output Voltage, VBIAS - VO — — 100 IO = 0A VOL Low Level Output Voltage, VO — — 100 IO = 0A VB = VS = 600V ILK Offset Supply Leakage Current — — 50 IQBS Quiescent VBS Supply Current — 10 50 IQCC Quiescent VCC Supply Current — 400 950 CT Input Current — 0.001 1.0 VCCUV+ ICT VCC Supply Undervoltage Positive Going Threshold 7.7 8.4 9.2 VCCUV- VCC Supply Undervoltage Negative Going Threshold 7.4 8.1 8.9 VCCUVH VCC Supply Undervoltage Lockout Hysteresis 200 500 — IO+ Output High Short Circuit Pulsed Current 100 125 — IO- Output Low Short Circuit Pulsed Current 210 250 — µA V 3 mV mA VO = 0V VO = 15V IR2151 Functional Block Diagram VB R HV LEVEL SHIFT RT + R CT R Q S Q DEAD TIME Q PULSE FILTER R S PULSE GEN HO VS V CC 15.6V + UV DETECT R DEAD TIME LO DELAY COM Lead Definitions Symbol Description RT CT Oscillator timing resistor input,in phase with LO for normal IC operation Oscillator timing capacitor input, the oscillator frequency according to the following equation: f= VB HO VS VCC LO COM 1 1.4 × (RT + 75Ω) × CT where 75Ω is the effective impedance of the RT output stage High side floating supply High side gate drive output High side floating supply return Low side and logic fixed supply Low side gate drive output Low side return Lead Assignments 8 Lead DIP 8 Lead SOIC IR2151 IR2151S 4 IR2151 8 Lead PDIP 01-3003 01 8 Lead SOIC 01-0021 08 5 IR2151 VCLAMP V CCUV+ VCC RT (HO) 50% 50% RT CT RT (LO) tf tr HO 90% LO HO LO Figure 1. Input/Output Timing Diagram 10% 90% 10% Figure 2. Switching Time Waveform Definitions RT 50% 50% 90% HO 10% DT LO 90% 10% Figure 3. Deadtime Waveform Definitions WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 http://www.irf.com/ Data and specifications subject to change without notice. 3/30/2001 6