TC55VBM316AFTN/ASTN40,55 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 524,288-WORD BY 16-BIT/1,048,576-WORD BY 8-BIT FULL CMOS STATIC RAM DESCRIPTION The TC55VBM316AFTN/ASTN is a 8,388,608-bit static random access memory (SRAM) organized as 524,288 words by 16 bits/1,048,576 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3 mA/MHz and a minimum cycle time of 40 ns. It is automatically placed in low-power mode at 0.7 µA standby current (at VDD = 3 V, Ta = 25°C, typical) when chip enable ( CE1 ) is asserted high or (CE2) is asserted low. There are three control inputs. CE1 and CE2 are used to select the device and for data retention control, and output enable ( OE ) provides fast memory access. Data byte control pin ( LB , UB ) provides lower and upper byte access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating extreme temperature range of −40° to 85°C, the TC55VBM316AFTN/ASTN can be used in environments exhibiting extreme temperature conditions. The TC55VBM316AFTN/ASTN is available in a plastic 48-pin thin-small-outline package (TSOP). FEATURES • • • • • • • 3.6 V 10 µA 3.0 V 5 µA Access Times (maximum): • Low-power dissipation Operating: 9 mW/MHz (typical) Single power supply voltage of 2.3 to 3.6 V Power down features using CE1 and CE2 Data retention supply voltage of 1.5 to 3.6 V Direct TTL compatibility for all inputs and outputs Wide operating temperature range of −40° to 85°C Standby Current (maximum): TC55VBM316AFTN/ASTN Access Time 40 55 40 ns 55 ns CE1 Access Time 40 ns 55 ns CE2 Access Time 40 ns 55 ns OE Access Time 25 ns 30 ns Package: TSOPⅠ48-P-1220-0.50 (AFTN) (Weight:0.51 g typ) TSOPⅠ48-P-1214-0.50 (ASTN) (Weight:0.36 g typ) • PIN ASSIGNMENT (TOP VIEW) PIN NAMES 48 PIN TSOP 1 48 A0~A18 Address Inputs (Word Mode) A-1~A18 Address Inputs (Byte Mode) CE1 , CE2 Chip Enable R/W Read/Write Control OE Output Enable LB , UB 24 I/O1~I/O16 25 Byte (×8 mode) Enable BYTE (Normal) Data Byte Control Data Inputs/Outputs VDD Power GND Ground NC No Connection OP* Option *: OP pin must be open or connected to GND. Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name A15 A14 A13 A12 A11 A10 A9 A8 NC NC R/W CE2 OP UB LB A18 Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name A17 A7 A6 A5 A4 A3 A2 A1 A0 CE1 GND OE I/O1 I/O9 I/O2 I/O10 Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 Pin Name I/O3 I/O11 I/O4 I/O12 VDD I/O5 45 46 47 I/O16 GND BYTE /A-1 I/O13 I/O6 I/O14 I/O7 I/O15 I/O8 2002-08-05 48 A16 1/15 TC55VBM316AFTN/ASTN40,55 BLOCK DIAGRAM DATA INPUT BUFFER I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 ROW ADDRESS DECODER ROW ADDRESS REGISTER VDD GND MEMORY CELL ARRAY 4,096 × 128 × 16 (8,388,608) DATA OUTPUT BUFFER I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 DATA INPUT BUFFER ROW ADDRESS BUFFER CE SENSE AMP DATA OUTPUT BUFFER A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A17 A18 COLUMN ADDRESS DECODER COLUMN ADDRESS REGISTER COLUMN ADDRESS BUFFER CLOCK GENERATOR CE A-1 A0 A1 A2 A3 A4 A5 A16 CE1 CE2 LB CE UB R/W OE BYTE 2002-08-05 2/15 TC55VBM316AFTN/ASTN40,55 OPERATING MODE MODE Read Write Output Deselect Standby CE1 CE2 OE R/W BYTE LB UB I/O1~I/O8 I/O9~I/O15 I/O16 POWER L H L H L * * Output High-Z A-1 IDDO L H L H H L L Output Output Output IDDO L H L H H H L High-Z Output Output IDDO L H L H H L H Output High-Z High-Z IDDO L H * L L * * Input High-Z A-1 IDDO L H * L H L L Input Input Input IDDO L H * L H H L High-Z Input Input IDDO L H * L H L H Input High-Z High-Z IDDO L H H H L * * High-Z High-Z A-1 IDDO L H H H H L L High-Z High-Z High-Z IDDO L H H H H H L High-Z High-Z High-Z IDDO L H H H H L H High-Z High-Z High-Z IDDO H * * * H or L * * High-Z High-Z High-Z IDDS * L * * H or L * * High-Z High-Z High-Z IDDS * * * * H H H High-Z High-Z High-Z IDDS * = don't care H = logic high L = logic low MAXIMUM RATINGS SYMBOL RATING VALUE UNIT VDD Power Supply Voltage −0.3~4.2 V VIN Input Voltage −0.3*~4.2 V VI/O Input/Output Voltage −0.5~VDD + 0.5 V PD Power Dissipation 0.6 W Tsolder Soldering Temperature (10s) 260 °C Tstg Storage Temperature −55~150 °C Topr Operating Temperature −40~85 °C *: −2.0 V when measured at a pulse width of 20ns DC RECOMMENDED OPERATING CONDITIONS (Ta = −40° to 85°C) SYMBOL PARAMETER VDD Power Supply Voltage VIH Input High Voltage VIL Input Low Voltage VDH Data Retention Supply Voltage MIN TYP MAX UNIT 2.3 3.6 V VDD + 0.3 V −0.3* VDD × 0.24 V 1.5 3.6 V VDD = 2.3 V~2.7 V 2.0 VDD = 2.7 V~3.6 V 2.2 *: −2.0 V when measured at a pulse width of 20ns 2002-08-05 3/15 TC55VBM316AFTN/ASTN40,55 DC CHARACTERISTICS (Ta = −40° to 85°C, VDD = 2.3 to 3.6 V) SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT ±1.0 µA IIL Input Leakage Current VIN = 0 V~VDD IOH Output High Current VOH = VDD − 0.5 V −0.5 mA IOL Output Low Current VOL = 0.4 V 2.1 mA ILO Output Leakage Current CE1 = VIH or CE2 = VIL or LB = UB = VIH or R/W = VIL or OE = VIH, VOUT = 0 V~VDD ±1.0 µA MIN 35 1 µs 8 MIN 30 1 µs 3 1 10 0.7 lDDO1 Operating Current lDDO2 CE1 = VIL and CE2 = VIH and R/W = VIH, LB = UB = VIL, IOUT = 0 mA, Other Input = VIH/VIL tcycle CE1 = 0.2 V and CE2 = VDD − 0.2 V and R/W = VDD − 0.2 V, LB = UB = 0.2 V, IOUT = 0 mA, Other Input = VDD − 0.2 V/0.2 V tcycle mA mA IDDS1 1) CE1 = VIH or CE2 = VIL (at BYTE ≥ VDD − 0.2 V or ≤ 0.2 V) 2) LB = UB = VIH (at BYTE ≥ VDD − 0.2 V) IDDS2 1) CE1 = VDD − 0.2 V, CE2 = VDD = Ta = −40~85°C VDD − 0.2 V (at BYTE ≥ VDD 3.3 V ± 0.3 V − 0.2 V or ≤ 0.2 V) Ta = 25°C 2) CE2 = 0.2 V (at BYTE ≥ VDD − 0.2 V or ≤ 0.2 V) VDD = 3.0 V Ta = −40~40°C 3) LB = UB = VDD − 0.2 V, CE1 = 0.2 V, CE2 = VDD − 0.2 Ta = −40~85°C V (at BYTE ≥ VDD − 0.2 V) Standby Current mA µA 2 5 CAPACITANCE (Ta = 25°C, f = 1 MHz) SYMBOL PARAMETER TEST CONDITION MAX UNIT CIN Input Capacitance VIN = GND 10 pF COUT Output Capacitance VOUT = GND 10 pF Note: This parameter is periodically sampled and is not 100% tested. 2002-08-05 4/15 TC55VBM316AFTN/ASTN40,55 AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = −40° to 85°C, VDD = 2.7 to 3.6 V) READ CYCLE TC55VBM316AFTN/ASTN SYMBOL PARAMETER 40 UNIT 55 MIN MAX MIN MAX tRC Read Cycle Time 40 55 tACC Address Access Time 40 55 tCO1 Chip Enable( CE1 ) Access Time 40 55 tCO2 Chip Enable(CE2) Access Time 40 55 tOE Output Enable Access Time 25 30 tBA Data Byte Control Access Time 40 55 tCOE Chip Enable Low to Output Active 5 5 tOEE Output Enable Low to Output Active 0 0 tBE Data Byte Control Low to Output Active 5 5 tOD Chip Enable High to Output High-Z 20 25 tODO Output Enable High to Output High-Z 20 25 tBD Data Byte Control High to Output High-Z 20 25 tOH Output Data Hold Time 10 10 ns WRITE CYCLE TC55VBM316AFTN/ASTN SYMBOL PARAMETER 40 UNIT 55 MIN MAX MIN MAX tWC Write Cycle Time 40 55 tWP Write Pulse Width 30 40 tCW Chip Enable to End of Write 35 45 tBW Data Byte Control to End of Write 35 45 tAS Address Setup Time 0 0 tWR Write Recovery Time 0 0 tODW R/W Low to Output High-Z 20 25 tOEW R/W High to Output Active 0 0 tDS Data Setup Time 20 25 tDH Data Hold Time 0 0 Note: ns tOD, tODO, tBD and tODW are specified in time when an output becomes high impedance, and are not judged depending on an output voltage level. 2002-08-05 5/15 TC55VBM316AFTN/ASTN40,55 AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = −40° to 85°C, VDD = 2.3 to 3.6 V) READ CYCLE TC55VBM316AFTN/ASTN SYMBOL PARAMETER 40 UNIT 55 MIN MAX MIN MAX tRC Read Cycle Time 55 70 tACC Address Access Time 55 70 tCO1 Chip Enable( CE1 ) Access Time 55 70 tCO2 Chip Enable(CE2) Access Time 55 70 tOE Output Enable Access Time 30 35 tBA Data Byte Control Access Time 55 70 tCOE Chip Enable Low to Output Active 5 5 tOEE Output Enable Low to Output Active 0 0 tBE Data Byte Control Low to Output Active 5 5 tOD Chip Enable High to Output High-Z 25 30 tODO Output Enable High to Output High-Z 25 30 tBD Data Byte Control High to Output High-Z 25 30 tOH Output Data Hold Time 10 10 ns WRITE CYCLE TC55VBM316AFTN/ASTN SYMBOL PARAMETER 40 UNIT 55 MIN MAX MIN MAX tWC Write Cycle Time 55 70 tWP Write Pulse Width 40 50 tCW Chip Enable to End of Write 45 55 tBW Data Byte Control to End of Write 45 55 tAS Address Setup Time 0 0 tWR Write Recovery Time 0 0 tODW R/W Low to Output High-Z 25 30 tOEW R/W High to Output Active 0 0 tDS Data Setup Time 25 30 tDH Data Hold Time 0 0 Note: ns tOD, tODO, tBD and tODW are specified in time when an output becomes high impedance, and are not judged depending on an output voltage level. 2002-08-05 6/15 TC55VBM316AFTN/ASTN40,55 AC TEST CONDITIONS PARAMETER TEST CONDITION 0.2 V, VDD × 0.7 V + 0.2 V Input pulse level t R, t F 1V / ns(Fig.1) Timing measurements VDD × 0.5 Reference level VDD × 0.5 30 pF + 1 TTL Gate(Fig.2) Output load Fig.1 : Input rise and fall time Fig.2 : Output load VTM VDD Typ 90% 90% 10% 10% GND 1 V/ns R1 Dout R1 = 810 Ω R2 = 1610 Ω VTM = 2.3 V 1 V/ns tR tF R2 30 pF BYTE FUNCTION SYMBOL PARAMETER MIN MAX UNIT tBS BYTE Setup Time 5 ms tBR BYTE Recovery Time 5 ms TIMING DIAGRAMS BYTE CE2 CE1 tBS tBR BYTE 2002-08-05 7/15 TC55VBM316AFTN/ASTN40,55 READ CYCLE (See Note 1) tRC Address A0~A18 (Word Mode) A-1~A18 (Byte Mode) tACC tCO1 tOH CE1 tCO2 CE2 tOE tOD OE tBA tODO UB , LB DOUT I/O1~16 (Word Mode) tBE tOEE tBD VALID DATA OUT Hi-Z Hi-Z tCOE I/O1~8 (Byte Mode) WRITE CYCLE 1 (R/W CONTROLLED) (See Note 4) tWC Address A0~A18 (Word Mode) A-1~A18 (Byte Mode) tAS tWP tWR R/W tCW CE1 tCW CE2 tBW UB , LB tODW tOEW DOUT I/O1~16 (Word Mode) (See Note 2) Hi-Z (See Note 3) I/O1~8 (Byte Mode) tDS tDH DIN I/O1~16 (Word Mode) (See Note 5) VALID DATA IN (See Note 5) I/O1~8 (Byte Mode) 2002-08-05 8/15 TC55VBM316AFTN/ASTN40,55 WRITE CYCLE 2 ( CE1 CONTROLLED) (See Note 4) tWC Address A0~A18 (Word Mode) A-1~A18 (Byte Mode) tAS tWP tWR R/W tCW CE1 tCW CE2 tBW UB , LB tBE DOUT I/O1~16 (Word Mode) Hi-Z I/O1~8 (Byte Mode) tODW Hi-Z tCOE tDS DIN I/O1~16 (Word Mode) tDH VALID DATA IN (See Note 5) I/O1~8 (Byte Mode) WRITE CYCLE 3 (CE2 CONTROLLED) (See Note 4) tWC Address A0~A18 (Word Mode) A-1~A18 (Byte Mode) tAS tWP tWR R/W tCW CE1 tCW CE2 tBW UB , LB tBE DOUT I/O1~16 (Word Mode) Hi-Z I/O1~8 (Byte Mode) tODW Hi-Z tCOE tDS DIN I/O1~16 (Word Mode) (See Note 5) tDH VALID DATA IN I/O1~8 (Byte Mode) 2002-08-05 9/15 TC55VBM316AFTN/ASTN40,55 WRITE CYCLE 4 ( UB, LB CONTROLLED) (See Note 4) tWC Address A0~A18 (Word Mode) tAS tWP tWR R/W tCW CE1 tCW CE2 tBW UB , LB tBE DOUT I/O1~16 (Word Mode) Hi-Z tODW Hi-Z tCOE tDS DIN I/O1~16 (Word Mode) Note: (1) (See Note 5) tDH VALID DATA IN R/W remains HIGH for the read cycle. (2) If CE1 (or UB or LB ) goes LOW(or CE2 goes HIGH) coincident with or after R/W goes LOW, the outputs will remain at high impedance. (3) If CE1 (or UB or LB ) goes HIGH(or CE2 goes LOW) coincident with or before R/W goes HIGH, the outputs will remain at high impedance. (4) If OE is HIGH during the write cycle, the outputs will remain at high impedance. (5) Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. 2002-08-05 10/15 TC55VBM316AFTN/ASTN40,55 DATA RETENTION CHARACTERISTICS (Ta = −40° to 85°C) SYMBOL PARAMETER VDH MIN TYP MAX UNIT 1.5 3.6 V VDH = 3.6 V Ta = −40~85°C 10 Ta = −40~40°C 2 Ta = −40~85°C 5 Data Retention Supply Voltage IDDS2 Standby Current VDH = 3.0 V µA tCDR Chip Deselect to Data Retention Mode Time 0 ns tR Recovery Time 5 ms CE1 CONTROLLED DATA RETENTION MODE VDD VDD (See Note 1) DATA RETENTION MODE 2.3 V (See Note 2) (See Note 2) VIH tCDR VDD − 0.2 V CE1 tR GND CE2 CONTROLLED DATA RETENTION MODE VDD VDD (See Note 3) DATA RETENTION MODE 2.3 V CE2 VIH tCDR tR VIL 0.2 V GND UB , LB CONTROLLED DATA RETENTION MODE VDD VDD (See Note 4) DATA RETENTION MODE 2.3 V (See Note 5) (See Note 5) VIH tCDR UB , LB VDD − 0.2 V tR GND 2002-08-05 11/15 TC55VBM316AFTN/ASTN40,55 Note: (1) In CE1 controlled data retention mode, minimum standby current mode is entered when CE2 ≤ 0.2 V or CE2 ≥ VDD − 0.2 V. (2) When CE1 is operating at the VIH(min.) level, the operating current is given by IDDS1 during the transition of VDD from 2.3(2.7) to 2.2V(2.4 V). (3) In CE2 controlled data retention mode, minimum standby current mode is entered when CE2 ≤ 0.2 V. (4) In UB (or LB ) controlled data retention mode, minimum standby current mode is entered when CE1 ≤ 0.2 V or CE1 ≥ VDD − 0.2 V, CE2 ≤ 0.2 V or CE2 ≥ VDD − 0.2 V. (5) When UB (or LB ) is operating at the VIH(min.) level, the operating current is given by IDDS1 during the transition of VDD from 2.3(2.7) to 2.2V(2.4 V). 2002-08-05 12/15 TC55VBM316AFTN/ASTN40,55 PACKAGE DIMENSIONS Unit:mm 0.25 typ 18.4 0.1 0.145 0.055 20.0 0.2 1.0 0.1 0.1 12.4max 25 12.0 0.1 24 0.1 0.05 1.2max 0~10 48 0.5 1 0.22 0.08 0.08 M TSOPⅠ48-P-1220-0.50 0.5 0.1 Weight:0.51 g (typ) 2002-08-05 13/15 TC55VBM316AFTN/ASTN40,55 PACKAGE DIMENSIONS Unit:mm 0.08 M TSOPⅠ48-P-1214-0.50 0.1 25 12.4 0.1 0.145 0.055 14.0 0.2 1.0 0.1 0.1 0.05 1.2max 0~10 0.25 typ 24 12.4max 0.5 0.22 0.08 48 12.0 0.1 1 0.5 0.1 Weight:0.36 g (typ) 2002-08-05 14/15 TC55VBM316AFTN/ASTN40,55 RESTRICTIONS ON PRODUCT USE 000707EBA • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice. 2002-08-05 15/15