TOSHIBA TC51WKM616AXBN75

TC51WKM616AXBN75
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
4,194,304-WORD BY 16-BIT CMOS PSEUDO STATIC RAM
DESCRIPTION
The TC51WKM616AXBN is a 67,108,864-bit pseudo static random access memory(PSRAM) organized as
4,194,304 words by 16 bits. Using Toshiba’s CMOS technology and advanced circuit techniques, it provides high
density, high speed and low power. The device uses dual power supplies(2.6 to 3.3 V for core and 1.7 to 2.2 V for
output buffer). The device also features SRAM-like W/R timing whereby the device is controlled by CE1 , OE , and
WE on asynchronous. The device has the page access operation. Page size is 8 words. The device also supports
deep power-down mode, realizing low-power standby.
•
FEATURES
•
•
•
•
•
•
•
Organized as 4,194,304 words by 16 bits
Dual power supplies(2.6 to 3.3 V for core and
1.7 to 2.2 V for output buffer)
Direct TTL compatibility for all inputs and outputs
Deep power-down mode: Memory cell data invalid
Page operation mode:
Page read operation by 8 words
Logic compatible with SRAM R/W ( WE ) pin
Standby current
Standby
100 µA
Deep power-down standby
5 µA
PIN ASSIGNMENT (TOP VIEW)
1
2
3
4
5
•
Access Times:
Access Time
75 ns
CE1 Access Time
75 ns
OE Access Time
25 ns
Page Access Time
30 ns
Package:
P-TFBGA48-0811-0.75BZ (Weight:
PIN NAMES
6
A0 to A21
Address Inputs
A0 to A2
Page Address Inputs
A
LB
OE
A0
A1
A2
CE2
B
I/O9
UB
A3
A4
CE1
I/O1
C
I/O10
I/O11
A5
A6
I/O2
I/O3
CE1
Chip Enable Input
D
VSS
I/O12
A17
A7
I/O4
VDD
CE2
Chip select Input
WE
Write Enable Input
Output Enable Input
I/O1 to I/O16 Data Inputs/Outputs
E
VDDQ I/O13
A21
A16
I/O5
VSS
F
I/O15 I/O14
A14
A15
I/O6
I/O7
OE
LB , UB
G
I/O16
A19
A12
A13
WE
I/O8
H
A18
A8
A9
A10
A11
A20
(FBGA48)
g typ.)
VDD
Data Byte Control Inputs
Power Supply for Core
VDDQ
Power Supply for Output Buffer
GND
Ground
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TC51WKM616AXBN75
BLOCK DIAGRAM
CE
DATA INPUT
BUFFER
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
ROW ADDRESS
DECODER
VDD
GND
MEMORY CELL ARRAY
8,192 × 512 × 16
(67,108,864)
DATA OUTPUT
BUFFER
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
DATA INPUT
BUFFER
ROW ADDRESS BUFFER
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
DATA OUTPUT
BUFFER
SENSE AMP
COLUMN ADDRESS
DECODER
COLUMN ADDRESS
BUFFER
REFRESH
ADDRESS
COUNTER
REFRESH
CONTROL
CONTROL SIGNAL A0 A1 A2 A3 A4 A5 A6 A7 A8
GENERATOR
CE
WE
OE
UB
LB
CE1
CE
CE2
OPERATION MODE
MODE
CE1
CE2
OE
WE
Read(Word)
L
H
L
H
Read(Lower Byte)
L
H
L
H
LB
UB
Add
I/O1 to I/O8
I/O9 to I/O16
POWER
L
L
X
DOUT
DOUT
IDDO
L
H
X
DOUT
High-Z
IDDO
IDDO
Read(Upper Byte)
L
H
L
H
H
L
X
High-Z
DOUT
Write(Word)
L
H
X
L
L
L
X
DIN
DIN
IDDO
Write(Lower Byte)
L
H
X
L
L
H
X
DIN
Invalid
IDDO
Write(Upper Byte)
L
H
X
L
H
L
X
Invalid
DIN
IDDO
Outputs Disabled
L
H
H
H
X
X
X
High-Z
High-Z
IDDO
Standby
H
H
X
X
X
X
X
High-Z
High-Z
IDDS
Deep Power-down Standby
H
L
X
X
X
X
X
High-Z
High-Z
IDDSD
Notes: L = Low-level Input(VIL),
H = High-level Input(VIH),
X = VIH or VIL, High-Z = High-impedance
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TC51WKM616AXBN75
ABSOLUTE MAXIMUM RATINGS (See Note 1)
SYMBOL
RATING
VALUE
UNIT
−1.0 to 3.6
V
−1.0 to VDD + 0.5 (3.6 V Max)
V
−1.0 to 3.6
V
−1.0 to VDDQ + 0.5
V
VDD
Power Supply Voltage
VDDQ
Output Buffer Power Supply Voltage
VIN
Input Voltage for Address and Control Pins
VI/O
Input/Output Voltage for I/O Pins
Topr.
Operating Temperature
−25 to 85
°C
Tstrg.
Storage Temperature
−55 to 150
°C
Tsolder
Soldering Temperature (10 s)
260
°C
PD
Power Dissipation
0.6
W
IOUT
Short Circuit Output Current
50
mA
DC RECOMMENDED OPERATING CONDITIONS (Ta = −25°C to 85°C)
SYMBOL
PARAMETER
MIN
TYP.
MAX
VDD
Power Supply Voltage
2.6
2.75
3.3
VDDQ
Output Buffer Power Supply Voltage
1.7
1.8
2.2
Input High Voltage for Address and Control Pins
1.6

VDD + 0.3*
Input High Voltage for I/O Pins
1.6

VDDQ + 0.3*
−0.3*

0.4
VIH
VIL
Input Low Voltage
UNIT
V
* : VIH(Max) VDD+1.0 V/ VDDQ+1.0 V with 10 ns pulse width
VIL(Min) -1.0 V with 10 ns pulse width
DC CHARACTERISTICS (Ta = −25°C to 85°C, VDD = 2.6 to 3.3 V, VDDQ = 1.7 to 2.2 V)
(See Note 3 to 4)
SYMBOL
PARAMETER
TEST CONDITION
MIN
TYP.
MAX
UNIT
IIL
Input Leakage Current
VIN = 0 V to VDDQ
−1.0

+1.0
µA
ILO
Output Leakage Current
Output disable, VOUT = 0 V to VDD
−1.0

+1.0
µA
VOH
Output High Voltage
IOH = − 100 µA
VDDQ − 0.2


V
VOL
Output Low Voltage
IOL = 100 µA


0.2
V
IDDO1
Operating Current
CE1 = VIL
CE2 = VIH, IOUT = 0 mA
tRC = min


50
mA
IDDO2
Page Access Operating Current
CE1 = VIL, CE2 = VIH,
t = min
Page add. cycling, IOUT = 0 mA PC


25
mA
IDDS
Standby Current(MOS)
CE1 = VDD − 0.2 V, CE2 = VDD − 0.2 V


70
µA
IDDSD
Deep Power-down Standby Current
CE2 = 0.2 V


5
µA
CAPACITANCE (Ta = 25°C, f = 1 MHz)
SYMBOL
PARAMETER
CIN
Input Capacitance
COUT
Output Capacitance
TEST CONDITION
MAX
UNIT
VIN = GND
10
pF
VOUT = GND
10
pF
Note: This parameter is sampled periodically and is not 100% tested.
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TC51WKM616AXBN75
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta = −25°C to 85°C, VDD = 2.6 to 3.3 V, VDDQ = 1.7 to 2.2 V) (See Note 5 to 11)
SYMBOL
PARAMETER
MIN
MAX
UNIT
tRC
Read Cycle Time
75
10000
ns
tACC
Address Access Time

75
ns
tCO
Chip Enable ( CE1 ) Access Time

75
ns
tOE
Output Enable Access Time

25
ns
tBA
Data Byte Control Access Time

25
ns
tCOE
Chip Enable Low to Output Active
10

ns
tOEE
Output Enable Low to Output Active
0

ns
tBE
Data Byte Control Low to Output Active
0

ns
tOD
Chip Enable High to Output High-Z

20
ns
tODO
Output Enable High to Output High-Z

20
ns
tBD
Data Byte Control High to Output High-Z

20
ns
tOH
Output Data Hold Time
10

ns
tPM
Page Mode Time
75
10000
ns
tPC
Page Mode Cycle Time
30

ns
tAA
Page Mode Address Access Time

30
ns
tAOH
Page Mode Output Data Hold Time
10

ns
tWC
Write Cycle Time
75
10000
ns
tWP
Write Pulse Width
50

ns
tCW
Chip Enable to End of Write
75

ns
tBW
Data Byte Control to End of Write
60

ns
tAW
Address Valid to End of Write
60

ns
tAS
Address Set-up Time
0

ns
tWR
Write Recovery Time
0

ns
tODW
WE Low to Output High-Z

20
ns
tOEW
WE High to Output Active
0

ns
tDS
Data Set-up Time
30

ns
tDH
Data Hold Time
0

ns
tCS
CE2 Set-up Time
0

ns
tCH
CE2 Hold Time
300

µs
tDPD
CE2 Pulse Width
10

ms
tCHC
CE2 Hold from CE1
0

ns
tCHP
CE2 Hold from Power On
30

µs
AC TEST CONDITIONS
PARAMETER
CONDITION
Output load
30 pF + 1 TTL Gate
Input pulse level
VDDQ − 0.2 V, 0.2 V
Timing measurements
VDDQ × 0.5
Reference level
VDDQ× 0.5
tR, tF
5 ns
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TC51WKM616AXBN75
TIMING DIAGRAMS
READ CYCLE
tRC
Address
A0 to A21
tACC
tOH
tCO
CE1
Fix-H
CE2
tOE
tOD
OE
tODO
WE
tBA
UB , LB
tBE
DOUT
tBD
tOEE
Hi-Z
VALID DATA OUT
tCOE
I/O1 to I/O16
Hi-Z
INDETERMINATE
PAGE READ CYCLE (8 words access)
tPM
Address
A0 to A2
tRC
tPC
tPC
tPC
Address
A3 to A21
CE1
Fix-H
CE2
OE
WE
UB , LB
tOE
tBA
DOUT
I/O1 to I/O16
tOD
tBD
tAOH
tOEE
tAOH
tAOH
tOH
tBE
DOUT
Hi-Z
tCOE
tCO
tACC
DOUT
tAA
DOUT
tAA
DOUT
Hi-Z
tODO
tAA
* Maximum 8 words
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TC51WKM616AXBN75
WRITE CYCLE 1 ( WE CONTROLLED)
(See Note 8)
tWC
Address
A0 to A21
tAW
tAS
tWP
tWR
WE
tCW
tWR
tBW
tWR
CE1
tCH
CE2
UB , LB
tODW
DOUT
tOEW
(See Note 10)
Hi-Z
I/O1 to I/O16
tDS
DIN
(See Note 9)
(See Note 11)
tDH
VALID DATA IN
(See Note 9)
I/O1 to I/O16
WRITE CYCLE 2 ( CE CONTROLLED)
(See Note 8)
tWC
Address
A0 to A21
tAW
tAS
tWP
tWR
WE
tCW
tWR
CE1
tCH
CE2
tBW
tWR
UB , LB
tBE
DOUT
tODW
Hi-Z
I/O1 to I/O16
Hi-Z
tCOE
tDS
DIN
(See Note 9)
tDH
VALID DATA IN
I/O1 to I/O16
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TC51WKM616AXBN75
WRITE CYCLE 3 ( UB , LB CONTROLLED)
(See Note 8)
tWC
Address
A0 to A21
tAW
tAS
tWP
tWR
WE
tCW
CE1
tCH
CE2
tCW
tBW
UB , LB
tBE
DOUT
tODW
Hi-Z
I/O1 to I/O16
Hi-Z
tCOE
tDS
DIN
(See Note 9)
tDH
VALID DATA IN
I/O1 to I/O16
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TC51WKM616AXBN75
Deep Power-down Timing
CE1
tDPD
CE2
tCS
tCH
Power-on Timing
VDD
VDD min
CE1
tCHC
CE2
tCH
tCHP
Provisions of Address Skew
Read
In case, multiple invalid address cycles shorter than tRCmin sustain over 10µs in a active status, as least one
valid address cycle over tRCmin must be needed during 10µs.
over 10µs
CE1
WE
Address
tRCmin
Write
In case, multiple invalid address cycles shorter than tWCmin sustain over 10µs in a active status, as least one
valid address cycle over tWCmin with tWPmin must be needed during 10µs.
over 10µs
CE1
tWPmin
WE
Address
tWCmin
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TC51WKM616AXBN75
Notes:
(1)
Stresses greater than listed under “Absolute Maximum Ratings” may cause permanent damage to the
device.
(2)
All voltages are reference to GND.
(3)
IDDO depends on the cycle time.
(4)
IDDO depends on output loading. Specified values are defined with the output open condition.
(5)
AC measurements are assumed tR, tF = 5 ns.
(6)
Parameters tOD, tODO, tBD and tODW define the time at which the output goes the open condition and
are not output voltage reference levels.
(7)
Data cannot be retained at deep power-down stand-by mode.
(8)
If OE is high during the write cycle, the outputs will remain at high impedance.
(9)
During the output state of I/O signals, input signals of reverse polarity must not be applied.
(10)
If CE1 or LB / UB goes LOW coincident with or after WE goes LOW, the outputs will remain at high
impedance.
(11)
If CE1 or LB / UB goes HIGH coincident with or before WE goes HIGH, the outputs will remain at
high impedance.
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TC51WKM616AXBN75
PACKAGE DIMENSIONS
Unit:mm
0.2 S A
P-TFBGA48-0811-0.75BZ
11.0
8.0
0.2 S B
4
0.15
0.1 S
0.1 S
1.2 max
0.28 0.05
S
B
0.75
1
2
3
4
5
6
(3.75)
A
0.08
0.375
S AB
0.4 0.05
2.125
A B C D E F G H
0.75
2.875
0.375
(5.25)
Weight:
g (typ)
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TC51WKM616AXBN75
RESTRICTIONS ON PRODUCT USE
000707EBA
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
• The information contained herein is subject to change without notice.
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