TC74AC373P/F/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC373P,TC74AC373F,TC74AC373FT Octal D-Type Latch with 3-State Output TC74AC373P The TC74AC373 is an advanced high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. These 8-bit D-type latches are controlled by a latch enable input (LE) and a output enable input ( OE ). When the OE input is high, the eight outputs are in a high impedance state. All inputs are equipped with protection circuits against static discharge or transient excess voltage. TC74AC373F Features • High speed: tpd = 4.8 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = 8 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Symmetrical output impedance: |IOH| = IOL = 24 mA (min) • Capability of driving 50 Ω transmission lines. ∼ tpHL Balanced propagation delays: tpLH − • Wide operating voltage range: VCC (opr) = 2 to 5.5 V • Pin and function compatible with 74F373 TC74AC373FT Weight DIP20-P-300-2.54A SOP20-P-300-1.27A TSSOP20-P-0044-0.65A 1 : 1.30 g (typ.) : 0.22 g (typ.) : 0.08 g (typ.) 2007-10-01 TC74AC373P/F/FT Pin Assignment IEC Logic Symbol OE 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 LE (1) OE LE EN (11) C1 (3) D0 D1 D2 D3 D4 D5 (2) 1D (4) (5) (6) (7) D6 D7 (8) (9) (13) (12) (14) (15) (17) (18) (16) (19) Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 (top view) Truth Table Inputs Output OE LE D Q H X X Z L L X Qn L H L L L H H H X: Don’t care Z: High impedance Qn: Q outputs are latched at the time when the LE input is taken to a low logic level. System Diagram D0 3 D1 4 D LE OE 11 D2 7 D L Q D3 8 D D L Q D4 13 L Q D5 14 D L Q D6 17 D L Q D7 18 D L Q D L Q L Q 1 2 5 Q0 6 Q1 9 Q2 12 Q3 2 15 Q4 16 Q5 19 Q6 Q7 2007-10-01 TC74AC373P/F/FT Absolute Maximum Ratings (Note 1) Characteristics Symbol Rating Unit Supply voltage range VCC −0.5 to 7.0 V DC input voltage VIN −0.5 to VCC + 0.5 V VOUT −0.5 to VCC + 0.5 V DC output voltage Input diode current IIK ±20 mA Output diode current IOK ±50 mA DC output current IOUT ±50 mA DC VCC/ground current ICC ±200 mA Power dissipation PD 500 (DIP) (Note 2)/180 (SOP/TSSOP) mW Storage temperature Tstg −65 to 150 °C Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/Derating Concept and Methods) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C should be applied up to 300 mW. Operating Ranges (Note) Characteristics Symbol Rating Unit Supply voltage VCC 2.0 to 5.5 V Input voltage VIN 0 to VCC V VOUT 0 to VCC V Operating temperature Topr −40 to 85 °C Input rise and fall time dt/dV Output voltage Note: 0 to 100 (VCC = 3.3 ± 0.3 V) 0 to 20 (VCC = 5 ± 0.5 V) ns/V The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. 3 2007-10-01 TC74AC373P/F/FT Electrical Characteristics DC Characteristics Test Condition Characteristics High-level input voltage Low-level input voltage Min Typ. Max Min Max 2.0 1.50 ― ― 1.50 ― 3.0 2.10 ― ― 2.10 ― 5.5 3.85 ― ― 3.85 ― 2.0 ― ― 0.50 ― 0.50 3.0 ― ― 0.90 ― 0.90 5.5 ― ― 1.65 ― 1.65 2.0 1.9 2.0 ― 1.9 ― 3.0 2.9 3.0 ― 2.9 ― 4.5 4.4 4.5 ― 4.4 ― 3.0 2.58 ― ― 2.48 ― 4.5 3.94 ― ― 3.80 ― 5.5 ― ― ― 3.85 ― 2.0 ― 0.0 0.1 ― 0.1 IOL = 50 μA 3.0 ― 0.0 0.1 ― 0.1 VIN = VIH or IOL = 12 mA VIL 4.5 ― 0.0 0.1 ― 0.1 3.0 ― ― 0.36 ― 0.44 4.5 ― ― 0.36 ― 0.44 5.5 ― ― ― ― 1.65 5.5 ― ― ±0.5 ― ±5.0 μA VIH ― VIL VOH ― VIN = VIH or IOH = −4 mA VIL IOH = −24 mA IOH = −75 mA Low-level output voltage VOL Unit VCC (V) IOH = −50 μA High-level output voltage Ta = −40 to 85°C Ta = 25°C Symbol (Note) IOL = 24 mA IOL = 75 mA (Note) VIN = VIH or VIL V V V V 3-state output off-state current IOZ Input leakage current IIN VIN = VCC or GND 5.5 ― ― ±0.1 ― ±1.0 μA Quiescent supply current ICC VIN = VCC or GND 5.5 ― ― 8.0 ― 80.0 μA Ta = 25°C Ta = −40 to 85°C Unit Note: VOUT = VCC or GND This spec indicates the capability of driving 50 Ω transmission lines. One output should be tested at a time for a 10 ms maximum duration. Timing Requirements (input: tr = tf = 3 ns) Characteristics Minimum pulse width Test Condition Symbol tw (H) ― Minimum set-up time ts ― Minimum hold time th ― (LE) 4 VCC (V) Limit Limit 3.3 ± 0.3 7.0 7.0 5.0 ± 0.5 5.0 5.0 3.3 ± 0.3 6.0 6.0 5.0 ± 0.5 3.5 3.5 3.3 ± 0.3 1.0 1.0 5.0 ± 0.5 1.0 1.0 ns ns ns 2007-10-01 TC74AC373P/F/FT AC Characteristics (CL = 50 pF, RL = 500 Ω, input: tr = tf = 3 ns) Characteristics Symbol Propagation delay time tpLH (LE-Q) tpHL Propagation delay time tpLH (D-Q) tpHL Output enable time Output disable time Input capacitance Output capacitance Power dissipation capacitance Note: tpZL tpZH tpLZ tpHZ Test Condition ― ― ― ― Ta = −40 to 85°C Ta = 25°C VCC (V) Min Typ. Max Min Max 3.3 ± 0.3 ― 7.7 13.2 1.0 15.0 5.0 ± 0.5 ― 6.1 8.7 1.0 10.0 3.3 ± 0.3 ― 7.6 12.9 1.0 14.7 5.0 ± 0.5 ― 5.8 8.3 1.0 9.5 3.3 ± 0.3 ― 7.6 12.9 1.0 14.7 5.0 ± 0.5 ― 6.1 8.7 1.0 10.0 3.3 ± 0.3 ― 7.0 11.0 1.0 12.5 5.0 ± 0.5 ― 5.4 7.5 1.0 8.5 Unit ns ns ns ns CIN ― ― 5 10 ― 10 pF COUT ― ― 10 ― ― ― pF ― 38 ― ― ― pF CPD (Note) CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD·VCC·fIN·ICC/8 (per latch) And the total CPD when n pcs. of latch operate can be gained by the following equation: CPD (total) = 26 + 12·n 5 2007-10-01 TC74AC373P/F/FT Package Dimensions Weight: 1.30 g (typ.) 6 2007-10-01 TC74AC373P/F/FT Package Dimensions Weight: 0.22 g (typ.) 7 2007-10-01 TC74AC373P/F/FT Package Dimensions Weight: 0.08 g (typ.) 8 2007-10-01 TC74AC373P/F/FT RESTRICTIONS ON PRODUCT USE 20070701-EN GENERAL • The information contained herein is subject to change without notice. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. 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Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. 9 2007-10-01