TC55V8512JI/FTI-12,-15 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 524,288-WORD BY 8-BIT CMOS STATIC RAM DESCRIPTION The TC55V8512JI/FTI is a 4,194,304-bit high-speed static random access memory (SRAM) organized as 524,288 words by 8 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high speed, it operates from a single 3.3 V power supply. Chip enable ( CE ) can be used to place the device in a low-power mode, and output enable ( OE ) provides fast memory access. This device is well suited to cache memory applications where high-speed access and high-speed storage are required. All inputs and outputs are directly LVTTL compatible. The TC55V8512JI/FTI is available in plastic 36-pin SOJ and 44-pin TSOP with 400mil width for high density surface assembly. The TC55V8512JI/FTI guarantees −40° to 85°C operating temperature so it is suitable for use in wide operating temperature system. FEATURES • • Fast access time (the following are maximum values) TC55V8512JI/FTI-12:12 ns TC55V8512JI/FTI-15:15 ns Low-power dissipation (the following are maximum values) Cycle Time 12 15 20 25 ns Operation (max) 180 150 140 120 mA • • • • • Single power supply voltage of 3.3 V ± 0.3 V Fully static operation All inputs and outputs are LVTTL compatible Output buffer control using OE Package: SOJ36-P-400-1.27 (JI) (Weight: 1.35 g typ) TSOP II44-P-400-0.80 (FTI) (Weight: 0.45 g typ) Standby:10 mA (both devices) PIN ASSIGNMENT (TOP VIEW) PIN NAMES 44 PIN TSOP 36 PIN SOJ A0 to A18 A17 A3 A2 A1 A0 CE I/O1 I/O2 VDD GND I/O3 I/O4 WE A16 A15 A14 A13 A18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 (TC55V8512JI) NC A4 A5 A6 A7 OE I/O8 I/O7 GND VDD I/O6 I/O5 A8 A9 A10 A11 A12 NU NC NC A17 A3 A2 A1 A0 CE I/O1 I/O2 VDD GND I/O3 I/O4 WE A16 A15 A14 A13 A18 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A4 A5 A6 A7 OE I/O8 I/O7 GND VDD I/O6 I/O5 A8 A9 A10 A11 A12 NU NC NC I/O1 to I/O8 Address Inputs Data Inputs/Outputs CE Chip Enable Input WE Write Enable Input OE Output Enable Input VDD Power (+3.3 V) GND Ground NC No Connection NU Not Usable (Input) (TC55V8512FTI) 2001-12-19 1/10 TC55V8512JI/FTI-12,-15 ROW ADDRESS BUFFER A0 A1 A4 A8 A9 A12 A14 A15 A16 A17 ROW DECODER BLOCK DIAGRAM VDD GND MEMORY CELL ARRAY 512 × 1,024 × 8 (4,194,304) DATA INPUT BUFFER DATA OUTPUT BUFFER CE I/O1 I/O2 I/O3 I/O4 I/O5 I/O5 I/O7 I/O8 SENSE AMP COLUMN DECODER CE COLUMN ADDRESS BUFFER CLOCK GENERATOR A2 A3 A5 A6 A7 A10 A11A13 A18 WE OE CE CE MAXIMUM RATINGS SYMBOL RATING VALUE UNIT VDD Power Supply Voltage −0.5 to 4.6 V VIN Input Terminal Voltage −0.5* to 4.6 V VI/O Input/Output Terminal Voltage −0.5* to VDD + 0.5** V PD Power Dissipation 1.4 W Tsolder Soldering Temperature (10s) 260 °C Tstg Storage Temperature −65 to 150 °C Topr Operating Temperature −40 to 100 °C *: −1.5 V with a pulse width of 20%･tRC min (4 ns max) **: VDD + 1.5 V with a pulse width of 20%･tRC min (4 ns max) DC RECOMMENDED OPERATING CONDITIONS (Ta = −40° to 85°C) SYMBOL PARAMETER MIN TYP MAX UNIT VDD Power Supply Voltage 3.0 3.3 3.6 V VIH Input High Voltage 2.0 VDD + 0.3** V VIL Input Low Voltage −0.3* 0.8 V *: −1.0 V with a pulse width of 20%･tRC min (4 ns max) **: VDD + 1.0 V with a pulse width of 20%･tRC min (4 ns max) 2001-12-19 2/10 TC55V8512JI/FTI-12,-15 DC CHARACTERISTICS (Ta = −40° to 85°C, VDD = 3.3 V ± 0.3 V) SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT −1 1 µA CE = VIH or WE = VIL or OE = VIH, VOUT = 0 to VDD −1 1 µA VIN = 0 to 0.8 V −1 20 VIN = 0 to 0.2 V −1 1 IOH = −2 mA 2.4 VDD − 0.2 IOL = 2 mA 0.4 IOL = 100 µA 0.2 tcycle = 12 ns 180 tcycle = 15 ns 150 tcycle = 20 ns 140 tcycle = 25 ns 120 CE = VIH, Other Input = VIH or VIL 55 CE = VDD − 0.2 V, Other Input = VDD − 0.2 V or 0.2 V 10 IIL Input Leakage Current VIN = 0 to VDD (Except NU pin) ILO Output Leakage Current II (NU) Input Current (NU pin) VOH Output High Voltage VOL Output Low Voltage IOH = −100 µA CE = VIL, IOUT = 0 mA, IDDO Operating Current OE = VIH, Other Input = VIH/VIL IDDS1 Standby Current IDDS2 µA V mA mA CAPACITANCE (Ta = 25°C, f = 1 .0 MHz) SYMBOL PARAMETER TEST CONDITION MAX UNIT CIN Input Capacitance VIN = GND 6 pF CI/O Input/Output Capacitance VI/O = GND 8 pF Note: This parameter is periodically sampled and is not 100% tested. OPERATING MODE MODE CE OE WE I/O1 to I/O8 POWER Read L L H Output IDDO Write L * L Input IDDO Outputs Disable L H H High Impedance IDDO Standby H * * High Impedance IDDS * : Don’t care Note: The NU pin must be left unconnected or tied to GND or a voltage level of less than 0.8 V. You must not apply a voltage of more than 0.8 V to the NU. 2001-12-19 3/10 TC55V8512JI/FTI-12,-15 AC CHARACTERISTICS (Ta = −40° to 85°C (See Note 1) , VDD = 3.3 V ± 0.3 V) READ CYCLE TC55V8512JI/FTI SYMBOL PARAMETER -12 UNIT -15 MIN MAX MIN MAX tRC Read Cycle Time 12 15 tACC Address Access Time 12 15 tCO Chip Enable Access Time 12 15 tOE Output Enable Access Time 6 8 tOH Output Data Hold Time from Address Change 3 4 tCOE Output Enable Time from Chip Enable 3 4 tOEE Output Enable Time from Output Enable 1 1 tCOD Output Disable Time from Chip Enable 7 8 tODO Output Disable Time from Output Enable 7 8 ns WRITE CYCLE TC55V8512JI/FTI SYMBOL PARAMETER -12 UNIT -15 MIN MAX MIN MAX tWC Write Cycle Time 12 15 tWP Write Pulse Width 8 9 tCW Chip Enable to End of Write 10 12 tAW Address Valid to End of Write 10 12 tAS Address Setup Time 0 0 tWR Write Recovery Time 0 0 tDS Data Setup Time 7 8 tDH Data Hold Time 0 0 tOEW Output Enable Time from Write Enable 1 1 tODW Output Disable Time from Write Enable 7 8 AC TEST CONDITIONS ns Fig.1 3.3 V PARAMETER Input Pulse Level TEST CONDITION 3.0 V/ 0.0 V Input Pulse Rise and Fall Time 2 ns Input Timing Measurement Reference Level 1.5 V Output Timing Measurement Reference Level 1.5 V Output Load Fig.1 1200 Ω I/O pin Z0 = 50 Ω CL = 30 pF I/O pin RL = 50 Ω VL = 1.5 V CL = 5 pF 870 Ω (For tCOE, tOEE, tCOD, tODO, tOEW and tODW ) 2001-12-19 4/10 TC55V8512JI/FTI-12,-15 TIMING DIAGRAMS READ CYCLE (See Note 2) tRC Address tACC tOH tCO CE tOE tCOD (See Note 6) OE tOEE tCOE DOUT (See Note 6) tODO (See Note 6) (See Note 6) VALID DATA OUT Hi-Z INDETERMINATE WRITE CYCLE 1 ( WE CONTROLLED) Hi-Z INDETERMINATE (See Note 5) tWC tAW Address tAS tWP tWR WE tCW CE tODW DOUT (See Note 3) INDETERMINATE DIN (See Note 6) tOEW Hi-Z tDS (See Note 6) (See Note 4) tDH INDETERMINATE VALID DATA IN 2001-12-19 5/10 TC55V8512JI/FTI-12,-15 WRITE CYCLE 2 (CE CONTROLLED) (See Note 5) tWC tAW Address tAS tWP tWR WE tCW CE tODW (See Note 6) tCOE (See Note 6) DOUT Hi-Z Hi-Z INDETERMINATE DIN tDS tDH VALID DATA IN 2001-12-19 6/10 TC55V8512JI/FTI-12,-15 Note: (1) Operating temperature (Ta) is guaranteed for transverse air flow exceeding 400 linear feet per minute. (2) WE remains HIGH for the Read Cycle. (3) If CE goes LOW coincident with or after WE goes LOW, the outputs will remain at high impedance. (4) If CE goes HIGH coincident with or before WE goes HIGH, the outputs will remain at high impedance. (5) If OE is HIGH during the write cycle, the outputs will remain at high impedance. (6) The parameters specified below are measured using the load shown in Fig.1. (A) tCOE, tOEE, tOEW･････････････････ Output Enable Time (B) tCOD, tODO, tODW ････････････････ Output Disable Time CE , OE WE (A) (B) 0.2 V DOUT Hi-Z 0.2 V 0.2 V INDETERMINATE VALID DATA OUT Hi-Z INDETERMINATE 0.2 V 2001-12-19 7/10 TC55V8512JI/FTI-12,-15 PACKAGE DIMENSIONS Weight: 1.35 g (typ) 2001-12-19 8/10 TC55V8512JI/FTI-12,-15 PACKAGE DIMENSIONS Weight: 0.45 g (typ) 2001-12-19 9/10 TC55V8512JI/FTI-12,-15 RESTRICTIONS ON PRODUCT USE 000707EBA • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice. 2001-12-19 10/10