MOTOROLA Order this document by MCM6246/D SEMICONDUCTOR TECHNICAL DATA MCM6246 512K x 8 Bit Static Random Access Memory The MCM6246 is a 4,194,304 bit static random access memory organized as 524,288 words of 8 bits. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability. The MCM6246 is equipped with chip enable (E) and output enable (G) pins, allowing for greater system flexibility and eliminating bus contention problems. Either input, when high, will force the outputs into high impedance. The MCM6246 is available in a 400 mil, 36–lead surface–mount SOJ package. • • • • • • Single 5 V ± 10% Power Supply Fast Access Time: 17/20/25/35 ns Equal Address and Chip Enable Access Time All Inputs and Outputs are TTL Compatible Three–State Outputs Power Operation: 205/200/185/170 mA Maximum, Active AC WJ PACKAGE 400 MIL SOJ CASE 893–01 PIN ASSIGNMENT A 1 36 NC A 2 35 A A 3 34 A A 4 33 A A 5 32 A E 6 31 G DQ 7 30 DQ A DQ 8 29 DQ A VCC 9 28 VSS A VSS 10 27 VCC DQ 11 26 DQ DQ 12 25 DQ W 13 24 A A 14 23 A BLOCK DIAGRAM A A A MEMORY MATRIX 1024 ROWS x 4096 COLUMNS ROW DECODER A A 15 22 A A A 16 21 A A A 17 20 A A A 18 19 NC COLUMN I/O DQ INPUT DATA CONTROL PIN NAMES COLUMN DECODER DQ A A A A A A A A A DQ E W G A . . . . . . . . . . . . . . . . . . . Address Inputs W . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . Output Enable E . . . . . . . . . . . . . . . . . . . . . . Chip Enable DQ . . . . . . . . . . . . . . . Data Input/Output NC . . . . . . . . . . . . . . . . . No Connection VCC . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . Ground DQ REV 5 6/9/97 Motorola, Inc. 1997 MOTOROLA FAST SRAM MCM6246 1 TRUTH TABLE (X = Don’t Care) E G W Mode I/O Pin Cycle Current H X X Not Selected High–Z — ISB1, ISB2 L H H Output Disabled High–Z — ICCA L L H Read Dout Read ICCA L X L Write High–Z Write ICCA ABSOLUTE MAXIMUM RATINGS (See Note) Symbol Value Unit VCC – 0.5 to + 7.0 V Vin, Vout – 0.5 to VCC + 0.5 V Output Current (per I/O) Iout ± 20 mA Power Dissipation PD 1.0 W Tbias – 10 to + 85 °C TA 0 to + 70 °C Rating Power Supply Voltage Relative to VSS Voltage Relative to VSS for Any Pin Except VCC Temperature Under Bias Ambient Temperature Storage Temperature — Plastic Tstg – 55 to + 150 °C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high impedance circuits. This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained. DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Supply Voltage (Operating Voltage Range) VCC 4.5 5.0 5.5 V Input High Voltage VIH 2.2 — VCC + 0.3** V Input Low Voltage VIL – 0.5* — 0.8 V * VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns). ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 2.0 ns). DC CHARACTERISTICS Parameter Symbol Min Max Unit Input Leakage Current (All Inputs, Vin = 0 to VCC) Ilkg(I) — ± 1.0 µA Output Leakage Current (E = VIH, Vout = 0 to VCC) Ilkg(O) — ± 1.0 µA Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V Symbol Min Typ Max Unit POWER SUPPLY CURRENTS Parameter AC Active Supply Current (Iout = 0 mA, VCC = max) MCM6246–17: tAVAV = 17 ns MCM6246–20: tAVAV = 20 ns MCM6246–25: tAVAV = 25 ns MCM6246–35: tAVAV = 35 ns ICC — — — — — 185 170 155 205 200 185 170 mA AC Standby Current (VCC = max, E = VIH, No other restrictions on other inputs) MCM6246–17: tAVAV = 17 ns MCM6246–20: tAVAV = 20 ns MCM6246–25: tAVAV = 25 ns MCM6246–35: tAVAV = 35 ns ISB1 — — — — 55 55 45 35 60 60 50 40 mA ISB2 — 10 15 mA CMOS Standby Current (E ≥ VCC – 0.2 V, Vin ≤ VSS + 0.2 V or ≥ VCC – 0.2 V) (VCC = max, f = 0 MHz) MCM6246 2 MOTOROLA FAST SRAM CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested) Symbol Typ Max Unit All Inputs Except Clocks and DQs E, G, W Cin Cck 4 5 6 8 pF DQ CI/O 5 8 pF Parameter Input Capacitance Input/Output Capacitance AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted) Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 READ CYCLE TIMING (See Note 1) MCM6246–17 MCM6246–20 MCM6246–25 MCM6246–35 Symbol Min Max Min Max Min Max Min Max Unit Notes Read Cycle Time tAVAV 17 — 20 — 25 — 35 — ns 2, 3 Address Access Time tAVQV — 17 — 20 — 25 — 35 ns Enable Access Time tELQV — 17 — 20 — 25 — 35 ns Output Enable Access Time tGLQV — 6 — 6 — 8 — 10 ns Output Hold from Address Change tAXQX 5 — 5 — 5 — 5 — ns Enable Low to Output Active tELQX 5 — 5 — 5 — 5 — ns 5, 6, 7 Output Enable Low to Output Active tGLQX 0 — 0 — 0 — 0 — ns 5, 6, 7 Enable High to Output High–Z tEHQZ — 8 — 8 — 10 — 12 ns 5, 6, 7 Output Enable High to Output High–Z tGHQZ — 8 — 8 — 10 — 12 ns 5, 6, 7 Power Up Time tELICCH 0 — 0 — 0 — 0 — ns Power Down Time tEHICCL — 17 — 20 — 25 — 35 ns Parameter 4 NOTES: 1. W is high for read cycle. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All read cycle timings are referenced from the last valid address to the first transitioning address. 4. Addresses valid prior to or coincident with E going low/E going high. 5. At any given voltage and temperature, tEHQZ max tELQX min, and tGHQZ max tGLQX min, both for a given device and from device to device. 6. Transition is measured ± 500 mV from steady–state voltage. 7. This parameter is sampled and not 100% tested. 8. Device is continuously selected (E ≤ VIL, G ≤ VIL). t t TIMING LIMITS RL = 50 Ω OUTPUT Z0 = 50 Ω VL = 1.5 V The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. Figure 1. AC Test Load MOTOROLA FAST SRAM MCM6246 3 READ CYCLE 1 (See Note 8) tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID DATA VALID tAVQV READ CYCLE 2 (See Note) tAVAV A (ADDRESS) tELQV E (CHIP ENABLE) tELQX tEHQZ G (OUTPUT ENABLE) Q (DATA OUT) SUPPLY CURRENT ICC HIGH–Z tGLQX tGLQV tGHQZ DATA VALID tAVQV tELICCH tEHICCL ISB NOTE: Addresses valid prior to or coincident with E going low/ E going high. MCM6246 4 MOTOROLA FAST SRAM WRITE CYCLE 1 (W Controlled, See Notes 1, 2, and 3) Parameter Write Cycle Time MCM6246–17 MCM6246–20 MCM6246–25 MCM6246–35 Symbol Min Max Min Max Min Max Min Max Unit Notes tAVAV 17 — 20 — 25 — 35 — ns 4 Address Setup Time tAVWL 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVWH 14 — 14 — 17 — 20 — ns Write Pulse Width tWLWH, tWLEH 13 — 13 — 17 — 20 — ns Data Valid to End of Write tDVWH 10 — 10 — 10 — 15 — ns Data Hold Time tWHDX 0 — 0 — 0 — 0 — ns Write Low to Data High–Z tWLQZ 0 9 0 9 0 10 0 15 ns 5,6,7 Write High to Output Active tWHQX 5 — 5 — 5 — 5 — ns 5,6,7 Write Recovery Time tWHAX 0 — 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state. 4. All write cycle timings are referenced from the last valid address to the first transitioning address. 5. Transition is measured ± 500 mV from steady–state voltage. 6. This parameter is sampled and not 100% tested. 7. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device. WRITE CYCLE 1 (W Controlled, See Notes 1, 2, and 3) tAVAV A (ADDRESS) tAVWH tWHAX E (CHIP ENABLE) tWLWH tWLEH W (WRITE ENABLE) tAVWL tDVWH DATA VALID D (DATA IN) tWLQZ Q (DATA OUT) MOTOROLA FAST SRAM tWHDX HIGH–Z tWHQX HIGH–Z MCM6246 5 WRITE CYCLE 2 (E Controlled, See Notes 1, 2, and 3) Parameter Write Cycle Time MCM6246–17 MCM6246–20 MCM6246–25 MCM6246–35 Symbol Min Max Min Max Min Max Min Max Unit Notes tAVAV 17 — 20 — 25 — 35 — ns 4 Address Setup Time tAVEL 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVEH 14 — 14 — 17 — 20 — ns Enable Pulse Width tELEH, tELWH 14 — 14 — 17 — 20 — ns Write Pulse Width tWLEH 14 — 14 — 17 — 20 — ns Data Valid to End of Write tDVEH 9 — 10 — 10 — 15 — ns Data Hold Time tEHDX 0 — 0 — 0 — 0 — ns Write Recovery Time tEHAX 0 — 0 — 0 — 0 — ns 5,6 NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state. 4. All write cycle timing is referenced from the last valid address to the first transitioning address. 5. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition. 6. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition. WRITE CYCLE 2 (E Controlled, See Notes 1, 2, and 3) tAVAV A (ADDRESS) tAVEH tELEH E (CHIP ENABLE) tAVEL tELWH tEHAX tWLEH W (WRITE ENABLE) tDVEH DATA VALID D (DATA IN) tEHDX HIGH–Z Q (DATA OUT) ORDERING INFORMATION (Order by Full Part Number) MCM 6246 XX XX XX Motorola Memory Prefix Shipping Method (R2 = Tape and Reel, Blank = Rails) Part Number Speed (17 = 17 ns, 20 = 20 ns, 25 = 25 ns, 35 = 35 ns) Package (WJ = 400 mil SOJ) Full Part Numbers — MCM6246WJ17 MCM6246WJ20 MCM6246WJ25 MCM6246WJ35 MCM6246 6 MCM6246WJ17R2 MCM6246WJ20R2 MCM6246WJ25R2 MCM6246WJ35R2 MOTOROLA FAST SRAM PACKAGE DIMENSIONS 400 MIL SOJ CASE 893–01 F 36 PL N 36 PL 36 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TO BE DETERMINED AT PLANE -T-. 4. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.006 (0.15) PER SIDE. 5. DIMENSION A AND B INCLUDE MOLD MISMATCH AND ARE DETERMINED AT THE PARTING LINE. 19 D 36 PL 0.007 (0.17) M 1 18 T Y X S S NOTE 3 DETAIL A 0.007 (0.17) A -X- M T Y S X S P B -YE C 0.004 (0.010) K DETAIL A DIM A B C D E F G K L N P R S L 2 PL -T- SEATING PLANE MOTOROLA FAST SRAM S RADIUS 36 PL MILLIMETERS MIN MAX 23.37 23.62 10.04 10.28 3.26 3.75 0.41 0.50 2.24 2.48 0.67 0.81 1.27 BASIC 0.89 1.14 0.64 BASIC 0.77 1.14 11.05 11.30 9.28 9.52 0.77 1.01 R 0.007 (0.17) G 34 PL INCHES MIN MAX 0.920 0.930 0.395 0.405 0.128 0.148 0.016 0.020 0.088 0.098 0.026 0.032 0.050 BASIC 0.035 0.045 0.025 BASIC 0.030 0.045 0.435 0.445 0.365 0.375 0.030 0.040 M T Y S X S NOTE 3 MCM6246 7 Motorola reserves the right to make changes without further notice to any products herein. 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