TOSHIBA TC58FVM6B2AFT65

TC58FVM6(T/B)2A(FT/XB)65
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
64MBIT (8M × 8 BITS/4M × 16 BITS) CMOS FLASH MEMORY
DESCRIPTION
The TC58FVM6T2A/B2A is a 67108864-bit, 3.0-V read-only electrically erasable and programmable flash
memory organized as 8388608 words × 8 bits or as 4194304 words × 16 bits. The TC58FVM6T2A/B2A features
commands for Read, Program and Erase operations to allow easy interfacing with microprocessors. The commands
are based on the JEDEC standard. The Program and Erase operations are automatically executed in the chip. The
TC58FVM6T2A/B2A also features a Simultaneous Read/Write operation so that data can be read during a Write or
Erase operation.
FEATURES
•
•
•
•
Power supply voltage
VDD = 2.3 V~3.6 V
Operating temperature
Ta = −40°C~85°C
Organization
8M × 8 bits/4M × 16 bits
Functions
Simultaneous Read/Write
Page Read
Auto Program, Auto Page Program
Auto Block Erase, Auto Chip Erase
Fast Program Mode/Acceleration Mode
Program Suspend/Resume
Erase Suspend/Resume
data polling/Toggle bit
block protection, boot block protection
Automatic Sleep, support for hidden ROM area
common flash memory interface (CFI)
Byte/Word Modes
•
•
•
•
•
•
•
Block erase architecture
8 × 8 Kbytes/127 × 64 Kbytes
Boot block architecture
TC58FVM6T2A: top boot block
TC58FVM6B2A: bottom boot block
Mode control
Compatible with JEDEC standard commands
Erase/Program cycles
105 cycles typ.
Access Time (Random/Page)
VDD
CL = 30 pF
CL = 100 pF
2.7~3.6 V
65 ns/25 ns
70 ns/30 ns
2.3~3.6 V
70 ns/30 ns
75 ns/35 ns
Power consumption
10 µA (Standby)
15 mA (Program/Erase operation)
55 mA (Random Read operation)
11 mA (Address Increment Read operation)
5 mA (Page Read operation)
Package
TC58FVM6**AFT:
TSOPI48-P-1220-0.50 (weight: 0.51 g)
TC58FVM6**AXB:
P-TFBGA56-0710-0.80AZ (weight: 0.125 g)
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Ordering information
TC58
F V
M6
T2
A FT 65
Speed version
65 = 65 ns
Package
FT = TSOP
XB = FBGA
Design rule
A = 0.16 µm
Function/Boot block architecture/Bank ratio
T2 = Page mode/Top boot block/1:3:3:1
B2 = Page mode/Bottom boot block/1:3:3:1
Capacity
M6 = 64Mbits
Supply Voltage
V = 3 V system
Device type
F = NOR Flash memory
Toshiba CMOS E2PROM
Ordering type
Boot block
TC58FVM6T2AFT65
Top
TC58FVM6B2AFT65
Bottom
TC58FVM6T2AXB65
Top
TC58FVM6B2AXB65
Bottom
Bank ratio
Package
TSOPI48-P-1220-0.50
1:3:3:1
P-TFBGA56-0710-0.80AZ
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PIN ASSIGNMENT (TOP VIEW)…TC58FVM6**AFT
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
RESET
A21
WP/ACC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PIN NAMES
A16
BYTE
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE
A0
A-1, A0~A21
Address Input
DQ0~DQ15
Data Input/Output
CE
Chip Enable Input
Output Enable Input
OE
BYTE
Word/Byte Select Input
WE
Write Enable Input
RY/BY
Ready/Busy Output
RESET
Hardware Reset Input
WP/ACC
Write Protect /
Program Acceleration Input
VDD
Power Supply
VSS
Ground
PIN ASSIGNMENT (TOP VIEW)…TC58FVM6**AXB
1
2
3
4
5
6
7
8
A
NC
NC
B
NC
NC
C
A3
A7
RY/BY
WE
A9
A13
D
A4
A17
WP/ACC
RESET
A8
A12
E
A2
A6
A18
A21
A10
A14
F
A1
A5
A20
A19
A11
A15
G
A0
DQ0
DQ2
DQ5
DQ7
A16
H
CΕ
DQ8
DQ10
DQ12
DQ14
BYTE
J
OE
DQ9
DQ11
VDD
DQ13
DQ15
K
VSS
DQ1
DQ3
DQ4
DQ6
VSS
L
NC
NC
M
NC
NC
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BLOCK DIAGRAM
VDD
VSS
RY/BY
DQ0
RY/BY Buffer
DQ15
I/O Buffer
WP/ACC
WE
Control Circuit
BYTE
Data Latch
RESET
CE
Command Register
OE
Memory Cell
Array
Memory Cell
Array
Memory Cell
Array
Memory Cell
Array
Bank0
Bank1
Bank2
Bank3
Address Latch
A21
Address Buffer
A0
A-1
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MODE SELECTION
BYTE MODE WORD MODE
MODE
(1)
CE
OE
WE
A9
A6
A1
A0
RESET
WP/ACC
Read/Page Read
L
L
H
A9
A6
A1
A0
H
*
DOUT
DOUT
ID Read (Manufacturer Code)
L
L
H
VID
L
L
L
H
*
Code
Code
ID Read (Device Code)
L
L
H
VID
L
L
H
H
*
Code
Code
Standby
H
*
*
*
*
*
*
H
*
High-Z
High-Z
Output Disable
*
H
H
*
*
*
*
*
*
High-Z
High-Z
A9
A6
A1
A0
H
*
DIN
DIN
VID
L
H
L
H
*
*
*
(2)
DQ0~DQ7
DQ0~DQ15
Write
L
H
Block Protect 1
L
VID
Block Protect 2
L
H
H
*
L
H
L
VID
*
*
*
Verify Block Protect
L
L
H
VID
L
H
L
H
*
Code
Code
Temporary Block Unprotect
*
*
*
*
*
*
*
VID
*
*
*
Hardware Reset/Standby
*
*
*
*
*
*
*
L
*
High-Z
High-Z
Boot Block Protect
*
*
*
*
*
*
*
*
L
*
*
(2)
Notes: * = VIH or VIL, L = VIL, H = VIH
(1) DQ8~DQ14 are High-Z and DQ15/A-1 is Address Input in Byte Mode.
Addresses are A21~A0 in Word Mode ( BYTE = VIH), A21~A-1 in Byte Mode ( BYTE = VIL).
(2) Pulse input
ID CODE TABLE
CODE TYPE
A6
A1
A0
*
L
L
L
0098h
TC58FVM6T2A
*
L
L
H
0057h
TC58FVM6B2A
*
L
L
H
0058h
L
H
L
Data
Manufacturer Code
Device Code
Verify Block Protect
(1)
A21~A12
BA
(2)
CODE (HEX)
(3)
Notes: * = VIH or VIL, L = VIL, H = VIH
(1) DQ8~DQ14 are High-Z and DQ15/A-1 is Address Input in Byte Mode.
(2) BA: Block Address
(3) 0001h - Protected Block
0000h - Unprotected Block
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COMMAND SEQUENCES
BUS
FIRST BUS
SECOND BUS
THIRD BUS
FOURTH BUS
FIFTH BUS
SIXTH BUS
COMMAND
WRITE
WRITE CYCLE
WRITE CYCLE
WRITE CYCLE
WRITE CYCLE
WRITE CYCLE
WRITE CYCLE
SEQUENCE
CYCLES
Addr.
Addr.
Addr.
Data
XXXh
F0h
REQ’D
Read/Reset
Read/Reset
1
Word
Byte
555h
3
AAAh
Word
ID Read
Auto-Program
555h
3
555h
555h
Word
555h
2AAh
4
AAAh
Word
11
555h
Byte
19
AAAh
Program Suspend
1
BK
Program Resume
1
BK
Auto Chip
Word
Erase
Byte
Auto Block
Word
Erase
Byte
Block Erase Suspend
(3)
(3)
555h
6
AAAh
555h
6
AAAh
1
BK
(3)
(3)
Block Erase Resume
1
BK
Block Protect 2
4
XXXh
Word
AAh
AAh
555h
2AAh
555h
AAh
AAh
2AAh
555h
2AAh
555h
BPA
(9)
Word
555h
2AAh
Set
Byte
Fast Program Reset
Hidden ROM
Word
Mode Entry
Byte
Hidden ROM
Word
Program
Byte
Hidden ROM
Word
Erase
Byte
Hidden ROM
Word
Mode Exit
Byte
Query
Word
Command
Byte
2
XXXh
555h
3
AAAh
555h
4
AAAh
555h
6
AAAh
555h
4
2
AAAh
BK
(3)
BK
(3)
+ 55h
+AAh
55h
55h
55h
55h
60h
+
555h
AAAh
555h
AAAh
555h
AAAh
555h
AAAh
AAh
A0h
90h
AAh
AAh
AAh
AAh
98h
555h
PA
(6)
XXXh
2AAh
555h
2AAh
555h
2AAh
555h
2AAh
555h
CA
(11)
XXXh
BK
55h
Fast Program
XXXh
(3)
90h
IA
A0h
PA
E6h
PA
(1)
RD
Data
(2)
+
555h
BK
RA
Data
(4)
ID
(5)
AAAh
2AAh
555h
2
(3)
F0h
Data
(6)
(6)
PD
PD
(7)
(7)
PA
(6)
PD
(7)
PA
(6)
PD
(7)
80h
80h
555h
AAAh
555h
AAAh
AAh
AAh
2AAh
555h
2AAh
555h
55h
555h
AAAh
55h
BA
55h
BA
(8)
10h
30h
30h
60h
AAAh
Fast Program
BK
Addr.
B0h
Byte
AAAh
555h
AAAh
Data
30h
AAh
3
Addr.
B0h
555h
3
55h
55h
AAAh
Byte
Data
2AAh
Byte
PageProgram
Protect
2AAh
AAh
Auto
Verify Block
AAh
Addr.
(3)
(3)
BPA
90h
BPA
(9)
(10)
BPD
+
555h
BK
40h
+
(9)
(10)
BPD
AAAh
55h
PD
555h
AAAh
20h
(7)
(13)
F0h
55h
55h
55h
55h
CD
555h
AAAh
555h
AAAh
555h
AAAh
555h
AAAh
88h
A0h
80h
90h
PA
(6)
555h
AAAh
XXXh
PD
(7)
AAh
2AAh
555h
(8)
30h
00h
(12)
Notes: The system should generate the following address patterns:
Word Mode: 555H or 2AAH on address pins A10~A0 DQ8~DQ15 are ignored in Word Mode.
Byte Mode: AAAH or 555H on address pins A10~A-1
(7) PD: Program Data
(1) RA: Read Address
(8) BA: Block Address = A21~A12
(2) RD: Read Data
(9) BPA: Block Address and ID Read Address (A6, A1, A0)
(3) BK: Bank Address = A21~A15
Block Address = A21~A12
(4) IA: Bank Address and ID Read Address (A6, A1, A0)
ID Read Address = (0, 1, 0)
Bank Address = A21~A15
(10) BPD: Verify Data
Manufacturer Code = (0, 0, 0)
(11) CA: CFI Address
Device Code = (0, 0, 1)
(12) CD: CFI Data
(5) ID: ID Data
(13) F0H: 00H is valid too
(6) PA: Program Address
(Input continuous 8 address from (A0, A1, A2) = (0, 0, 0) to (A0, A1, A2) = (1, 1, 1) in Page program.)
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SIMULTANEOUS READ/WRITE OPERATION
The TC58FVM6T2A/B2A features a Simultaneous Read/Write operation. The Simultaneous Read/Write operation
enables the device to simultaneously write data to or erase data from a bank while reading data from another bank.
The TC58FVM6T2A/B2A has a total of four banks (8Mbits: 24Mbits: 24Mbits: 8Mbits). Banks can be switched
between using the bank addresses (A21~A19). For a description of bank blocks and addresses, please refer to the
Block Address Table and Block Size Table.
The Simultaneous Read/Write operation cannot perform multiple operations within a single bank. The table
below shows the operation modes in which simultaneous operation can be performed.
Note that during Auto-Program execution or Auto Block Erase operation, the Simultaneous Read/Write operation
cannot read data from addresses in the same bank which have not been selected for operation. Data from these
addresses can be read using the Program Suspend or Erase Suspend function, however.
SIMULTANEOUS READ/WRITE OPERATION
STATUS OF BANK ON WHICH OPERATION IS BEING
PERFORMED
STATUS OF OTHER BANKS
Read Mode
(1)
ID Read Mode
Auto-Program Mode
Auto-Page Program Mode
(2)
Fast Program Mode
Program Suspend Mode
Read Mode
Auto Block Erase Mode
(3)
Auto Multiple Block Erase Mode
Erase Suspend Mode
Program during Erase Suspend
Program Suspend during Erase Suspend
CFI Mode
(1) Only Command Mode is valid.
(2) Including times when Acceleration Mode is in use.
(3) If the selected blocks are spread across all nine banks, simultaneous operation cannot be carried out.
OPERATION MODES
In addition to the Read, Write and Erase Modes, the TC58FVM6T2A/B2A features many functions including
block protection and data polling. When incorporating the device into a deign, please refer to the timing charts and
flowcharts in combination with the description below.
READ MODE ( PAGE READ )
To read data from the memory cell array, set the device to Read Mode. In Read Mode the device can perform
high-speed random access and Page Read as asynchronous ROM.
The device is automatically set to Read Mode immediately after power-on or on completion of automatic
operation. A software reset releases ID Read Mode and the lock state which the device enters if automatic
operation ends abnormally, and sets the device to Read Mode. A hardware reset terminates operation of the
device and resets it to Read Mode. When reading data without changing the address immediately after
power-on, either input a hardware Reset or change CE from H to L.
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ID Read Mode
ID Read Mode is used to read the device maker code and device code. The mode is useful in that it allows
EPROM programmers to identify the device type automatically.
ID read can be executed in two ways, as follows:
(1) Applying VID to A9
This method is used mainly by EPROM programmers. Applying VID to A9 sets the device to ID Read
Mode, outputting the maker code from address 00h and the device code from address 01h. Releasing VID
from A9 returns the device to Read Mode. With this method all banks are set to ID Read Mode; thus,
simultaneous operation cannot be performed.
(2) Input command sequence
With this method simultaneous operation can be performed. Inputting an ID Read command sets the
specified bank to ID Read Mode. Banks are specified by inputting the bank address (BK) in the third Bus
Write cycle of the Command cycle. To read an ID code, the bank address as well as the ID read address must
be specified (with WP/ACC = VIH or VIL). The maker code is output from address BK + 00; the device code
is output from address BK + 01. From other banks data are output from the memory cells. Inputting a Reset
command releases ID Read Mode and returns the device to Read Mode.
Access time in ID Read Mode is the same as that in Read Mode. For a list of the codes, please refer to the
ID Code Table.
Standby Mode
There are two ways to put the device into Standby Mode.
(1) Control using CE and RESET
With the device in Read Mode, input VDD ± 0.3 V to CE and RESET . The device will enter Standby
Mode and the current will be reduced to the standby current (IDDS1). However, if the device is in the
process of performing simultaneous operation, the device will not enter Standby Mode but will instead
cause the operating current to flow.
(2) Control using RESET only
With the device in Read Mode, input VSS ± 0.3 V to RESET . The device will enter Standby Mode and the
current will be reduced to the standby current (IDDS1). Even if the device is in the process of performing
simultaneous operation, this method will terminate the current operation and set the device to Standby
Mode. This is a hardware reset and is described later.
In Standby Mode DQ is put in High-Impedance state.
Auto-Sleep Mode
This function suppresses power dissipation during reading. If the address input does not change for 150 ns,
the device will automatically enter Sleep Mode and the current will be reduced to the standby current (IDDS2).
However, if the device is in the process of performing simultaneous operation, the device will not enter Standby
Mode but will instead cause the operating current to flow. Because the output data is latched, data is output in
Sleep Mode. When the address is changed, Sleep Mode is automatically released, and data from the new
address is output.
Output Disable Mode
Inputting VIH to OE disables output from the device and sets DQ to High-Impedance.
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Command Write
The TC58FVM6T2A/B2A uses the standard JEDEC control commands for a single-power supply E2PROM. A
Command Write is executed by inputting the address and data into the Command Register. The command is
written by inputting a pulse to WE with CE = VIL and OE = VIH ( WE control). The command can also be
written by inputting a pulse to CE with WE = VIL ( CE control). The address is latched on the falling edge of
either WE or CE . The data is latched on the rising edge of either WE or CE . DQ0~DQ7 are valid for data
input and DQ8~DQ15 are ignored.
To abort input of the command sequence use the Reset command. The device will reset the Command Register
and enter Read Mode. If an undefined command is input, the Command Register will be reset and the device
will enter Read Mode.
Software Reset
Apply a software reset by inputting a Read/Reset command. A software reset returns the device from ID Read
Mode or CFI Mode to Read Mode, releases the lock state if automatic operation has ended abnormally, and
clears the Command Register.
Hardware Reset
A hardware reset initializes the device and sets it to Read Mode. When a pulse is input to RESET for tRP,
the device abandons the operation which is in progress and enters Read Mode after tREADY. Note that if a
hardware reset is applied during data overwriting, such as a Write or Erase operation, data at the address or
block being written to at the time of the reset will become undefined.
After a hardware reset the device enters Read Mode if RESET = VIH or Standby Mode if RESET = VIL.
The DQ pins are High-Impedance when RESET = VIL. After the device has entered Read Mode, Read
operations and input of any command are allowed.
Comparison between Software Reset and Hardware Reset
ACTION
SOFTWARE RESET
HARDWARE RESET
Releases ID Read Mode or CFI Mode.
True
True
Clears the Command Register.
True
True
Releases the lock state if automatic operation has ended abnormally.
True
True
Stops any automatic operation which is in progress.
False
True
Stops any operation other than the above and returns the device to
Read Mode.
False
True
BYTE/Word Mode
BYTE is used select Word Mode (16 bits) or Byte Mode (8 bits) for the TC58FVM6T2A/B2A. If VIH is input to
BYTE , the device will operate in Word Mode. Read data or write commands using DQ0~DQ15. When VIL is
input to BYTE , read data or write commands using DQ0~DQ7. DQ15/A-1 is used as the lowest address.
DQ8~DQ14 will become High-Impedance.
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Auto-Program Mode
The TC58FVM6T2A/B2A can be programmed in either byte or word units. Auto-Program Mode is set using
the Program command. The program address is latched on the falling edge of the WE signal and data is
latched on the rising edge of the fourth Bus Write cycle (with WE control). Auto programming starts on the
rising edge of the WE signal in the fourth Bus Write cycle. The Program and Program Verify commands are
automatically executed by the chip. The device status during programming is indicated by the Hardware
Sequence flag. To read the Hardware Sequence flag, specify the address to which the Write is being performed.
During Auto Program execution, a command sequence for the bank on which execution is being performed
cannot be accepted. To terminate execution, use a hardware reset. Note that if the Auto-Program operation is
terminated in this manner, the data written so far is invalid.
Any attempt to program a protected block is ignored. In this case the device enters Read Mode 3 µs after the
rising edge of the WE signal in the fourth Bus Write cycle.
If an Auto-Program operation fails, the device remains in the programming state and does not automatically
return to Read Mode. The device status is indicated by the Hardware Sequence flag. Either a Reset command or
a hardware reset is required to return the device to Read Mode after a failure. If a programming operation fails,
the block which contains the address to which data could not be programmed should not be used.
The device allows 0s to be programmed into memory cells which contain a 1. 1s cannot be programmed into
cells which contain 0s. If this is attempted, execution of Auto Program will fail. This is a user error, not a device
error. A cell containing 0 must be erased in order to set it to 1.
Auto-Page Program Mode
Auto-Page Program is a function which enables to simultaneously program 8words or 16bytes data.
In this mode Program time for 64M bit is less than 60% compare with Auto program mode. In word mode,
input page program command during first bus write cycle to third bus write cycle. Input program data and
address of (A0, A1, A2) = (0, 0, 0) in forth bus write cycle. Input increment address and program data during
fifth bus write cycle to eleventh bus write cycle. After input eleventh bus write cycle , page program operation
start. In byte mode, input increment address and program data of (A-1, A0, A1, A2) = (0, 0, 0, 0) --- (A-1, A0, A1,
A2) = (1, 1, 1, 1) during fifth bus write cycle to nineteenth bus write cycle.
Fast Program Mode
Fast Program is a function which enables execution of the command sequence for the Auto Program to be
completed in two cycles. In this mode the first two cycles of the command sequence, which normally requires
four cycles, are omitted. Writing is performed in the remaining two cycles. To execute Fast Program, input the
Fast Program command. Write in this mode uses the Fast Program command but operation is the same at that
for ordinary Auto-Program. The status of the device is indicated by the Hardware Sequence flag and read
operations can be performed as usual. To exit this mode, the Fast Program Reset command must be input.
When the command is input, the device will return to Read Mode.
Acceleration Mode
The TC58FVM6T2A/B2A features Acceleration Mode which allows write time to be reduced. Applying VACC
to WP or ACC automatically sets the device to Acceleration Mode. In Acceleration Mode, Block Protect Mode
changes to Temporary Block Unprotect Mode. Write Mode changes to Fast Program Mode. Modes are switched
by the WP/ACC signal; thus, there is no need for a Temporary Block Unprotect operation or to set or reset Fast
Program Mode. Operation of Write is the same as in Auto-Program Mode. Removing VACC from WP/ACC
terminates Acceleration Mode.
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Program Suspend/Resume Mode
Program Suspend is used to enable Data Read by suspending the Write operation. The device accepts a
Program Suspend command in Write Mode (including Write operations performed during Erase Suspend) but
ignores the command in other modes. When the command is input, the address of the bank on which Write is
being performed must be specified. After input of the command, the device will enter Program Suspend Read
Mode after tSUSP.
During Program Suspend, Cell Data Read, ID Read and CFI Data Read can be performed. When Data Write
is suspended, the address to which Write was being performed becomes undefined. ID Read and CFI Data Read
are the same as usual.
After completion of Program Suspend input a Program Resume command to return to Write Mode. When
inputting the command, specify the address of the bank on which Write is being performed. If the ID Read or
CFI Data Read functions is being used, abort the function before inputting the Resume command. On receiving
the Resume command, the device returns to Write Mode and resumes outputting the Hardware Sequence flag
for the bank to which data is being written.
Program Suspend can be run in Fast Program Mode or Acceleration Mode. However, note that when running
Program Suspend in Acceleration Mode, VACC must not be released.
Auto Chip Erase Mode
The Auto Chip Erase Mode is set using the Chip Erase command. An Auto Chip Erase operation starts on the
rising edge of WE in the sixth bus cycle. All memory cells are automatically preprogrammed to 0, erased and
verified as erased by the chip. The device status is indicated by the Hardware Sequence flag.
Command input is ignored during an Auto Chip Erase. A hardware reset can interrupt an Auto Chip Erase
operation. If an Auto Chip Erase operation is interrupted, it cannot be completed correctly. Hence an additional
Erase operation must be performed.
Any attempt to erase a protected block is ignored. If all blocks are protected, the Auto Erase operation will not
be executed and the device will enter Read mode 250µs after the rising edge of the WE signal in the sixth bus
cycle.
If an Auto Chip Erase operation fails, the device will remain in the erasing state and will not return to Read
Mode. The device status is indicated by the Hardware Sequence flag. Either a Reset command or a hardware
reset is required to return the device to Read Mode after a failure.
In this case it cannot be ascertained which block the failure occurred in. Either abandon use of the device
altogether, or perform a Block Erase on each block, identify the failed block, and stop using it. The host
processor must take measures to prevent subsequent use of the failed block.
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TC58FVM6(T/B)2A(FT/XB)65
Auto Block Erase/Auto Multi-Block Erase Modes
The Auto Block Erase Mode and Auto Multi-Block Erase Mode are set using the Block Erase command. The
block address is latched on the falling edge of the WE signal in the sixth bus cycle. The block erase starts as
soon as the Erase Hold Time (tBEH) has elapsed after the rising edge of the WE signal. When multiple blocks
are erased, the sixth Bus Write cycle is repeated with each block address and Auto Block Erase command being
input within the Erase Hold Time (this constitutes an Auto Multi-Block Erase operation). If a command other
than an Auto Block Erase command or Erase Suspend command is input during the Erase Hold Time, the
device will reset the Command Register and enter Read Mode. The Erase Hold Time restarts on each successive
rising edge of WE . Once operation starts, all memory cells in the selected block are automatically
preprogrammed to 0, erased and verified as erased by the chip. The device status is indicated by the setting of
the Hardware Sequence flag. When the Hardware Sequence flag is read, the addresses of the blocks on which
auto-erase operation is being performed must be specified. If the selected blocks are spread across all nine
banks, simultaneous operation cannot be carried out.
All commands (except Erase Suspend) are ignored during an Auto Block Erase or Auto Multi-Block Erase
operation. Either operation can be aborted using a Hardware Reset. If an auto-erase operation is interrupted, it
cannot be completed correctly; therefore, a further erase operation is necessary to complete the erasing.
Any attempt to erase a protected block is ignored. If all the selected blocks are protected, the auto-erase
operation is not executed and the device returns to Read Mode 250µs after the rising edge of the WE signal in
the last bus cycle.
If an auto-erase operation fails, the device remains in Erasing state and does not return to Read Mode. The
device status is indicated by the Hardware Sequence flag. After a failure either a Reset command or a Hardware
Reset is required to return the device to Read Mode. If multiple blocks are selected, it will not be possible to
ascertain the block in which the failure occurred. In this case either abandon use of the device altogether, or
perform a Block Erase on each block, identify the failed block, and stop using it. The host processor must take
measures to prevent subsequent use of the failed block.
Erase Suspend/Erase Resume Modes
Erase Suspend Mode suspends Auto Block Erase and reads data from or writes data to an unselected block.
The Erase Suspend command is allowed during an auto block erase operation but is ignored in all other
operation modes. When the command is input, the address of the bank on which Erase is being performed must
be specified.
In Erase Suspend Mode only a Read, Program or Resume command can be accepted. If an Erase Suspend
command is input during an Auto Block Erase, the device will enter Erase Suspend Read Mode after tSUSE. The
device status (Erase Suspend Read Mode) can be verified by checking the Hardware Sequence flag. If data is
read consecutively from the block selected for Auto Block Erase, the DQ2 output will toggle and the DQ6 output
will stop toggling and RY/ BY will be set to High-Impedance.
Inputting a Write command during an Erase Suspend enables a Write to be performed to a block which has
not been selected for the Auto Block Erase. Data is written in the usual manner.
To resume the Auto Block Erase, input an Erase Resume command. On input of the command, the address of
the bank on which the Write was being performed must be specified. On receiving an Erase Resume command,
the device returns to the state it was in when the Erase Suspend command was input. If an Erase Suspend
command is input during the Erase Hold Time, the device will return to the state it was in at the start of the
Erase Hold Time. At this time more blocks can be specified for erasing. If an Erase Resume command is input
during an Auto Block Erase, Erase resumes. At this time toggle output of DQ6 resumes and 0 is output on
RY/ BY .
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TC58FVM6(T/B)2A(FT/XB)65
BLOCK PROTECTION
Block Protection is a function for disabling writing and erasing specific blocks. Block protection can be carried
out in two ways: by supplying a high voltage (VID) to the device (see Block protection 1) or by supplying a high
voltage and a command sequence (see Block protection 2).
(1) Block protection 1
Specify a device block address and make the following signal settings A9 = OE = VID, A1 = VIH and CE
= A0 = A6 = VIL. Now when a pulse is input to WE for tPPLH, the device will start to write to the block
protection circuit. Block protection can be verified using the Verify Block Protect command. Inputting VIL
on OE sets the device to Verify Mode. 01H is output if the block is protected and 00H is output if the block
is unprotected. If block protection was unsuccessful, the operation must be repeated. Releasing VID from A9
and OE terminates this mode.
(2) Block protection 2
Applying VID to RESET and inputting the Block Protect 2 command also performs block protection. The
first cycle of the command sequence is the Set-up command. In the second cycle, the Block Protect command
is input, in which a block address and A1 = VIH and A0 = A6 = VIL are input. Now the device writes to the
block protection circuit. There is a wait of tPPLH until this write is completed; however, no intervention is
necessary during this time. In the third cycle the Verify Block Protect command is input. This command
verifies the write to the block protection circuit. Read is performed in the fourth cycle. If the protection
operation is complete, 01H is output. If a value other than 01H is output, block protection is not complete
and the Block Protect command must be input again. Removing the VID input from RESET exits this
mode.
Temporary Block Unprotection
The TC58FVM6T2A/B2A has a temporary block unprotection feature which disables block protection for all
protected blocks. Unprotection is enabled by applying VID to the RESET pin. Now Write and Erase operations
can be performed on all blocks except the boot blocks which have been protected by the Boot Block Protect
operation. The device returns to its previous state when VID is removed from the RESET pin. That is,
previously protected blocks will be protected again.
Verify Block Protect
The Verify Block Protect command is used to ascertain whether a block is protected or unprotected.
Verification is performed either by inputting the Verify Block Protect command or by applying VID to the A9 pin,
as for ID Read Mode, and setting the block address = A0 = A6 = VIL and A1 = VIH. If the block is protected, 01H
is output. If the block is unprotected, 00H is output.
Boot Block Protection
Boot block protection temporarily protects certain boot blocks using a method different from ordinary block
protection. Neither VID nor a command sequence is required. Protection is performed simply by inputting VIL
on WP/ACC . The target blocks are the two pairs of boot blocks. The top boot blocks are BA133 and BA134; the
bottom boot blocks are BA0 and BA1. Inputting VIH on WP/ACC releases the mode. From now on, if it is
necessary to protect these blocks, the ordinary Block Protection Mode must be used.
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TC58FVM6(T/B)2A(FT/XB)65
Hidden ROM Area
The TC58FVM6T2A/B2A features a 64-Kbyte hidden ROM area which is separate from the memory cells. The
area consists of one block. Data Read, Write and Protect can be performed on this block. Because Protect cannot
be released, once the block is protected, data in the block cannot be overwritten.
The hidden ROM area is located in the address space indicated in the HIDDEN ROM AREA ADDRESS
TABLE. To access the Hidden ROM area, input a Hidden ROM Mode Entry command. The device now enters
Hidden ROM Mode, allowing Read, Write, Erase and Block Protect to be executed. Write and Erase operations
are the same as auto operations except that the device is in Hidden ROM Mode. To protect the hidden ROM
area, use the block protection function. The operation of Block Protect here is the same as a normal Block
Protect except that VIH rather than VID is input to RESET . Once the block has been protected, protection
cannot be released, even using the temporary block unprotection function. Use Block Protect carefully. Note that
in Hidden ROM Mode, simultaneous operation cannot be performed for BANK3 in top boot type and for BANK0
in bottom boot type.
To exit Hidden ROM Mode, use the Hidden ROM Mode Exit command. This will return the device to Read
Mode.
HIDDEN ROM AREA ADDRESS TABLE
TYPE
BOOT BLOCK
ARCHITECTURE
BYTE MODE
WORD MODE
ADDRESS RANGE
SIZE
ADDRESS RANGE
SIZE
TC58FVM6T2A
TOP BOOT BLOCK
7F0000h~7FFFFFh
64 Kbytes
3F8000h~3FFFFFh
32 Kwords
TC58FVM6B2A
BOTTOM BOOT BLOCK
000000h~00FFFFh
64 Kbytes
000000h~007FFFh
32 Kwords
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TC58FVM6(T/B)2A(FT/XB)65
COMMON FLASH MEMORY INTERFACE (CFI)
The TC58FVM6T2A/B2A conforms to the CFI specifications. To read information from the device, input the
Query command followed by the address. In Word Mode DQ8~DQ15 all output 0s. To exit this mode, input the
Reset command.
CFI CODE TABLE
ADDRESS A6~A0
DATA DQ15~DQ0
DESCRIPTION
10h
11h
12h
0051h
0052h
0059h
ASCII string “QRY”
13h
14h
0002h
0000h
Primary OEM command set
2: AMD/FJ standard type
15h
16h
0040h
0000h
Address for primary extended table
17h
18h
0000h
0000h
Alternate OEM command set
0: none exists
19h
1Ah
0000h
0000h
Address for alternate OEM extended table
1Bh
0023h
VDD (min) (Write/Erase)
DQ7~DQ4: 1 V
DQ3~DQ0: 100 mV
1Ch
0036h
VDD (max) (Write/Erase)
DQ7~DQ4: 1 V
DQ3~DQ0: 100 mV
1Dh
0000h
VPP (min) voltage
1Eh
0000h
VPP (max) voltage
1Fh
0004h
Typical time-out per single byte/word write (2 µs)
20h
0000h
Typical time-out for minimum size buffer write (2 µs)
21h
000Ah
Typical time-out per individual block erase (2 ms)
22h
0000h
Typical time-out for full chip erase (2 ms)
23h
0005h
Maximum time-out for byte/word write (2 times typical)
24h
0000h
Maximum time-out for buffer write (2 times typical)
25h
0004h
Maximum time-out per individual block erase (2 times typical)
26h
0000h
Maximum time-out for full chip erase (2 times typical)
27h
0017h
Device Size (2 byte)
28h
29h
0002h
0000h
Flash device interface description
2: ×8/×16
2Ah
2Bh
0004h
0000h
Maximum number of bytes in multi-byte write (2 )
N
N
N
N
N
N
N
N
N
N
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TC58FVM6(T/B)2A(FT/XB)65
ADDRESS A6~A0
DATA DQ15~DQ0
DESCRIPTION
2Ch
0002h
Number of erase block regions within device
2Dh
2Eh
2Fh
30h
0007h
0000h
0020h
0000h
Erase Block Region 1 information
Bits 0~15: y = block number
Bits 16~31: z = block size
(z × 256 bytes)
31h
32h
33h
34h
007Eh
0000h
0000h
0001h
Erase Block Region 2 information
40h
41h
42h
0050h
0052h
0049h
ASCII string “PRI”
43h
0031h
Major version number, ASCII
44h
0031h
Minor version number, ASCII
45h
0000h
Address-Sensitive Unlock
0: Required
1: Not required
46h
0002h
Erase Suspend
0: Not supported
1: For Read-only
2: For Read & Write
47h
0001h
Block Protect
0: Not supported
X: Number of blocks per group
48h
0001h
Block Temporary Unprotect
0: Not supported
1: Supported
49h
0004h
Block Protect/Unprotect scheme
4Ah
0001h
Simultaneous operation
0: Not supported
1: Supported
4Bh
0000h
Burst Mode
0: Not supported
4Ch
0001h
Page Mode
0: Not supported
1: Supported
4Dh
0085h
VACC (min) voltage
DQ7~DQ4: 1 V
DQ3~DQ0: 100 mV
4Eh
0095h
VACC (max) voltage
DQ7~DQ4: 1 V
DQ3~DQ0: 100 mV
4Fh
000Xh
Top/Bottom Boot Block Flag
2: TC58FVM6B2A
3: TC58FVM6T2A
50h
0001h
Program Suspend
0: Not supported
1: Supported
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TC58FVM6(T/B)2A(FT/XB)65
ADDRESS A6~A0
DATA DQ15~DQ0
DESCRIPTION
57h
0004h
Bank Organization
00h: Data at 4Ah is zero
X: Number of Banks
58h
00XXh
Bank0 Region information
X = Number of blocks in Bank0
TOP: 10h
BOTTOM: 17h
59h
00XXh
Bank1 Region information
X = Number of blocks in Bank1
TOP: 30h
BOTTOM: 30h
5Ah
00XXh
Bank2 Region information
X = Number of blocks in Bank2
TOP: 30h
BOTTOM: 30h
5Bh
00XXh
Bank3 Region information
X = Number of blocks in Bank3
TOP: 17h
BOTTOM: 10h
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TC58FVM6(T/B)2A(FT/XB)65
HARDWARE SEQUENCE FLAGS
The TC58FVM6T2A/B2A has a Hardware Sequence flag which allows the device status to be determined during
an auto mode operation. The output data is read out using the same timing as that used when CE = OE = VIL in
Read Mode. The RY/ BY output can be either High or Low.
The device re-enters Read Mode automatically after an auto mode operation has been completed successfully. The
Hardware Sequence flag is read to determine the device status and the result of the operation is verified by
comparing the read-out data with the original data.
STATUS
DQ7
DQ6
DQ5
DQ3
DQ2
RY/BY
DQ 7 (4)
Toggle
0
0
1
0
Data
Data
Data
Data
Data
High-Z
0
Toggle
0
0
Toggle
0
0
Toggle
0
0
1
0
Selected
0
Toggle
0
1
Toggle
0
Not-selected
0
Toggle
0
1
1
0
Selected
1
1
0
0
Toggle
High-Z
Not-selected
Data
Data
Data
Data
Data
High-Z
Selected
DQ 7 (4)
Toggle
0
0
Toggle
0
Not-selected
(4)
DQ 7
Toggle
0
0
1
0
Auto Programming/Auto Page Programming
DQ 7 (4)
Toggle
1
0
1
0
0
Toggle
1
1
NA
0
DQ 7 (4)
Toggle
1
0
NA
0
Auto Programming/Auto Page Programming
(1)
Read in Program Suspend
(2)
Erase Hold Time
Selected
(3)
Not-selected
In Auto
Erase
In Progress
Auto Erase
Read
In Erase
Suspend
Programming
Time Limit
Exceeded
Auto Erase
Programming in Erase Suspend
Notes: DQ outputs cell data and RY/BY goes High-Impedence when the operation has been completed.
DQ0 and DQ1 pins are reserved for future use.
0 is output on DQ0, DQ1 and DQ4.
(1) Data output from an address to which Write is being performed is undefined.
(2) Output when the block address selected for Auto Block Erase is specified and data is read from there.
During Auto Chip Erase, all blocks are selected.
(3) Output when a block address not selected for Auto Block Erase of same bank as selected block is specified and data is
read from there.
(4) In case of Page program operation is program data of (A0, A1, A2) = (1, 1, 1) in eleventh bus write cycle in word mode.
Program data of (A-1, A0, A1, A2) = (1, 1, 1, 1) in nineteenth bus write cycle in byte mode.
DQ7 ( DATA polling)
During an Auto-Program or auto-erase operation, the device status can be determined using the data polling
function. DATA polling begins on the rising edge of WE in the last bus cycle. In an Auto-Program operation,
DQ7 outputs inverted data during the programming operation and outputs actual data after programming has
finished. In an auto-erase operation, DQ7 outputs 0 during the Erase operation and outputs 1 when the Erase
operation has finished. If an Auto-Program or auto-erase operation fails, DQ7 simply outputs the data.
When the operation has finished, the address latch is reset. Data polling is asynchronous with the OE
signal.
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TC58FVM6(T/B)2A(FT/XB)65
DQ6 (Toggle bit 1)
The device status can be determined by the Toggle Bit function during an Auto-Program or auto-erase
operation. The Toggle bit begins toggling on the rising edge of WE in the last bus cycle. DQ6 alternately
outputs a 0 or a 1 for each OE access while CE = VIL while the device is busy. When the internal operation
has been completed, toggling stops and valid memory cell data can be read by subsequent reading. If the
operation fails, the DQ6 output toggles.
If an attempt is made to execute an Auto Program operation on a protected block, DQ6 will toggle for around
3 µs. It will then stop toggling. If an attempt is made to execute an auto erase operation on a protected block,
DQ6 will toggle for around 250 µs. It will then stop toggling. After toggling has stopped the device will return to
Read Mode.
DQ5 (internal time-out)
If the internal timer times out during a Program or Erase operation, DQ5 outputs a 1. This indicates that the
operation has not been completed within the allotted time.
Any attempt to program a 1 into a cell containing a 0 will fail (see Auto-Program Mode). In this case DQ5
outputs a 1. Either a hardware reset or a software Reset command is required to return the device to Read
Mode.
DQ3 (Block Erase timer)
The Block Erase operation starts 50 µs (the Erase Hold Time) after the rising edge of WE in the last
command cycle. DQ3 outputs a 0 for the duration of the Block Erase Hold Time and a 1 when the Block Erase
operation starts. Additional Block Erase commands can only be accepted during the Block Erase Hold Time.
Each Block Erase command input within the hold time resets the timer, allowing additional blocks to be marked
for erasing. DQ3 outputs a 1 if the Program or Erase operation fails.
DQ2 (Toggle bit 2)
DQ2 is used to indicate which blocks have been selected for Auto Block Erase or to indicate whether the
device is in Erase Suspend Mode.
If data is read continuously from the selected block during an Auto Block Erase, the DQ2 output will toggle.
Now 1 will be output from non-selected blocks; thus, the selected block can be ascertained. If data is read
continuously from the block selected for Auto Block Erase while the device is in Erase Suspend Mode, the DQ2
output will toggle. Because the DQ6 output is not toggling, it can be determined that the device is in Erase
Suspend Mode. If data is read from the address to which data is being written during Erase Suspend in
Programming Mode, DQ2 will output a 1.
RY/BY (READY/ BUSY )
TC58FVM6T2A/B2A has a RY/ BY signal to indicate the device status to the host processor. A 0 (Busy state)
indicates that an Auto-Program or auto-erase operation is in progress. A 1 (Ready state) indicates that the
operation has finished and that the device can now accept a new command. RY/ BY outputs a 0 when an
operation has failed.
RY/ BY outputs a 0 after the rising edge of WE in the last command cycle.
During an Auto Block Erase operation, commands other than Erase Suspend are ignored. RY/ BY outputs a
1 during an Erase Suspend operation. The output buffer for the RY/ BY pin is an open-drain type circuit,
allowing a wired-OR connection. A pull-up resistor must be inserted between VDD and the RY/ BY pin.
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TC58FVM6(T/B)2A(FT/XB)65
DATA PROTECTION
The TC58FVM6T2A/B2A includes a function which guards against malfunction or data corruption.
Protection against Program/Erase Caused by Low Supply Voltage
To prevent malfunction at power-on or power-down, the device will not accept commands while VDD is below
VLKO. In this state, command input is ignored.
If VDD drops below VLKO during an Auto Operation, the device will terminate Auto-Program execution. In
this case, Auto operation is not executed again when VDD return to recommended VDD voltage Therefore,
command need to be input to execute Auto operation again.
When VDD > VLKO, make up countermeasure to be input accurately command in system side please.
Protection against Malfunction Caused by Glitches
To prevent malfunction during operation caused by noise from the system, the device will not accept pulses
shorter than 3 ns (Typ.) input on WE , CE or OE . However, if a glitch exceeding 3 ns (Typ.) occurs and the
glitch is input to the device malfunction may occur.
The device uses standard JEDEC commands. It is conceivable that, in extreme cases, system noise may be
misinterpreted as part of a command sequence input and that the device will acknowledge it. Then, even if a
proper command is input, the device may not operate. To avoid this possibility, clear the Command Register
before command input. In an environment prone to system noise, Toshiba recommend input of a software or
hardware reset before command input.
Protection against Malfunction at Power-on
To prevent damage to data caused by sudden noise at power-on, when power is turned on with WE = CE =
VIL the device does not latch the command on the first rising edge of WE or CE . Instead, the device
automatically Resets the Command Register and enters Read Mode.
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TC58FVM6(T/B)2A(FT/XB)65
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VDD
PARAMETER
RANGE
−0.6~4.6
VDD Supply Voltage
VIN
V
(1)
−0.6~VDD + 0.5 (≤ 4.6)
Input Voltage
VDQ
UNIT
V
(1)
−0.6~VDD + 0.5 (≤ 4.6)
Input/Output Voltage
VIDH
Maximum Input Voltage for A9, OE and RESET
VACCH
Maximum Input Voltage for WP/ACC
PD
(2)
V
13.0
V
10.5
V
Power Dissipation
600
mW
Tsolder
Soldering Temperature (10s)
260
°C
Tstg
Storage Temperature
−55~150
°C
Topr
Operating Temperature
−40~85
°C
100
mA
IOSHORT
(1)
(2)
(3)
Output Short-Circuit Current
(2)
(3)
This level may undershoot to −2.0 V for periods < 20 ns, and may overshoot to +2.0 V for periods < 20 ns.
Do not apply VID/VACC when the supply voltage is not within the device's recommended operating voltage range.
Outputs should be shorted for no more than one second.
No more than one output should be shorted at a time.
CAPACITANCE (Ta = 25°C, f = 1 MHz)
TSOPI
SYMBOL
PARAMETER
CONDITION
MAX
UNIT
CIN
Input Pin Capacitance
VIN = 0 V
4
pF
COUT
Output Pin Capacitance
VOUT = 0 V
8
pF
CIN2
Control Pin Capacitance
VIN = 0 V
8
pF
MAX
UNIT
This parameter is periodically sampled and is not tested for every device.
TFBGA
SYMBOL
PARAMETER
CONDITION
CIN
Input Pin Capacitance
VIN = 0 V
4
pF
COUT
Output Pin Capacitance
VOUT = 0 V
8
pF
CIN2
Control Pin Capacitance
VIN = 0 V
9
pF
MIN
MAX
UNIT
2.3
3.6
This parameter is periodically sampled and is not tested for every device.
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
PARAMETER
VDD
VDD Supply Voltage
VIH
Input High-Level Voltage
0.7 × VDD
VDD + 0.3
VIL
Input Low-Level Voltage
−0.3
0.2 × VDD
VID
High-Level Voltage for A9, OE and RESET
11.4
12.6
VACC
High-Level Voltage for WP/ACC
8.5
9.5
Ta
Operating Temperature
−40
85
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°C
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TC58FVM6(T/B)2A(FT/XB)65
DC CHARACTERISTICS
SYMBOL
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
ILI
Input Leakage Current
0 V ≤ VIN ≤ VDD


±1
ILO
Output Leakage Current
0 V ≤ VOUT ≤ VDD


±1
VOH
Output High Voltage
IOH = −0.1 mA
VDD − 0.4


IOH = −2.5 mA
0.85 × VDD


VOL
Output Low Voltage
IOL = 4.0 mA


0.4
IDDO1
VDD Average Random Read
Current
VIN = VIH/VIL, IOUT = 0 mA
tRC = 100 ns (MIN)

35
55
IDDO2
VDD Average Program Current
VIN = VIH/VIL, IOUT = 0 mA

8
15
IDDO3
VDD Average Erase Current
VIN = VIH/VIL, IOUT = 0 mA

8
15
IDDO4
VDD Average
Read-While-Program Current
VIN = VIH/VIL, IOUT = 0 mA
tRC = 100 ns (MIN)

43
70
IDDO5
VDD Average
Read-while-Erase Current
VIN = VIH/VIL, IOUT = 0 mA
tRC = 100 ns (MIN)

43
70
IDDO6
VDD Average Program-whileErase-Suspend Current
VIN = VIH/VIL, IOUT = 0 mA

8
15
IDDO7
VDD Average Page Read
Current
VIN = VIH/VIL, IOUT = 0 mA
tPRC = 25 ns (MIN)

1
5
IDDO8
VDD Average Address
(2)
Increment Read Current
VIN = VIH/VIL, IOUT = 0 mA
tRC = 100 ns (MIN)
tPRC = 25ns (MIN)

5
11
IDDS1
VDD Standby Current
CE = RESET = VDD
or RESET = VSS

2
10
IDDS2
VDD Standby Current
(1)
(Automatic Sleep Mode )
VIH = VDD
VIL = VSS

2
10
IID
High-Voltage Input Current for
A9, OE and RESET
11.4 V ≤ VID ≤ 12.6 V


35
IACC
High-Voltage Input Current for
WP/ACC
8.5 V ≤ VACC ≤ 9.5 V


20
mA
VLKO
Low-VDD Lock-out Voltage
1.5

2.0
V

µA
V
mA
µA
(1) The device enters Automatic Sleep Mode in which the address remains fixed for during 150 ns.
(2) (IDDO1 + IDDO7 × 7)/8words
AC TEST CONDITIONS
PARAMETER
Input Pulse Level
Input Pulse Rise and Fall Time (10%~90%)
CONDITION
VDD, 0.0 V
5 ns
Timing Measurement Reference Level (input)
VDD/2, VDD/2
Timing Measurement Reference Level (output)
VDD/2, VDD/2
Output Load
CL (100 pF) + 1 TTL Gate/CL (30 pF) + 1 TTL Gate
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TC58FVM6(T/B)2A(FT/XB)65
AC CHARACTERISTICS AND OPERATING CONDITIONS
READ CYCLE
Product name
TC58FVM6T2A/B2A
VDD = 2.7-3.6 V
VDD voltage (V)
Output load capacitance (CL)
SYMBOL
30 pF
PARAMETER
VDD = 2.3-3.6V
100 pF
30 pF
100 pF
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
tRC
Read Cycle Time
65

70

70

75

ns
tPRC
Page Read Cycle Time
25

30

30

35

ns
tACC
Address Access Time

65

70

70

75
ns
tCE
CE Access Time

65

70

70

75
ns
tOE
OE Access Time

25

30

30

35
ns
tPACC
Page Access Time

25

30

30

35
ns
tCEE
CE to Output Low-Z
0

0

0

0

ns
tOEE
OE to Output Low-Z
0

0

0

0

ns
tOH
Output Data Hold Time
0

0

0

0

ns
tDF1
CE to Output High-Z

25

25

25

25
ns
tDF2
OE to Output High-Z

25

25

25

25
ns
BLOCK PROTECT
SYMBOL
PARAMETER
MIN
MAX
UNIT
tVPT
VID Transition Time
4

µs
tVPS
VID Set-up Time
4

µs
tCESP
CE Set-up Time
4

µs
tVPH
OE Hold Time
4

µs
tPPLH
WE Low-Level Hold Time
100

µs
MIN
TYP.
MAX
UNIT
Auto-Program Time (Byte Mode)

8
300
µs
Auto-Program Time (Word Mode)

11
300
µs
tPPAW
Auto-Page program time

45
2400
µs
tPCEW
Auto Chip Erase Time

95
1350
s
tPBEW
Auto Block Erase Time

0.7
10
s


Cycles
PROGRAM AND ERASE CHARACTERISTICS
SYMBOL
tPPW
tEW
PARAMETER
Erase/Program Cycle
5
10
* Auto Chip Erase Time and Auto Block Erase Time include internal pre program time.
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TC58FVM6(T/B)2A(FT/XB)65
COMMAND WRITE/PROGRAM/ERASE CYCLE
SYMBOL
PARAMETER
UNIT
MIN
MAX
tCMD
Command Write Cycle Time
60

ns
tAS
Address Set-up Time/ BYTE Set-up Time
0

ns
tAH
Address Hold Time/ BYTE Hold Time
30

ns
tDS
Data Set-up Time
30

ns
tDH
Data Hold Time
0

ns
tWELH
WE Low-Level Hold Time
( WE Control)
30

ns
tWEHH
WE High-Level Hold Time
( WE Control)
20

ns
tCES
CE Set-up Time to WE Active
( WE Control)
0

ns
tCEH
CE Hold Time from WE High Level
( WE Control)
0

ns
tCELH
CE Low-Level Hold Time
( CE Control)
30

ns
tCEHH
CE High-Level Hold Time
( CE Control)
20

ns
tWES
WE Set-up time to CE Active
( CE Control)
0

ns
tWEH
WE Hold Time from CE High Level
( CE Control)
0

ns
tOES
OE Set-up Time
0

ns
tOEHP
OE Hold Time (Toggle, Data Polling)
10

ns
tOEHT
OE High-Level Hold Time (Toggle)
20

ns
tAHT
Address Hold Time (Toggle)
0

ns
tAST
Address Set-up Time (Toggle)
0

ns
tBEH
Erase Hold Time
50

µs
tVDS
VDD Set-up Time
500

µs
Program/Erase Valid to RY/BY Delay

90
ns
Program/Erase Valid to RY/BY Delay during Suspend Mode

300
ns
500

ns
tBUSY
tRP
RESET Low-Level Hold Time
tREADY
RESET Low-Level to Read Mode

20
µs
tRB
RY/BY Recovery Time
0

ns
tRH
RESET Recovery Time
50

ns
tCEBTS
CE Set-up time BYTE Transition
5

ns
tBTD
BYTE to Output High-Z

30
ns
tSUSP
Program Suspend Command to Suspend Mode

1.6
µs
tSUSPA
Page Program Suspend Command to Suspend Mode

2.0
µs
tRESP
Program Resume Command to Program Mode

1
µs
tSUSE
Erase Suspend Command to Suspend Mode

15
µs
tRESE
Erase Resume Command to Erase Mode

1
µs
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TC58FVM6(T/B)2A(FT/XB)65
TIMING DIAGRAMS
VIH or VIL
Data invalid
Read/ID Read Operation
tRC
Address
tACC
tOH
tCE
CE
tOE
tDF1
tOEE
OE
tCEE
WE
tDF2
tOEH
DOUT
Output data Valid
Hi-Z
Hi-Z
ID Read Operation (apply VID to A9)
tRC
A0
A1
tACC
A6
VID
VIH
A9
tVPS
tCE
CE
tOE
OE
WE
Hi-Z
DOUT
Read Mode
Manufacturer
code
ID Read Mode
Hi-Z
Device
code
Hi-Z
Read Mode
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TC58FVM6(T/B)2A(FT/XB)65
Page Read Operation
Address(A3-21)))
tPRC
tRC
Address(0-2)
tACC
tCE
CE
tOE
OE
WE
tPACC
DOUT
Hi-Z
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
Hi-Z
DOUT
Read after command input (Only Hidden Rom/CFI Read)
Address
Last command address
CE
OE
WE
tWEHH+tACC
DOUT
Command data
Hi-Z
DOUT
valid
Hi-Z
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TC58FVM6(T/B)2A(FT/XB)65
Command Write Operation
This is the timing of the Command Write Operation. The timing which is described in the following pages is
essentially the same as the timing shown on this page.
•
WE Control
tCMD
Command address
Address
tAS
tAH
CE
tCES
tCEH
WE
tWEL
tWEHH
tDS
Command data
DIN
•
tDH
CE Control
tCMD
Command address
Address
tAS
tAH
CE
tCELH
tCEHH
tWES
tWEH
WE
tDS
DIN
tDH
Command data
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TC58FVM6(T/B)2A(FT/XB)65
ID Read Operation (input command sequence)
Address
555h
2AAh
BK + 555h
tCMD
BK + 00h
BK + 01h
tRC
CE
OE
tOES
WE
DIN
AAh
55h
90h
Manufacturer code
DOUT
Device code
Hi-Z
ID Read Mode
Read Mode (input of ID Read command sequence)
(Continued)
Address
555h
2AAh
555h
tCMD
CE
OE
WE
DIN
DOUT
AAh
55h
F0h
Hi-Z
ID Read Mode (input of Reset command sequence)
Read Mode
Note: Word Mode address shown.
BK: Bank address
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TC58FVM6(T/B)2A(FT/XB)65
Auto-Program Operation (WE Control)
555h
Address
2AAh
555h
PA
PA
tCMD
CE
OE
tOEHP
tOES
tPPW
WE
AAh
DIN
55h
DOUT
A0h
Hi-Z
PD
DQ7
DOUT
tVDS
VDD
Note: Word Mode address shown.
PA: Program address
PD: Program data
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TC58FVM6(T/B)2A(FT/XB)65
Auto Page Program Operation ( WE Control)
PA
Address(A3-21)
PA
tCMD
555h
Address(A0-2)
2AAh
555h
0h
1h
2h
3h
4h
5h
6h
7h
7h
CE
tOEHP
OE
tOES
tPPAW
WE
AAh
DIN
55h
E6h
PD1
DOUT
PD2
PD3
Hi-Z
PD4
PD5
PD6
PD7
PD8
DQ7
DOUT
tVDS
VDD
Note: Word Mode address shown.
PA: Program address
PD: Program Data
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TC58FVM6(T/B)2A(FT/XB)65
Auto Chip Erase/Auto Block Erase Operation ( WE Control)
555h
Address
2AAh
555h
555h
2AAh
555h/BA
tCMD
CE
OE
tOES
WE
AAh
DIN
55h
80h
AAh
55h
10h/30h
tVDS
VDD
Note: Word Mode address shown.
BA: Block address for Auto Block Erase operation
Auto-Program Operation (CE Control)
555h
Address
2AAh
555h
PA
PA
tCMD
CE
tPPW
OE
tOEHP
tOES
WE
DIN
AAh
55h
DOUT
A0h
Hi-Z
PD
DQ7
DOUT
tVDS
VDD
Note: Word Mode address shown.
PA: Program address
PD: Program data
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TC58FVM6(T/B)2A(FT/XB)65
Auto Page Program Operation ( CE Control)
PA
Address(A3-21)
PA
tCMD
555h
Address(A0-2)
2AAh
555h
0h
1h
2h
3h
4h
5h
6h
7h
7h
CE
tOEHP
OE
tOES
tPPAW
WE
AAh
DIN
55h
E6h
PD1
DOUT
PD2
PD3
Hi-Z
PD4
PD5
PD6
PD7
PD8
DQ7
DOUT
tVDS
VDD
Note: Word Mode address shown.
PA: Program address
PD: Program data
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TC58FVM6(T/B)2A(FT/XB)65
Auto Chip Erase/Auto Block Erase Operation ( CE Control)
555h
Address
2AAh
555h
555h
2AAh
555h/BA
tCMD
CE
OE
tOES
WE
AAh
DIN
55h
80h
AAh
55h
10h/30h
tVDS
VDD
Note: Word Mode address shown.
BA: Block address for Auto Block Erase operation
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TC58FVM6(T/B)2A(FT/XB)65
Program/Erase Suspend Operation
BK
Address
RA
CE
OE
WE
tOE
B0h
DIN
tCE
DOUT
DOUT
Hi-Z
Hi-Z
tSUSP/tSUSE
RY/BY
Program/Erase Mode
Suspend Mode
RA: Read address
Program/Erase Resume Operation
Address
RA
BK
PA/BA
CE
OE
tOES
WE
tRESP/tRESE
tDF1
tDF2
tOE
30h
DIN
tCE
DOUT
DOUT
Flag
Hi-Z
Hi-Z
RY/BY
Suspend Mode
Program/Erase Mode
PA: Program address
BK: Bank address
BA: Block address
RA: Read address
Flag: Hardware Sequence flag
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TC58FVM6(T/B)2A(FT/XB)65
RY/BY during Auto Program/Erase Operation
CE
Command input sequence
WE
tBUSY During operation
RY / BY
Hardware Reset Operation
WE
tRB
RESET
tRP
tREADY
RY/BY
Read after RESET
tRC
Address
tRH
RESET
tACC
DOUT
Hi-Z
tOH
Output data valid
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TC58FVM6(T/B)2A(FT/XB)65
BYTE during Read Operation
CE
tCEBTS
OE
BYTE
tBTD
DQ0~DQ7
Data Output
DQ8~DQ14
Data Output
Data Output
tACC
DQ15/A-1
Data Output
Address Input
BYTE during Write Operation
CE
WE
tAS
BYTE
tAH
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TC58FVM6(T/B)2A(FT/XB)65
Hardware Sequence Flag ( DATA Polling)
Address
Last
Command
Address
tCMD
PA/BA
CE
tCE
tOE
tDF1
OE
tOEHP
tDF2
WE
tPPW /tPCEW /tPBEW
tACC
tOH
Last
Command
Data
DIN
DQ7
DQ0~DQ6
DQ7
Valid
Valid
Invalid
Valid
Valid
tBUSY
RY/BY
PA: Program address
BA: Block address
Hardware Sequence Flag (Toggle bit)
Address
tAST
tAST
tAHT
CE
tOEHT
tCE
tAHT
OE
tOEHP
WE
tOE
DIN
Last
Command
Data
DQ2/6
Toggle
Toggle
Toggle
Stop*
Toggle
Valid
tBUSY
RY/BY
*DQ2/DQ6 stops toggling when auto operation has been completed.
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TC58FVM6(T/B)2A(FT/XB)65
Block Protect 1 Operation
Block Protect
Verify Block Protect
BA
Address
A0
A1
tVPT
A6
VID
VIH
A9
VID
VIH
OE
tVPS
tPPLH
tVPH
tVPH
WE
tCESP
tOE
CE
DOUT
Hi-Z
01h*
Hi-Z
BA: Block address
*: 01H indicates that block is protected.
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TC58FVM6(T/B)2A(FT/XB)65
Block Protect 2 Operation
BA
Address
tCMD
BA
tCMD
BA
tCMD
BA + 1
tRC
A0
A1
A6
CE
OE
tPPLH
WE
tVPS
VID
VIH
RESET
DIN
60h
60h
40h
60h
tOE
DOUT
Hi-Z
01h*
BA: Block address
BA + 1: Address of next block
*: 01h indicates that block is protected.
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TC58FVM6(T/B)2A(FT/XB)65
FLOWCHARTS
Auto-Program
Start
Auto-Program Command Sequence
(see below)
DATA Polling or Toggle Bit
Address = Address + 1
No
Last Address?
Yes
Auto-Program
Completed
Auto-Program Command Sequence (address/data)
555h/AAh
2AAh/55h
555h/A0h
Program Address/
Program Data
Note: The above command sequence takes place in Word Mode.
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TC58FVM6(T/B)2A(FT/XB)65
Auto-Page Program
START
Auto page program command sequence
( see below )
DATA Polling or Toggle Bit
Address = Address + 1
No
Last address ?
Yes
Auto-Program
スタート
Completed
555h/AAh
2AAh/55h
555h/E6h
Program address (A2=0,A1=0,A0=0)
/ Program data
Program address (A2=1,A1=0,A0=0)
/ Program data
Program address (A2=0,A1=0,A0=1)
/ Program data
Program address (A2=1,A1=0,A0=1)
/ Program data
Program address (A2=0,A1=1,A0=0)
/ Program data
Program address (A2=1,A1=1,A0=0)
/ Program data
Program address (A2=0,A1=1,A0=1)
/ Program data
Program address (A2=1,A1=1,A0=1)
/ Program data
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TC58FVM6(T/B)2A(FT/XB)65
Fast Program
Start
Fast Program Set Command
Sequence (see below)
Fast Program Command Sequence
(see below)
DATA Polling or Toggle Bit
Address = Address + 1
No
Last Address?
Yes
Program Sequence
(see below)
Fast Program
Completed
Fast Program Set Command Sequence
(address/data)
Fast Program Command Sequence
(address/data)
Fast Program Reset Command Sequence
(address/data)
555h/AAh
XXXh/A0h
XXXh/90h
2AAh/55h
Program Address/
Program Data
XXXh/F0h
555h/20h
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TC58FVM6(T/B)2A(FT/XB)65
Auto Erase
Start
Auto Erase Command Sequence
(see below)
DATA Polling or Toggle Bit
Auto Erase
Completed
Auto Chip Erase Command Sequence
(address/data)
Auto Block/Auto Multi-Block Erase Command Sequence
(address/data)
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h
555h/80h
555h/80h
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h
555h/10h
Block Address/30h
Block Address/30h
Block Address/30h
Additional address
inputs during
Auto Multi-Block Erase
Note: The above command sequence takes place in Word Mode.
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TC58FVM6(T/B)2A(FT/XB)65
DQ7 DATA Polling
Start
Read Byte (DQ0~DQ7)
Addr. = VA
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
1) : DQ7 must be rechecked even if DQ5 = 1
because DQ7 may change at the same
time as DQ5.
1)
Read Byte (DQ0~DQ7)
Addr. = VA
Yes
DQ7 = Data?
No
Fail
Pass
DQ6 Toggle Bit
Start
Read Byte (DQ0~DQ7)
Addr. = VA
No
DQ6 = Toggle?
Yes
No
DQ5 = 1?
Yes
1) : DQ6 must be rechecked even if DQ5 = 1
because DQ6 may stop toggling at the
same time that DQ5 changes to 1.
1)
Read Byte (DQ0~DQ7)
Addr. = VA
DQ6 = Toggle?
No
Yes
Fail
Pass
VA: Byte address for programming
Any of the addresses within the block being erased during a Block Erase operation
“Don’t care” during a Chip Erase operation
Any address not within the current block during an Erase Suspend operation
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TC58FVM6(T/B)2A(FT/XB)65
Block Protect 1
Start
PLSCNT = 1
Set up Block Address
Addr. = BPA
Wait for 4 µs
OE = A9 = VID, CE = VIL
Wait for 4 µs
WE = VIL
Wait for 100 µs
WE = VIH
PLSCNT = PLSCNT + 1
Wait for 4 µs
OE = VIH
Wait for 4 µs
OE = VIL
Verify Block Protect
No
Data = 01h?
No
Yes
Yes
Protect Another Block?
PLSCNT = 25?
Yes
Device Failed
No
Remove VID from A9
Block Protect
Complete
BPA: Block Address and ID Read Address (A6, A1, A0)
ID Read Address = (0, 1, 0)
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TC58FVM6(T/B)2A(FT/XB)65
Block Protect 2
Start
RESET = VID
Wait for 4 µs
PLSCNT = 1
Block Protect 2
Command First Bus Write Cycle
(XXXH/60H)
Set up Address
Addr. = BPA
Block Protect 2
Command Second Bus Write Cycle
(BPA/60H)
Wait for 100 µs
Block Protect 2
Command Third Bus Write Cycle
(XXXH/40H)
PLSCNT = PLSCNT + 1
Verify Block Protect
No
Data = 01h?
No
Yes
Yes
Protect Another Block?
PLSCNT = 25?
Yes
Remove VID from RESET
No
Remove VID from RESET
Reset Command
Reset Command
Device Failed
Block Protect
Complete
BPA: Block Address and ID Read Address (A6, A1, A0)
ID Read Address = (0, 1, 0)
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TC58FVM6(T/B)2A(FT/XB)65
BLOCK ADDRESS TABLES
(1) TC58FVM6T2A (top boot block)
BLOCK ADDRESS
BANK
#
BLOCK
#
ADDRESS RANGE
BANK ADDRESS
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
BK0
BK1
BYTE MODE
WORD MODE
BA0
L
L
L
L
L
L
L
*
*
*
000000h~00FFFFh
000000h~007FFFh
BA1
L
L
L
L
L
L
H
*
*
*
010000h~01FFFFh
008000h~00FFFFh
BA2
L
L
L
L
L
H
L
*
*
*
020000h~02FFFFh
010000h~017FFFh
BA3
L
L
L
L
L
H
H
*
*
*
030000h~03FFFFh
018000h~01FFFFh
BA4
L
L
L
L
H
L
L
*
*
*
040000h~04FFFFh
020000h~027FFFh
BA5
L
L
L
L
H
L
H
*
*
*
050000h~05FFFFh
028000h~02FFFFh
BA6
L
L
L
L
H
H
L
*
*
*
060000h~06FFFFh
030000h~037FFFh
BA7
L
L
L
L
H
H
H
*
*
*
070000h~07FFFFh
038000h~03FFFFh
BA8
L
L
L
H
L
L
L
*
*
*
080000h~08FFFFh
040000h~047FFFh
BA9
L
L
L
H
L
L
H
*
*
*
090000h~09FFFFh
048000h~04FFFFh
BA10
L
L
L
H
L
H
L
*
*
*
0A0000h~0AFFFFh
050000h~057FFFh
BA11
L
L
L
H
L
H
H
*
*
*
0B0000h~0BFFFFh
058000h~05FFFFh
BA12
L
L
L
H
H
L
L
*
*
*
0C0000h~0CFFFFh
060000h~067FFFh
BA13
L
L
L
H
H
L
H
*
*
*
0D0000h~0DFFFFh
068000h~06FFFFh
BA14
L
L
L
H
H
H
L
*
*
*
0E0000h~0EFFFFh
070000h~077FFFh
BA15
L
L
L
H
H
H
H
*
*
*
0F0000h~0FFFFFh
078000h~07FFFFh
BA16
L
L
H
L
L
L
L
*
*
*
100000h~10FFFFh
080000h~087FFFh
BA17
L
L
H
L
L
L
H
*
*
*
110000h~11FFFFh
088000h~08FFFFh
BA18
L
L
H
L
L
H
L
*
*
*
120000h~12FFFFh
090000h~097FFFh
BA19
L
L
H
L
L
H
H
*
*
*
130000h~13FFFFh
098000h~09FFFFh
BA20
L
L
H
L
H
L
L
*
*
*
140000h~14FFFFh
0A0000h~0A7FFFh
BA21
L
L
H
L
H
L
H
*
*
*
150000h~15FFFFh
0A8000h~0AFFFFh
BA22
L
L
H
L
H
H
L
*
*
*
160000h~16FFFFh
0B0000h~0B7FFFh
BA23
L
L
H
L
H
H
H
*
*
*
170000h~17FFFFh
0B8000h~0BFFFFh
BA24
L
L
H
H
L
L
L
*
*
*
180000h~18FFFFh
0C0000h~0C7FFFh
BA25
L
L
H
H
L
L
H
*
*
*
190000h~19FFFFh
0C8000h~0CFFFFh
BA26
L
L
H
H
L
H
L
*
*
*
1A0000h~1AFFFFh
0D0000h~0D7FFFh
BA27
L
L
H
H
L
H
H
*
*
*
1B0000h~1BFFFFh
0D8000h~0DFFFFh
BA28
L
L
H
H
H
L
L
*
*
*
1C0000h~1CFFFFh
0E0000h~0E7FFFh
BA29
L
L
H
H
H
L
H
*
*
*
1D0000h~1DFFFFh
0E8000h~0EFFFFh
BA30
L
L
H
H
H
H
L
*
*
*
1E0000h~1EFFFFh
0F0000h~0F7FFFh
BA31
L
L
H
H
H
H
H
*
*
*
1F0000h~1FFFFFh
0F8000h~0FFFFFh
2003-01-29
47/61
TC58FVM6(T/B)2A(FT/XB)65
BLOCK ADDRESS
BANK
#
BLOCK
#
ADDRESS RANGE
BANK ADDRESS
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
BK1
BYTE MODE
WORD MODE
BA32
L
H
L
L
L
L
L
*
*
*
200000h~20FFFFh
100000h~107FFFh
BA33
L
H
L
L
L
L
H
*
*
*
210000h~21FFFFh
108000h~10FFFFh
BA34
L
H
L
L
L
H
L
*
*
*
220000h~22FFFFh
110000h~117FFFh
BA35
L
H
L
L
L
H
H
*
*
*
230000h~23FFFFh
118000h~11FFFFh
BA36
L
H
L
L
H
L
L
*
*
*
240000h~24FFFFh
120000h~127FFFh
BA37
L
H
L
L
H
L
H
*
*
*
250000h~25FFFFh
128000h~12FFFFh
BA38
L
H
L
L
H
H
L
*
*
*
260000h~26FFFFh
130000h~137FFFh
BA39
L
H
L
L
H
H
H
*
*
*
270000h~27FFFFh
138000h~13FFFFh
BA40
L
H
L
H
L
L
L
*
*
*
280000h~28FFFFh
140000h~147FFFh
BA41
L
H
L
H
L
L
H
*
*
*
290000h~29FFFFh
148000h~14FFFFh
BA42
L
H
L
H
L
H
L
*
*
*
2A0000h~2AFFFFh
150000h~157FFFh
BA43
L
H
L
H
L
H
H
*
*
*
2B0000h~2BFFFFh
158000h~15FFFFh
BA44
L
H
L
H
H
L
L
*
*
*
2C0000h~2CFFFFh
160000h~167FFFh
BA45
L
H
L
H
H
L
H
*
*
*
2D0000h~2DFFFFh
168000h~16FFFFh
BA46
L
H
L
H
H
H
L
*
*
*
2E0000h~2EFFFFh
170000h~177FFFh
BA47
L
H
L
H
H
H
H
*
*
*
2F0000h~2FFFFFh
178000h~17FFFFh
BA48
L
H
H
L
L
L
L
*
*
*
300000h~30FFFFh
180000h~187FFFh
BA49
L
H
H
L
L
L
H
*
*
*
310000h~31FFFFh
188000h~18FFFFh
BA50
L
H
H
L
L
H
L
*
*
*
320000h~32FFFFh
190000h~197FFFh
BA51
L
H
H
L
L
H
H
*
*
*
330000h~33FFFFh
198000h~19FFFFh
BA52
L
H
H
L
H
L
L
*
*
*
340000h~34FFFFh
1A0000h~1A7FFFh
BA53
L
H
H
L
H
L
H
*
*
*
350000h~35FFFFh
1A8000h~1AFFFFh
BA54
L
H
H
L
H
H
L
*
*
*
360000h~36FFFFh
1B0000h~1B7FFFh
BA55
L
H
H
L
H
H
H
*
*
*
370000h~37FFFFh
1B8000h~1BFFFFh
BA56
L
H
H
H
L
L
L
*
*
*
380000h~38FFFFh
1C0000h~1C7FFFh
BA57
L
H
H
H
L
L
H
*
*
*
390000h~39FFFFh
1C8000h~1CFFFFh
BA58
L
H
H
H
L
H
L
*
*
*
3A0000h~3AFFFFh
1D0000h~1D7FFFh
BA59
L
H
H
H
L
H
H
*
*
*
3B0000h~3BFFFFh
1D8000h~1DFFFFh
BA60
L
H
H
H
H
L
L
*
*
*
3C0000h~3CFFFFh
1E0000h~1E7FFFh
BA61
L
H
H
H
H
L
H
*
*
*
3D0000h~3DFFFFh
1E8000h~1EFFFFh
BA62
L
H
H
H
H
H
L
*
*
*
3E0000h~3EFFFFh
1F0000h~1F7FFFh
BA63
L
H
H
H
H
H
H
*
*
*
3F0000h~3FFFFFh
1F8000h~1FFFFFh
2003-01-29
48/61
TC58FVM6(T/B)2A(FT/XB)65
BLOCK ADDRESS
BANK
#
BLOCK
#
ADDRESS RANGE
BANK ADDRESS
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
BK2
BYTE MODE
WORD MODE
BA64
H
L
L
L
L
L
L
*
*
*
400000h~40FFFFh
200000h~207FFFh
BA65
H
L
L
L
L
L
H
*
*
*
410000h~41FFFFh
208000h~20FFFFh
BA66
H
L
L
L
L
H
L
*
*
*
420000h~42FFFFh
210000h~217FFFh
BA67
H
L
L
L
L
H
H
*
*
*
430000h~43FFFFh
218000h~21FFFFh
BA68
H
L
L
L
H
L
L
*
*
*
440000h~44FFFFh
220000h~227FFFh
BA69
H
L
L
L
H
L
H
*
*
*
450000h~45FFFFh
228000h~22FFFFh
BA70
H
L
L
L
H
H
L
*
*
*
460000h~46FFFFh
230000h~237FFFh
BA71
H
L
L
L
H
H
H
*
*
*
470000h~47FFFFh
238000h~23FFFFh
BA72
H
L
L
H
L
L
L
*
*
*
480000h~48FFFFh
240000h~247FFFh
BA73
H
L
L
H
L
L
H
*
*
*
490000h~49FFFFh
248000h~24FFFFh
BA74
H
L
L
H
L
H
L
*
*
*
4A0000h~4AFFFFh
250000h~257FFFh
BA75
H
L
L
H
L
H
H
*
*
*
4B0000h~4BFFFFh
258000h~25FFFFh
BA76
H
L
L
H
H
L
L
*
*
*
4C0000h~4CFFFFh
260000h~267FFFh
BA77
H
L
L
H
H
L
H
*
*
*
4D0000h~4DFFFFh
268000h~26FFFFh
BA78
H
L
L
H
H
H
L
*
*
*
4E0000h~4EFFFFh
270000h~277FFFh
BA79
H
L
L
H
H
H
H
*
*
*
4F0000h~4FFFFFh
278000h~27FFFFh
BA80
H
L
H
L
L
L
L
*
*
*
500000h~50FFFFh
280000h~287FFFh
BA81
H
L
H
L
L
L
H
*
*
*
510000h~51FFFFh
288000h~28FFFFh
BA82
H
L
H
L
L
H
L
*
*
*
520000h~52FFFFh
290000h~297FFFh
BA83
H
L
H
L
L
H
H
*
*
*
530000h~53FFFFh
298000h~29FFFFh
BA84
H
L
H
L
H
L
L
*
*
*
540000h~54FFFFh
2A0000h~2A7FFFh
BA85
H
L
H
L
H
L
H
*
*
*
550000h~55FFFFh
2A8000h~2AFFFFh
BA86
H
L
H
L
H
H
L
*
*
*
560000h~56FFFFh
2B0000h~2B7FFFh
BA87
H
L
H
L
H
H
H
*
*
*
570000h~57FFFFh
2B8000h~2BFFFFh
BA88
H
L
H
H
L
L
L
*
*
*
580000h~58FFFFh
2C0000h~2C7FFFh
BA89
H
L
H
H
L
L
H
*
*
*
590000h~59FFFFh
2C8000h~2CFFFFh
BA90
H
L
H
H
L
H
L
*
*
*
5A0000h~5AFFFFh
2D0000h~2D7FFFh
BA91
H
L
H
H
L
H
H
*
*
*
5B0000h~5BFFFFh
2D8000h~2DFFFFh
BA92
H
L
H
H
H
L
L
*
*
*
5C0000h~5CFFFFh
2E0000h~2E7FFFh
BA93
H
L
H
H
H
L
H
*
*
*
5D0000h~5DFFFFh
2E8000h~2EFFFFh
BA94
H
L
H
H
H
H
L
*
*
*
5E0000h~5EFFFFh
2F0000h~2F7FFFh
BA95
H
L
H
H
H
H
H
*
*
*
5F0000h~5FFFFFh
2F8000h~2FFFFFh
2003-01-29
49/61
TC58FVM6(T/B)2A(FT/XB)65
BLOCK ADDRESS
BANK
#
BLOCK
#
ADDRESS RANGE
BANK ADDRESS
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
BK2
BK3
BYTE MODE
WORD MODE
BA96
H
H
L
L
L
L
L
*
*
*
600000h~60FFFFh
300000h~307FFFh
BA97
H
H
L
L
L
L
H
*
*
*
610000h~61FFFFh
308000h~30FFFFh
BA98
H
H
L
L
L
H
L
*
*
*
620000h~62FFFFh
310000h~317FFFh
BA99
H
H
L
L
L
H
H
*
*
*
630000h~63FFFFh
318000h~31FFFFh
BA100
H
H
L
L
H
L
L
*
*
*
640000h~64FFFFh
320000h~327FFFh
BA101
H
H
L
L
H
L
H
*
*
*
650000h~65FFFFh
328000h~32FFFFh
BA102
H
H
L
L
H
H
L
*
*
*
660000h~66FFFFh
330000h~337FFFh
BA103
H
H
L
L
H
H
H
*
*
*
670000h~67FFFFh
338000h~33FFFFh
BA104
H
H
L
H
L
L
L
*
*
*
680000h~68FFFFh
340000h~347FFFh
BA105
H
H
L
H
L
L
H
*
*
*
690000h~69FFFFh
348000h~34FFFFh
BA106
H
H
L
H
L
H
L
*
*
*
6A0000h~6AFFFFh
350000h~357FFFh
BA107
H
H
L
H
L
H
H
*
*
*
6B0000h~6BFFFFh
358000h~35FFFFh
BA108
H
H
L
H
H
L
L
*
*
*
6C0000h~6CFFFFh
360000h~367FFFh
BA109
H
H
L
H
H
L
H
*
*
*
6D0000h~6DFFFFh
368000h~36FFFFh
BA110
H
H
L
H
H
H
L
*
*
*
6E0000h~6EFFFFh
370000h~377FFFh
BA111
H
H
L
H
H
H
H
*
*
*
6F0000h~6FFFFFh
378000h~37FFFFh
BA112
H
H
H
L
L
L
L
*
*
*
700000h~70FFFFh
380000h~387FFFh
BA113
H
H
H
L
L
L
H
*
*
*
710000h~71FFFFh
388000h~38FFFFh
BA114
H
H
H
L
L
H
L
*
*
*
720000h~72FFFFh
390000h~397FFFh
BA115
H
H
H
L
L
H
H
*
*
*
730000h~73FFFFh
398000h~39FFFFh
BA116
H
H
H
L
H
L
L
*
*
*
740000h~74FFFFh
3A0000h~3A7FFFh
BA117
H
H
H
L
H
L
H
*
*
*
770000h~75FFFFh
3A8000h~3AFFFFh
BA118
H
H
H
L
H
H
L
*
*
*
760000h~76FFFFh
3B0000h~3B7FFFh
BA119
H
H
H
L
H
H
H
*
*
*
770000h~77FFFFh
3B8000h~3BFFFFh
BA120
H
H
H
H
L
L
L
*
*
*
780000h~78FFFFh
3C0000h~3C7FFFh
BA121
H
H
H
H
L
L
H
*
*
*
790000h~79FFFFh
3C8000h~3CFFFFh
BA122
H
H
H
H
L
H
L
*
*
*
7A0000h~7AFFFFh
3D0000h~3D7FFFh
BA123
H
H
H
H
L
H
H
*
*
*
7B0000h~7BFFFFh
3D8000h~3DFFFFh
BA124
H
H
H
H
H
L
L
*
*
*
7C0000h~7CFFFFh
3E0000h~3E7FFFh
BA125
H
H
H
H
H
L
H
*
*
*
7D0000h~7DFFFFh
3E8000h~3EFFFFh
BA126
H
H
H
H
H
H
L
*
*
*
7E0000h~7EFFFFh
3F0000h~3F7FFFh
2003-01-29
50/61
TC58FVM6(T/B)2A(FT/XB)65
BLOCK ADDRESS
BANK
#
BLOCK
#
ADDRESS RANGE
BANK ADDRESS
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
BK3
BYTE MODE
WORD MODE
BA127
H
H
H
H
Ｈ
H
Ｈ
L
L
L
7F0000h~7F1FFFh
3F8000h~3F8FFFh
BA128
H
H
H
H
Ｈ
H
Ｈ
L
L
Ｈ
7F2000h~7F3FFFh
3F9000h~3F9FFFh
BA129
H
H
H
H
H
H
H
L
H
L
7F4000h~7F5FFFh
3FA000h~3FAFFFh
BA130
H
H
H
H
H
H
H
L
H
H
7F6000h~7F7FFFh
3FB000h~3FBFFFh
BA131
H
H
H
H
H
H
H
H
L
L
7F8000h~7F9FFFh
3FC000h~3FCFFFh
BA132
H
H
H
H
H
H
H
H
L
H
7FA000h~7FBFFFh
3FD000h~3FDFFFh
BA133
H
H
H
H
H
H
H
H
H
L
7FC000h~7FDFFFh
3FE000h~3FEFFFh
BA134
H
H
H
H
H
H
H
H
H
H
7FE000h~7FFFFFh
3FF000h~3FFFFFh
2003-01-29
51/61
TC58FVM6(T/B)2A(FT/XB)65
(2) TC58FVM6B2A (bottom boot block)
BLOCK ADDRESS
BANK
#
BLOCK
#
ADDRESS RANGE
BANK ADDRESS
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
BK0
BK1
BYTE MODE
WORD MODE
BA0
L
L
L
L
L
L
L
L
L
L
000000h~001FFFh
000000h~000FFFh
BA1
L
L
L
L
L
L
L
L
L
H
002000h~003FFFh
001000h~001FFFh
BA2
L
L
L
L
L
L
L
L
H
L
004000h~005FFFh
002000h~002FFFh
BA3
L
L
L
L
L
L
L
L
H
H
006000h~007FFFh
003000h~003FFFh
BA4
L
L
L
L
L
L
L
H
L
L
008000h~009FFFh
004000h~004FFFh
BA5
L
L
L
L
L
L
L
H
L
H
00A000h~00BFFFh
005000h~005FFFh
BA6
L
L
L
L
L
L
L
H
H
L
00C000h~00DFFFh
006000h~006FFFh
BA7
L
L
L
L
L
L
L
H
H
H
00E000h~00FFFFh
007000h~007FFFh
BA8
L
L
L
L
L
L
H
*
*
*
010000h~01FFFFh
008000h~00FFFFh
BA9
L
L
L
L
L
H
L
*
*
*
020000h~02FFFFh
010000h~017FFFh
BA10
L
L
L
L
L
H
H
*
*
*
030000h~03FFFFh
018000h~01FFFFh
BA11
L
L
L
L
H
L
L
*
*
*
040000h~04FFFFh
020000h~027FFFh
BA12
L
L
L
L
H
L
H
*
*
*
050000h~05FFFFh
028000h~02FFFFh
BA13
L
L
L
L
H
H
L
*
*
*
060000h~06FFFFh
030000h~037FFFh
BA14
L
L
L
L
H
H
H
*
*
*
070000h~07FFFFh
038000h~03FFFFh
BA15
L
L
L
H
L
L
L
*
*
*
080000h~08FFFFh
040000h~047FFFh
BA16
L
L
L
H
L
L
H
*
*
*
090000h~09FFFFh
048000h~04FFFFh
BA17
L
L
L
H
L
H
L
*
*
*
0A0000h~0AFFFFh
050000h~057FFFh
BA18
L
L
L
H
L
H
H
*
*
*
0B0000h~0BFFFFh
058000h~05FFFFh
BA19
L
L
L
H
H
L
L
*
*
*
0C0000h~0CFFFFh
060000h~067FFFh
BA20
L
L
L
H
H
L
H
*
*
*
0D0000h~0DFFFFh
068000h~06FFFFh
BA21
L
L
L
H
H
H
L
*
*
*
0E0000h~0EFFFFh
070000h~077FFFh
BA22
L
L
L
H
H
H
H
*
*
*
0F0000h~0FFFFFh
078000h~07FFFFh
BA23
L
L
H
L
L
L
L
*
*
*
100000h~10FFFFh
080000h~087FFFh
BA24
L
L
H
L
L
L
H
*
*
*
110000h~11FFFFh
088000h~08FFFFh
BA25
L
L
H
L
L
H
L
*
*
*
120000h~12FFFFh
090000h~097FFFh
BA26
L
L
H
L
L
H
H
*
*
*
130000h~13FFFFh
098000h~09FFFFh
BA27
L
L
H
L
H
L
L
*
*
*
140000h~14FFFFh
0A0000h~0A7FFFh
BA28
L
L
H
L
H
L
H
*
*
*
150000h~15FFFFh
0A8000h~0AFFFFh
BA29
L
L
H
L
H
H
L
*
*
*
160000h~16FFFFh
0B0000h~0B7FFFh
BA30
L
L
H
L
H
H
H
*
*
*
170000h~17FFFFh
0B8000h~0BFFFFh
2003-01-29
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TC58FVM6(T/B)2A(FT/XB)65
BLOCK ADDRESS
BANK
#
BLOCK
#
ADDRESS RANGE
BANK ADDRESS
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
BK1
BYTE MODE
WORD MODE
BA31
L
L
H
H
L
L
L
*
*
*
180000h~18FFFFh
0C0000h~0C7FFFh
BA32
L
L
H
H
L
L
H
*
*
*
190000h~19FFFFh
0C8000h~0CFFFFh
BA33
L
L
H
H
L
H
L
*
*
*
1A0000h~1AFFFFh
0D0000h~0D7FFFh
BA34
L
L
H
H
L
H
H
*
*
*
1B0000h~1BFFFFh
0D8000h~0DFFFFh
BA35
L
L
H
H
H
L
L
*
*
*
1C0000h~1CFFFFh
0E0000h~0E7FFFh
BA36
L
L
H
H
H
L
H
*
*
*
1D0000h~1DFFFFh
0E8000h~0EFFFFh
BA37
L
L
H
H
H
H
L
*
*
*
1E0000h~1EFFFFh
0F0000h~0F7FFFh
BA38
L
L
H
H
H
H
H
*
*
*
1F0000h~1FFFFFh
0F8000h~0FFFFFh
BA39
L
H
L
L
L
L
L
*
*
*
200000h~20FFFFh
100000h~107FFFh
BA40
L
H
L
L
L
L
H
*
*
*
210000h~21FFFFh
108000h~10FFFFh
BA41
L
H
L
L
L
H
L
*
*
*
220000h~22FFFFh
110000h~117FFFh
BA42
L
H
L
L
L
H
H
*
*
*
230000h~23FFFFh
118000h~11FFFFh
BA43
L
H
L
L
H
L
L
*
*
*
240000h~24FFFFh
120000h~127FFFh
BA44
L
H
L
L
H
L
H
*
*
*
250000h~25FFFFh
128000h~12FFFFh
BA45
L
H
L
L
H
H
L
*
*
*
260000h~26FFFFh
130000h~137FFFh
BA46
L
H
L
L
H
H
H
*
*
*
270000h~27FFFFh
138000h~13FFFFh
BA47
L
H
L
H
L
L
L
*
*
*
280000h~28FFFFh
140000h~147FFFh
BA48
L
H
L
H
L
L
H
*
*
*
290000h~29FFFFh
148000h~14FFFFh
BA49
L
H
L
H
L
H
L
*
*
*
2A0000h~2AFFFFh
150000h~157FFFh
BA50
L
H
L
H
L
H
H
*
*
*
2B0000h~2BFFFFh
158000h~15FFFFh
BA51
L
H
L
H
H
L
L
*
*
*
2C0000h~2CFFFFh
160000h~167FFFh
BA52
L
H
L
H
H
L
H
*
*
*
2D0000h~2DFFFFh
168000h~16FFFFh
BA53
L
H
L
H
H
H
L
*
*
*
2E0000h~2EFFFFh
170000h~177FFFh
BA54
L
H
L
H
H
H
H
*
*
*
2F0000h~2FFFFFh
178000h~17FFFFh
BA55
L
H
H
L
L
L
L
*
*
*
300000h~30FFFFh
180000h~187FFFh
BA56
L
H
H
L
L
L
H
*
*
*
310000h~31FFFFh
188000h~18FFFFh
BA57
L
H
H
L
L
H
L
*
*
*
320000h~32FFFFh
190000h~197FFFh
BA58
L
H
H
L
L
H
H
*
*
*
330000h~33FFFFh
198000h~19FFFFh
BA59
L
H
H
L
H
L
L
*
*
*
340000h~34FFFFh
1A0000h~1A7FFFh
BA60
L
H
H
L
H
L
H
*
*
*
350000h~35FFFFh
1A8000h~1AFFFFh
BA61
L
H
H
L
H
H
L
*
*
*
360000h~36FFFFh
1B0000h~1B7FFFh
BA62
L
H
H
L
H
H
H
*
*
*
370000h~37FFFFh
1B8000h~1BFFFFh
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TC58FVM6(T/B)2A(FT/XB)65
BLOCK ADDRESS
BANK
#
BLOCK
#
ADDRESS RANGE
BANK ADDRESS
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
BK1
BK2
BYTE MODE
WORD MODE
BA63
L
H
H
H
L
L
L
*
*
*
380000h~38FFFFh
1C0000h~1C7FFFh
BA64
L
H
H
H
L
L
H
*
*
*
390000h~39FFFFh
1C8000h~1CFFFFh
BA65
L
H
H
H
L
H
L
*
*
*
3A0000h~3AFFFFh
1D0000h~1D7FFFh
BA66
L
H
H
H
L
H
H
*
*
*
3B0000h~3BFFFFh
1D8000h~1DFFFFh
BA67
L
H
H
H
H
L
L
*
*
*
3C0000h~3CFFFFh
1E0000h~1E7FFFh
BA68
L
H
H
H
H
L
H
*
*
*
3D0000h~3DFFFFh
1E8000h~1EFFFFh
BA69
L
H
H
H
H
H
L
*
*
*
3E0000h~3EFFFFh
1F0000h~1F7FFFh
BA70
L
H
H
H
H
H
H
*
*
*
3F0000h~3FFFFFh
1F8000h~1FFFFFh
BA71
H
L
L
L
L
L
L
*
*
*
400000h~40FFFFh
200000h~207FFFh
BA72
H
L
L
L
L
L
H
*
*
*
410000h~41FFFFh
208000h~20FFFFh
BA73
H
L
L
L
L
H
L
*
*
*
420000h~42FFFFh
210000h~217FFFh
BA74
H
L
L
L
L
H
H
*
*
*
430000h~43FFFFh
218000h~21FFFFh
BA75
H
L
L
L
H
L
L
*
*
*
440000h~44FFFFh
220000h~227FFFh
BA76
H
L
L
L
H
L
H
*
*
*
450000h~45FFFFh
228000h~22FFFFh
BA77
H
L
L
L
H
H
L
*
*
*
460000h~46FFFFh
230000h~237FFFh
BA78
H
L
L
L
H
H
H
*
*
*
470000h~47FFFFh
238000h~23FFFFh
BA79
H
L
L
H
L
L
L
*
*
*
480000h~48FFFFh
240000h~247FFFh
BA80
H
L
L
H
L
L
H
*
*
*
490000h~49FFFFh
248000h~24FFFFh
BA81
H
L
L
H
L
H
L
*
*
*
4A0000h~4AFFFFh
250000h~257FFFh
BA82
H
L
L
H
L
H
H
*
*
*
4B0000h~4BFFFFh
258000h~25FFFFh
BA83
H
L
L
H
H
L
L
*
*
*
4C0000h~4CFFFFh
260000h~267FFFh
BA84
H
L
L
H
H
L
H
*
*
*
4D0000h~4DFFFFh
268000h~26FFFFh
BA85
H
L
L
H
H
H
L
*
*
*
4E0000h~4EFFFFh
270000h~277FFFh
BA86
H
L
L
H
H
H
H
*
*
*
4F0000h~4FFFFFh
278000h~27FFFFh
BA87
H
L
H
L
L
L
L
*
*
*
500000h~50FFFFh
280000h~287FFFh
BA88
H
L
H
L
L
L
H
*
*
*
510000h~51FFFFh
288000h~28FFFFh
BA89
H
L
H
L
L
H
L
*
*
*
520000h~52FFFFh
290000h~297FFFh
BA90
H
L
H
L
L
H
H
*
*
*
530000h~53FFFFh
298000h~29FFFFh
BA91
H
L
H
L
H
L
L
*
*
*
540000h~54FFFFh
2A0000h~2A7FFFh
BA92
H
L
H
L
H
L
H
*
*
*
550000h~55FFFFh
2A8000h~2AFFFFh
BA93
H
L
H
L
H
H
L
*
*
*
560000h~56FFFFh
2B0000h~2B7FFFh
BA94
H
L
H
L
H
H
H
*
*
*
570000h~57FFFFh
2B8000h~2BFFFFh
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TC58FVM6(T/B)2A(FT/XB)65
BLOCK ADDRESS
BANK
#
BLOCK
#
ADDRESS RANGE
BANK ADDRESS
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
BK2
BK3
BYTE MODE
WORD MODE
BA95
H
L
H
H
L
L
L
*
*
*
580000h~58FFFFh
2C0000h~2C7FFFh
BA96
H
L
H
H
L
L
H
*
*
*
590000h~59FFFFh
2C8000h~2CFFFFh
BA97
H
L
H
H
L
H
L
*
*
*
5A0000h~5AFFFFh
2D0000h~2D7FFFh
BA98
H
L
H
H
L
H
H
*
*
*
5B0000h~5BFFFFh
2D8000h~2DFFFFh
BA99
H
L
H
H
H
L
L
*
*
*
5C0000h~5CFFFFh
2E0000h~2E7FFFh
BA100
H
L
H
H
H
L
H
*
*
*
5D0000h~5DFFFFh
2E8000h~2EFFFFh
BA101
H
L
H
H
H
H
L
*
*
*
5E0000h~5EFFFFh
2F0000h~2F7FFFh
BA102
H
L
H
H
H
H
H
*
*
*
5F0000h~5FFFFFh
2F8000h~2FFFFFh
BA103
H
H
L
L
L
L
L
*
*
*
600000h~60FFFFh
300000h~307FFFh
BA104
H
H
L
L
L
L
H
*
*
*
610000h~61FFFFh
308000h~30FFFFh
BA105
H
H
L
L
L
H
L
*
*
*
620000h~62FFFFh
310000h~317FFFh
BA106
H
H
L
L
L
H
H
*
*
*
630000h~63FFFFh
318000h~31FFFFh
BA107
H
H
L
L
H
L
L
*
*
*
640000h~64FFFFh
320000h~327FFFh
BA108
H
H
L
L
H
L
H
*
*
*
650000h~65FFFFh
328000h~32FFFFh
BA109
H
H
L
L
H
H
L
*
*
*
660000h~66FFFFh
330000h~337FFFh
BA110
H
H
L
L
H
H
H
*
*
*
670000h~67FFFFh
338000h~33FFFFh
BA111
H
H
L
H
L
L
L
*
*
*
680000h~68FFFFh
340000h~347FFFh
BA112
H
H
L
H
L
L
H
*
*
*
690000h~69FFFFh
348000h~34FFFFh
BA113
H
H
L
H
L
H
L
*
*
*
6A0000h~6AFFFFh
350000h~357FFFh
BA114
H
H
L
H
L
H
H
*
*
*
6B0000h~6BFFFFh
358000h~35FFFFh
BA115
H
H
L
H
H
L
L
*
*
*
6C0000h~6CFFFFh
360000h~367FFFh
BA116
H
H
L
H
H
L
H
*
*
*
6D0000h~6DFFFFh
368000h~36FFFFh
BA117
H
H
L
H
H
H
L
*
*
*
6E0000h~6EFFFFh
370000h~377FFFh
BA118
H
H
L
H
H
H
H
*
*
*
6F0000h~6FFFFFh
378000h~37FFFFh
BA119
H
H
H
L
L
L
L
*
*
*
700000h~70FFFFh
380000h~387FFFh
BA120
H
H
H
L
L
L
H
*
*
*
710000h~71FFFFh
388000h~38FFFFh
BA121
H
H
H
L
L
H
L
*
*
*
720000h~72FFFFh
390000h~397FFFh
BA122
H
H
H
L
L
H
H
*
*
*
730000h~73FFFFh
398000h~39FFFFh
BA123
H
H
H
L
H
L
L
*
*
*
740000h~74FFFFh
3A0000h~3A7FFFh
BA124
H
H
H
L
H
L
H
*
*
*
750000h~75FFFFh
3A8000h~3AFFFFh
BA125
H
H
H
L
H
H
L
*
*
*
760000h~76FFFFh
3B0000h~3B7FFFh
BA126
H
H
H
L
H
H
H
*
*
*
770000h~77FFFFh
3B8000h~3BFFFFh
2003-01-29
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TC58FVM6(T/B)2A(FT/XB)65
BLOCK ADDRESS
BANK
#
BLOCK
#
ADDRESS RANGE
BANK ADDRESS
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
BK3
BYTE MODE
WORD MODE
BA127
H
H
H
H
L
L
L
*
*
*
780000h~78FFFFh
3C0000h~3C7FFFh
BA128
H
H
H
H
L
L
H
*
*
*
790000h~79FFFFh
3C8000h~3CFFFFh
BA129
H
H
H
H
L
H
L
*
*
*
7A0000h~7AFFFFh
3D0000h~3D7FFFh
BA130
H
H
H
H
L
H
H
*
*
*
7B0000h~7BFFFFh
3D8000h~3DFFFFh
BA131
H
H
H
H
H
L
L
*
*
*
7C0000h~7CFFFFh
3E0000h~3E7FFFh
BA132
H
H
H
H
H
L
H
*
*
*
7D0000h~7DFFFFh
3E8000h~3EFFFFh
BA133
H
H
H
H
H
H
L
*
*
*
7E0000h~7EFFFFh
3F0000h~3F7FFFh
BA134
H
H
H
H
H
H
H
*
*
*
7F0000h~7FFFFFh
3F8000h~3FFFFFh
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TC58FVM6(T/B)2A(FT/XB)65
BLOCK SIZE TABLE
(1) TC58FVM6T2A (top boot block)
BLOCK
#
BLOCK SIZE
BYTE MODE
BYTE MODE
BA0~BA15
64 Kbytes
32 Kwords
BA16~BA63
64 Kbytes
BA64~BA111
BANK
#
BANK SIZE
BLOCK COUNT
BYTE MODE
WORD MODE
BK0
1024 Kbytes
512 Kwords
16
32 Kwords
BK1
3072 Kbytes
1536 Kwords
48
64 Kbytes
32 Kwords
BK2
3072 Kbytes
1536 Kwords
48
BA112~BA126
64 Kbytes
32 Kwords
BK3
960 Kbytes
480 Kwords
15
BA127~BA134
8 Kbytes
4 Kwords
BK3
64 Kbytes
32 Kwords
8
(2) TC58FVM6B2A (bottom boot block)
BLOCK
#
BLOCK SIZE
BANK
#
BANK SIZE
BLOCK COUNT
BYTE MODE
WORD MODE
BK0
64 Kbytes
32 Kbytes
8
32 Kwords
BK0
960 Kbytes
480 Kwords
15
64 Kbytes
32 Kwords
BK1
3072 Kbytes
1536 Kwords
48
BA71~BA118
64 Kbytes
32 Kwords
BK2
3072 Kbytes
1536 Kwords
48
BA119~BA134
64 Kbytes
32 Kwords
BK3
1024 Kbytes
512 Kwords
16
BYTE MODE
WORD MODE
BA0~BA7
8 Kbytes
4 Kwords
BA8~BA22
64 Kbytes
BA23~BA70
2003-01-29
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TC58FVM6(T/B)2A(FT/XB)65
PACKAGE DIMENSIONS
Unit: mm
2003-01-29
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TC58FVM6(T/B)2A(FT/XB)65
PACKAGE DIMENSIONS
Unit: mm
Ball side
2003-01-29
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TC58FVM6(T/B)2A(FT/XB)65
Revision History
Date
Rev.
2002-03-14
1.00
Original version
2002-06-21
1.01
P.6
P.15
P.23
P.25
2002-07-31
1.02
P.17 Added explanation of DATA polling in case of page program operation.
P.20 Added VID/VACC comments.
2002-08-07
1.03
P21 Added IDDO8 Spec
P23 Added tBEH (Erase Hold Time) Spec
2002-08-07
1.04
P21 Added DC Typical Value
2002-10-17
1.05
Added FBGA package.
Added Ordering information.
2002-10-24
1.07
Generalize
1.08
Added the PIN Capacitance.
Added the Block protect 2 at mode selection.
Added a part of comment (CMD ID-READ).
Modified the comment of Hidden ROM Area.
Modified the absolute maximum range of Power Dissipation.
Deleted the spec of tAHW .
Modified the block address table.
Annotated Absolute Maximum Ratings.
Deleted annotation of Recommended DC operating conditions.
2003-01-29
Description
Corrected bank addresses.
Corrected CFI CODE (31H).
Changed tSUSP Spec.
Added timing diagram of read after command input.
2003-01-29
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TC58FVM6(T/B)2A(FT/XB)65
RESTRICTIONS ON PRODUCT USE
000707EBA
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
• The information contained herein is subject to change without notice.
2003-01-29
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