TC90A44P,45P/F TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC90A44P,TC90A45P,TC90A45F NTSC 2-LINE DIGITAL Y / C SEPARATION IC The TC90A44P, TC90A45P / F separates luminance (Y) and chrominance (C) signals from NTSC system composite video signal by using 2 horizontal (H) lines separation. The Y / C separation unit for TV and VCR set is able to assembled at low cost, because it requires few external parts and no adjustment. FEATURES · TV system : NTSC · PLL4 × multiplication circuit · sync. tip clamping circuit · Internal 8 bit A / D converter · Internal 8 bit D / A converters (2 ch.) · 1 H line memory · Dynamic comb filter · Color killer mode (Y / C separation OFF) · DIP16 / SOP16 package · 5 V single power supply Weight DIP16-P-300-2.54A : 1.00 g (Typ.) SOP16-P-300-1.27 : 0.18 g (Typ.) 000707EBA1 · TOSHIBA is continually working to improve the quality and reliability of its products. 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Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. · The products described in this document are subject to the foreign exchange and foreign trade laws. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 2001-01-16 1/11 TC90A44P,45P/F TC90A44P BLOCK DIAGRAM TC90A45P / F BLOCK DIAGRAM TERMINAL CONNECTION DIAGRAM 2001-01-16 2/11 TC90A44P,45P/F TERMINAL FUNCTION PIN No. NAME 1 AVSS I/O INTERFACE CIRCUIT Ground for analog components. − — VRB ADC bias lower limit reference voltage. This defaults internally to approximately 2.25 V, so this pin should normally be conected to ground (AVSS) through a 0.01 µF capacitor. − 3 VRT ADC bias higher limit reference voltage. This defaults internally to approximately 2.8 V, so this pin should normally be conected to ground (AVSS) through a 0.01 µF capacitor. − 4 ADIN Composite video signal input. I 5 BIAS1 ADC bias voltage. This defaults internally to approximately 1.3 V, so this pin should normally be conected to ground (AVSS) through a 0.01 µF capacitor. − 6 TEST Test terminal. Normally connected to ground (DVSS). − 7 KILLER This pin is switch for color killer circuit. H : For B / W signal, Y / C separation OFF. L : Normal Y / C separation I 2 FUNCTION 2001-01-16 3/11 TC90A44P,45P/F PIN No. NAME FUNCTION I/O INTERFACE CIRCUIT 8 DVDD Power supply for digital components (+5 V). − − 9 DVSS Ground for digital components. − − 10 CKIN Clock input. After applying capacitor for DC cut, input a color-burst-synchronized fSC clock signal to this pin. I 11 VFIL Connect a VCO filter to this pin. − − 12 BIAS3 DAC bias voltage. This defaults internally to approximately 3.4 V, so this pin should normally be conected to ground (AVSS) through a 0.01 µF capacitor. 13 COUT Chrominance signal output. O 14 BIAS2 DAC bias voltage. This defaults internally to approximately 1.7 V, so this pin should normally be conected to ground (AVSS) through a 0.01 µF capacitor. − 15 YOUT Luminance signal output. O 16 AVDD Power supply for analog components (+5 V) − − 2001-01-16 4/11 TC90A44P,45P/F FUNCTION BLOCK DESCRIPTIONS (1) Input clamp (CLAMP) This is sync tip clamp circuit for composite signal. This circuit makes feedback so that the min. data after A / D converter at Y / C separation equal to internal DC bias level. (2) A / D converter (ADC) This is high speed series-parallel 8 bit A / D converter (Dynamic Range: 1.0V). Recommendable Input level is 0.75 Vp-p (Sync tip~white 100%). (3) Line memory This block is DRAM line memory for 1 H delay. (4) Band-pass filter (BPF) This filter extracts the signal of chrominance band from composite video signal. The center frequency is fsc. (5) Dynamic comb filter (DCF) This block is logical comb filter to extract the chrominance signal. Filtering logic applies a correlation of two lines to reduce color dot crawl and cross color. (6) Color killer circuit (KILLER) This block is applied for black and white (B / W) signal regardless of have color burst or no color burts. When pin 10 (KILLER) is “H ”, logic stop Y / C separation and output composite video signal from pin 14 (YOUT). (7) PLL (4 times multiply clock generator) This block is 4 times multiplier and makes 4fsc as system clock. This block supplies system clock (4fsc) to each block via buffer and generates timing signal for memories. (8) D / A converter (DAC) This is high speed 8 bit D / A converter. Y output level is 1.73 Vp-p (Typ.). C output level is 437 mVp-p (Typ.). (Input condition is 0.75Vp-p) 2001-01-16 5/11 TC90A44P,45P/F MAXIMUM RATINGS (Ta ＝ 25°C) CHARACTERISTIC SYMBOL RATING UNIT Power Supply Voltage VDD VSS~VSS + 6.5 V Input Voltage VIN −0.3~VDD + 0.3 V PD (Note) 600 Tstg −55~125 TC90A44P/45P Power Dissipation TC90A45F Storage Temperature 440 mW °C (Note) : Ta = 70°C RECOMMENDED OPERATING CONDITION CHARACTERISTIC SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT Power Supply Voltage VDD − 4.75 5.00 5.25 V Input Voltage VIN − 0 − VDD V Operating Temperature Topr − −10 − 70 °C ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS (Ta = 25°C, VDD = 5 V) SYMBOL TEST CIRCUIT Power Supply Voltage VDD Supply Current IDD CHARACTERISTIC MIN. TYP. MAX. UNIT 1 4.75 5.00 5.25 V 1 45 60 75 mA 2.55 2.70 2.85 3.70 3.85 4.00 2.15 2.25 2.35 2.7 2.8 2.9 1.9 2.0 2.1 1.0 1.3 1.7 BIAS2 1.2 1.7 2.1 BIAS3 3.0 3.4 4.0 VFIL 1.2 1.9 3.0 CKIN 1.8 2.3 2.8 YOUT (sync tip) Output Voltage Level COUT (center) TEST CONDITION 1 V VRB VRT CLOCK = 3.579545 MHz ADIN (sync tip) BIAS1 Terminal Voltage Level Input Voltage VIN = 0.75 Vp-p 1 V High Level VIH 1 4 − − V Low Level VIL 1 − − 1 V 2001-01-16 6/11 TC90A44P,45P/F AC CHARACTERISTICS (1)Y output (Ta = 25°C, VDD = 5 V, input clock : 3.579545 MHz 0.4 Vp-p, S1 = 1) CHARACTERISTICS SYMBOL TEST CIRCUIT TEST CONDITION Input Level VIN 1 0~140 IRE Low Frequency Gain GV 1 S2 = 1, S3 = 1, S4 = 2 VIN = 15.73426 kHz, 0.75 Vp-p, Vdc = 2.5 V Frequency Response Comb Characteristics f2 / f1 MTF1 f4 / f1 MTF2 f2 / f3 COMBY 1 S2 = 1, S3 = 1, S4 = 2 VIN = 0.75 Vp-p, Vdc = 2.5 V 1 MIN. TYP. MAX. UNIT − 0.75 − Vp-p 6.8 7.2 7.7 dB −0.8 −1.0 −2.0 −1.5 −2.0 −3.0 − −46 −40 dB 250 400 700 Ω dB S2 = 2, S4 = 2 VIN = 15.73426 kHz, 0.75 Vp-p, Vdc = 2.5 V Output Impedance Zo 1 Zo = V1 - V2 ´ 400 V2 V1 : S3 = 1, V2 : S3 = 2 (Note) : f1 = fH = 15.73426 kHz, f2 = fsc = 3.579545 MHz, f3 = fsc + 1 / 2fH = 3.587412 MHz, f4 = 1 / 3 (4fsc) = 4.772727 MHz CONDITION OF INPUT SIGNAL 2001-01-16 7/11 TC90A44P,45P/F (2)C output (Ta = 25°C, VDD = 5 V, input clock : 3.579545MHz 0.4 Vp-p, S1 = 2) CHARACTERISTICS Gain SYMBOL CV BPF Characteristics Comb Characteristics TEST CIRCUIT 1 S2 = 1, S3 = 1, S4 = 1 VIN = 0.75 Vp-p 1 S2 = 2, S3 = 1, S4 = 2 VIN = 0.75 Vp-p, Vdc = 2.5 V (fsc - 503496 Hz) − (fsc) TC90A44P BWCW TC90A45P / F TC90A44P COMBC S2 = 1, S3 = 1, S4 = 2 VIN = 0.75 Vp-p, Vdc = 2.5 V 1 TC90A45P / F Differential Gain DG Differential Phase DP TEST CONDITION S2 = 1, S3 = 1, S4 = 1 Modulated lamp signal 140 IRE : 0.75 V 1 MIN. TYP. MAX. UNIT 5.7 6.2 6.7 dB −2.5 −1.9 −1.5 dB −1.5 −1.3 −1.0 − −38 −35 − −46 −40 0 2 5 % 0 2 5 ° 250 400 700 Ω TYP. MAX. UNIT dB S2 = 2, S4 = 2 VIN = 15.73426 kHz, 0.75 Vp-p, Vdc = 2.5 V Output Impedance Zo 1 Zo = V1 - V2 ´ 400 V2 V1 : S3 = 1, V2 : S3 = 2 (3)PLL circuit characteristics CHARACTERISTICS Pull-In Frequency Range Input Amplitude (fsc Components) SYMBOL TEST CIRCUIT TEST CONDITION fck 1 − 3.5 3.6 3.7 MHz Vck 1 − 0.35 0.5 − Vp-p MIN. 2001-01-16 8/11 TC90A44P,45P/F TEST CIRCUIT 1 APPLICATION CIRCUIT 2001-01-16 9/11 TC90A44P,45P/F PACKAGE DIMENSIONS DIP16-P-300-2.54A Unit : mm Weight : 1.00 g (Typ.) 2001-01-16 10/11 TC90A44P,45P/F PACKAGE DIMENSIONS SOP16-P-300-1.27 Unit : mm Weight : 0.18 g (Typ.) 2001-01-16 11/11