TOSHIBA TC90A67F

TC90A67F
Preliminary
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC90A67F
Single Chip Picture-in-Picture IC (PAL/NTSC)
TC90A67F is a Picture-in-Picture (PIP) IC including a PIP
controller and a PAL/NTSC decoder function on a chip.
TC90A67F has an ADC, a video decoder, a vertical filter, a field
memory, DACs and so on, so that it is easy to design a PIP
application with the least external components.
Features
Video Decoder for the Sub-Picture
·
NTSC, PAL (Europe), M-PAL and N-PAL systems
·
Automatic color system identification
·
8-bit ADC for a composite video input
·
Y/C separation by built-in digital filters
·
ACC, Color killer circuits
·
Contrast, Brightness, Tint and Color level controls
·
Accessible V-chip signal data via. IIC bus
Weight: 1.6 g (typ.)
Main-Picture System Clock
·
External PLL circuit for main-picture system clock (A recommended IC TI: TLC2933)
PIP Controller
·
525-60 Hz, 626-50 Hz and mixed are available
·
Vertical filter
·
Field memory (181 kbit)
·
PIP mode: Single PIP with 1/9 or 1/16 size, 6 PIPs with 1/36 size
·
Flexible PIP position
·
3ch 8-bit DACs for YUV or RGB outputs
·
YUV to RGB converter
Others
·
42 MHz crystal oscillator
·
I2C bus control
·
Package: QFP80
·
Power supply: 3.3 V
1
2002-02-06
Compsite
signal
CLMP
CVI
Block Diagram
BPF
Clamp
CCD
Slice
Sync
Sepa
LPF
ADC
XI
XO
42 MHz
Oscillator
V.Sync
Sepa
fH PLL
fsc
PLL
ACC
VCO
CKP
2
PD
PHREF
Chroma
LPF
Vertical
Filtering
subtiming Gen
Chroma
Demo
Y signal
Processing
Line
Memory
PHD
HD
main
YUV/RGB
PVD
VD
main
maintiming Gen
PIP
Control
Field
Memory
IIC BUS
UP
SAMPLING
DAC
DAC
DAC
2002-02-06
Ys
Bout
Rout
Yout
TC90A67F
VSS
PHD
NC
TESTM0
TESTM1
TESTM2
9
8
7
6
AVDD
5
CVI
4
AVSS
3
VREFH
2
BIASA
1
AVSS
YOUT 80
CKP
VREFL
AVDD 79
CKPSEL
AVSS
ROUT 78
PHREF
NC
AVSS 77
NC
TC90A67F
(QFP80)
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
CKOUT
BOUT 76
VDD
AVDD
AVDD 75
PVD
3
BIASD
NC 74
NC
NC
BIAS1 73
VSS
VREF
NC 72
YS
NC
BIAS2 71
PIPEN
AVSS
VREFD 70
NC
FILTER
NC 69
SCL
AVDD
NC 68
SDA
CKIN
VSS 67
VDD
NC
VDD 66
VSS
TEST2 65
RESET
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
VCHIP
CKC
QFP80-P-1420-0.80B
CKILL
CKCSEL
Terminal Connection Diagram
NC
CLMP
25 VDD
26 TEST
27 VSS
28 XI
29 XO
30 NC
31 VDD
32 NC
33 NC
34 CSTD
35 VSS
36 VDD
37 PFIELD
38 CFIELD
39 CVREF
40 CHREF
2002-02-06
TC90A67F
TC90A67F
Terminal Function
QFP80-P-1420-0.80B
PIN
Name
I/O
1
AVSS
¾
Ground for DAC
2
BIASA
¾
ADC bias voltage
3
VREFH
¾
Upper limit reference voltage of ADC
4
AVSS
¾
Ground for ADC
5
CVI
I
6
AVDD
¾
Power supply for ADC
7
VREFL
¾
Lower limit reference voltage of ADC
8
AVSS
¾
Ground for ADC
9
NC
¾
10
CKOUT
O
384fH-clock output
11
AVDD
O
Power supply for VCO
12
BIASD
¾
DAC bias voltage
13
VREF
¾
Lower limit reference voltage of DAC
14
NC
¾
15
NC
¾
16
AVSS
¾
Ground for VCO
17
FILTER
O
VCO filter terminal
18
AVDD
¾
Power supply for DAC
19
CKIN
I
20
NC
¾
21
VSS
¾
Ground for digital circuit
22
CKC
I
Clock input (sub-picture)
23
CKCSEL
I
Internal/external 384fH VCO select
24
CLMP
O
Clamp level output
25
VDD
¾
Power supply for digital circuit
26
TEST
I
27
VSS
¾
Function
Condition
normal: 2.3 V
Composite video signal input
normal: 1.0 V
normal: 1.8 V
384fH-clock input
Test pin
L: internal, H: external
normal: H
Ground for crystal oscillator
28
XI
I
42 MHz crystal oscillator input
29
XO
O
42 MHz crystal oscillator output
30
NC
¾
31
VDD
¾
32
NC
¾
33
NC
¾
34
CSTD
O
Internal signal output
35
VSS
¾
Ground for DRAM
36
VDD
¾
Power supply for DRAM
37
PFIELD
O
Field odd/even output (main picture)
H: even, L: odd
38
CFIELD
O
Field odd/even output (sub picture)
H: even, L: odd
39
CVREF
O
Vertical sync. output (sub picture)
40
CHREF
O
Horizontal sync. output (sub picture)
41
NC
¾
Power supply for crystal oscillator
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2002-02-06
TC90A67F
PIN
Name
I/O
42
CKILL
O
Color killer detection output (sub picture)
H: color killer ON,
L: OFF
43
VCHIP
I
23rd-line detect signal output
23rd-line: H
44
RESET
I
Reset input
L: reset
45
VDD
¾
Power supply for digital circuit
46
SDA
I/O
I2C BUS data input, data and acknowledge output
47
SCL
I
48
NC
¾
49
PIPEN
I
PIP enable
normal: H
50
YS
O
Main, sub-picture switching pulse
sub-picture: high
51
NC
¾
52
VSS
O
Ground for digital circuit
53
PVD
I
Vertical sync. input (main picture)
54
VDD
O
Power supply for digital component
55
NC
¾
56
PHREF
O
Horizontal sync. output (main picture)
57
CKPSEL
I
CKP frequency selection
58
CKP
I
Clock input (main-picture)
59
VSS
¾
60
PHD
I
61
NC
¾
62
TESTM0
63
Function
Condition
I2C BUS clock input
normal: negative
L: 24 MHz, H: 48 MHz
Ground for digital circuit
Horizontal sync. input (main picture)
normal: positive
I
Test pin
normal: H
TESTM1
I
Test pin
normal: H
64
TESTM2
I
Test pin
normal: H
65
TEST2
I
Test pin
normal: H
66
VDD
¾
Power supply for digital circuit
67
VSS
¾
Ground for digital circuit
68
NC
¾
69
NC
¾
70
VREFD
I
71
BIAS2
¾
72
NC
¾
73
BIAS1
¾
74
NC
¾
75
AVDD
¾
Power supply for DAC
76
BOUT
O
Analog signal output (B-Y or B)
77
AVSS
¾
Ground for DAC
78
ROUT
O
Analog signal output (R-Y or R)
79
AVDD
¾
Power supply for DAC
80
YOUT
O
Analog signal output (Y or G)
Lower limit reference voltage of DAC
normal: 1.8 V
DAC bias reference voltage
DAC bias reference voltage
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2002-02-06
TC90A67F
System Block Diagram
Main V/C/J
Chroma
Demo
RGB Text
Processor
Sync
Processor
YUV
Processor
Main Video
H/V
YUV
YUV
PIP
Controller
Ys
Sub Video
Sub
V/C/J
TC90A67F
PIP Mode
1 PIP MODE
Size: 1/3, 1/4, 1/6
6 PIP MODE 1
Size: 1/6 ´ 6
6 PIP MODE 2
Size: 1/6 ´ 6
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2002-02-06
TC90A67F
Function
TC90A67F has horizontal and vertical sync separation circuit for sub picture, color demodulation circuit for sub
picture, horizontal and vertical timing generation circuit for main picture, PIP control circuit.
Color demodulation circuit consists of digital circuit, and corresponds to M-NTSC, PAL, M-PAL, N-PAL system. It
is possible to process the sub picture easily, according to adopting system clock of 24 MHz by digital PLL circuit
locked fH. Horizontal and vertical timing generation circuit uses system clock (24 MHz) generated by analog PLL
circuit locked main picture’s fH.
PIP control circuit consists of filter for horizontal and vertical reduction, line memory, field memory and
according to changing horizontal and vertical reduction factors, it is possible to carry out various pip sizes.
1. ADC, Clamping Circuit
Dynamic range of ADC is 1.32 Vp-p whose voltage is fixed in IC. (top voltage is 2.31 V, bottom voltage is
0.99 V) ADC has pedestal clamp function, base voltage is output from CLMP terminal. The pedestal level
becomes about 1.32 V. (64LSB)
2. Horizontal and Vertical Sync for Main Picture
It is necessary to input main picture’s H-sync and V-sync at PHD and PVD terminal in order to make
system clock for readout stored data into the internal field memory. PHD and PVD are fitted to 5 V. It can
be inverted the polarity using IICBUS registers WHINV and WNINV at sub address 29hex.
At terminals of IC, polarity of H-sync is positive and V-sync is negative.
The clocks from external VCO are selectable in 24 MHz and 48 MHz, it can be switched by given voltage
to CKPSEL (SDIP: 52 pin, QFP: 57 pin) terminal. (CKPSEL = L: 24 MHz, CKPSEL = H: 48 MHz)
3. The System Clock Locked to the Sub Picture’s Horizontal Sync.
The signal converted into the digital environment passes through horizontal sync separation circuit,
horizontal locked circuit, which construct PLL circuit, it makes the system clock locked to the sub picture’s
horizontal sync.
This clock is put in internal VCO and generated the system clock of 24 MHz.
4. Horizontal Reduction
It is necessary to limit to frequency bandwidth for Y signal and color difference signal concerning PIP
mode. Horizontal reduction is selectable using HWS. (HWS: sub address 10hex)
HWS [1:0]
Horizontal Reduction
Sampling Rate for Y
Sampling Rate for Color Difference
00
1/3
4 MHz
1 MHz
01
1/4
3 MHz
0.75 MHz
10
1/6
2 MHz
0.5 MHz
11
1/8
1.5 MHz
0.375 MHz
In order to horizontal reduction, LPFs are used for Y signal and color difference signal.
It is selectable in two kinds of LPF for Y signal and six kinds of LPF for color difference signal.
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TC90A67F
5. Vertical Reduction
It is necessary to reduce vertical direction concerning PIP mode, and vertical reduction is carried out
from multiplication of coefficient as below. Vertical reduction is selectable using VWS.
(VWS: sub address 10hex)
Vertical Reduction
1H
Coefficient
2H
Coefficient
3H
Coefficient
4H
Coefficient
5H
Coefficient
6H
Coefficient
1/3 (VWS [1:0] = 00)
1/4
1/2
1/4
¾
¾
¾
1/4 (VWS [1:0] = 01)
1/8
3/8
3/8
1/8
¾
¾
1/5 (VWS [1:0] = 10)
1/16
1/4
3/8
1/4
1/16
¾
1/6 (VWS [1:0] = 11)
1/16
3/16
1/4
1/4
3/16
1/16
6. The Sub Picture’s Area of Writing in the Field Memory and Reading from the Field
Memory
Writing start position is defined horizontal start point to write (sub address 16hex: CHS) and vertical
start point to write. (sub address 16hex: CVSN or sub address 17hex: CVSP)
CVSN: Vertical frequency of sub picture is 60 Hz
CVSP: Vertical frequency of sub picture is 50 Hz
Horizontal width of the sub picture is defined by sampling number of horizontal direction. (sub address
1Ahex: HSPL) The number of writing vertical lines is determined internally according to vertical frequency
of the main picture and VWS.
Reading start position is defined horizontal start point to read (sub address 14hex: PHS) and vertical
start point to read. (sub address 14hex: PVSN or 15hex: PVSP)
PVSN: Vertical frequency of sub picture is 60 Hz
PVSP: Vertical frequency of sub picture is 50 Hz
Horizontal display size of the sub picture is defined by PHW (sub address 12hex) and the readout
number of vertical lines is defined by PVWN (sub address 12hex) or PVWP (sub address 13hex).
PVWN: Vertical frequency of sub picture is 60 Hz
PVWP: Vertical frequency of sub picture is 50 Hz
7. DACs for Y Signal and Color Difference Signal
TC90A67F is built-in three 8 bit-DAC in motion on 24 MHz. Output dynamic range is determined by the
difference between VDD and VREFD terminal voltage. Standard level is 1.5 Vp-p.
8. ACC Control
ACC control is carried out comparing demodulation result of color burst signal with set reference level by
ACCPAL or ACCNTSC register. (ACCPAL, ACCNTSC: sub address 21hex)
When compared value is less than the reference level, controller puts on gain, and more than reference
level, controller cuts down one.
9. Peaking Circuit for Y Signal
It is possible to carry out a clear picture according to putting up some frequency bandwidth when sub
picture becomes indistinct picture for reducing high frequency bandwidth using LPF for Y signal. There are
two kinds of characteristics for LPF, and it is selectable about gain of four stages respectively using YPKGS
and YPKGG.
YPKGS: select for LPF characteristics (sub address 10hex)
YPKGG: select for gain (sub address 10hex)
10. PGB Matrix Circuit
For a built-in RGB matrix circuit, and when RGBON = 1, it can be changed R-Y, Y, B-Y into RGB signal.
How to find the value of coefficient (a, b, c) is as below.
< c < 1)
1Chex: MTXCR: a, MTXCG2: b, MTXCG1: c (on condition 0 <
= a < 1, 0 <
= b < 1, 0 =
R = a (R - Y) + Y
G = b {-(R - Y)} + c {-(B - Y)} + Y
B = (B - Y) + Y
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2002-02-06
TC90A67F
11. Blue Back Function
It is possible to control blue back function using BBACK resister.
(BBACK: sub address 13hex, BBACK = 1: blue back mode)
It is available for only sub picture set to live mode. BBACK is useful when detected V chip or no signal. it
can be selected in four kinds of colors using BLEVEL.
(BLEVEL: sub address 13hex)
12. Addition of Frame
It is possible to add the frame to the sub picture. It is selectable frame width by FRAMEW and
adjustable frame color for RGB or R-Y, Y, B-Y respectively by FRAMEYG, FRAMER, FRAMEB.
(FRAMEW, FRAMEYG, FRAMER, FRAMEB: sub address 1Ehex)
13. CCD Slice Circuit
This IC has a CCD slice circuit, picks up CCD data, the CCD data and CCD slice conditions can be
checked on using IIC BUS read mode.
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2002-02-06
0
0
0
0
0
21
22
23
24
25
0
0
0
0
0
(0)
TYDLY
[1:0]
1F
20
(0)
YSDLYS
[1:0]
1E
0
0
0
FRAMEW
[1:0]
YGOS [5:0]
1D
HSPL [5:0]
0
0
MTXCB
[5:0]
0
0
1
BRTRGB
[5:0]
1C
1B
0
0
19
1A
DRAMCLRN
(0)
18
17
0
0
CHLOADN
[7:0]
1
0
1
0
1
10
1
0
(14)
NTSOFF
[6:0]
(3A)
SELREV
(0)
MTXCG
[24:20]
CLVL [4:0]
0
0
0
ROS [4:0]
(0)
FRAMEB
[3:0]
(112)
(0A)
(83)
(99)
(05C)
(04A)
(0)
HWS [1:0]
1
0
0
FRAMER
[3:0]
(00)
(0C)
FSSTM
[1:0]
CHLOADP
[7:0]
0
(1)
0
FSMO [1:0]
(76)
PIDREF
[6:0]
FSSEL
[1:0]
(0C)
NTSON
[6:0]
(14)
KILOFF
[6:0]
(F9)
CFLDREV
(0)
(51)
(0)
PFLDREV
(0)
(0)
(00)
(0A)
ACCNTSC
[6:0]
0
BOS [4:0]
MTXCG
[14:10]
(00)
(00)
(0000)
HUE [7:0]
MSNUM
[2:0]
(0)
2
RADOS
[12:0]
CTRT [4:0]
VWS [1:0]
3
(0000)
CVSP [8:0]
CVSN [7:0]
PVSP [8:0]
PVSN [7:0]
PVWP [8:0]
PVWN [8:0]
RON
PALDET
4
WADOS
[12:0]
(0)
(0)
PIPNUM
[2:0]
PD
UNLOCK
5
TATEON
(0)
CKIL
SLV [6:0]
6
CLPF [2:0]
PVDET60
BEDGE
7
YPKGG
[1:0]
PNOVPN
AEDGE
8
(0C)
0
(FE)
OFF2527
(0)
(0)
(00)
1
(19)
(00)
(2B)
(0)
(31)
(0)
YLPFS (0)
PVMD525
SBDET
9
KILON [6:0]
ACCPAL
[6:0]
(0)
PMDS [1:0]
PMDFIX
(0)
PHW 0 [2:0]
YPKGS
(0)
CFIELD
10
FRAMEYG
[3:0]
(00)
(31)
HUEBIAS
[5:0]
(32)
(00)
STRO [3:0]
(1)
BCF [1:0]
11
(0)
CHS [7:0]
16
SELGAIN
(0)
PHS [7:0]
(0)
PHC [6:0]
BLEVEL
[1:0]
15
BBACK
(0)
PHW [6:0]
YDLY1 [1:0]
CVDET60
12
14
13
12
(0)
0
11
MF
TRAP358
(0)
TRAPFIX
(0)
0
10
0
CNOVPN
CVMD525
NOSIG
02 (READ)
CRIN [3:0]
13
CCDATA
[15:0]
CR13DET
00 (READ)
14
01 (READ)
15
Sub Address
Bus Map (the value in parentheses indicate preseted data. the parts of mesh is fixed, input the indicated value.)
2002-02-06
(1)
RGBON (0)
MSON (0)
(0)
0
TC90A67F
29
1
0
0
1
1
28
0
0
1
1
13
27
14
SSLV [5:0]
15
26
Sub Address
WS262
(0)
0
0
12
WVINV
(0)
0
(20)
11
WHINV
(0)
CCDL [3:0]
0
10
F60
(0)
0
9
11
F50
(0)
(8)
0
CCDSBH
[4:0]
8
0
F50
(0)
F60
(0)
0
0
(0C)
6
0
7
0
0
0
5
0
0
0
4
0
0
0
CCDSBL
[4:0]
3
0
0
FLDSEL
(1)
2
0
0
SELFLOOP
(0)
(4)
1
2002-02-06
0
WS262 (0)
SLVFIX (1)
0
TC90A67F
TC90A67F
2
Description of I C Bus Registers
Write Command
Sub
Address
Bit
Name
Preset
10H
D15
¾
0
Fix to ‘0’
D14
TRAPFIX
0
Change fsc-trap mode.
D13
TRAP358
0
Comment
0: auto, 1: fix
Select fsc-trap characteristic. (active at TRAPFIX = 1 only)
0: 4.43 MHz, 1: 3.58 MHz
D12, D11
YDLY1 [1:0]
01
D10
YPKGS
0
Y-output signal delay against U and V output signal (rough).
Select Y-peaking filter characteristic.
0: hi-band, 1: low-band
Select Y-horizontal decimation filter characteristic.
D9
YLPFS
0
0: hi-band, 1: low-band
11H
D8, D7
YPKGG
[1:0]
00
D6 to D4
CLPF [2:0]
000
Select R-Y/B-Y horizontal decimation filter characteristic.
D3, D2
VWS [1:0]
00
Select vertical decimation.
00: 1/3, 01: 1/4, 10: 1/5, 11: 1/6
D1, D0
HWS [1:0]
00
Select horizontal decimation.
00: 1/3, 01: 1/4, 10: 1/6, 11: 1/8
D15, D14
¾
00
Fix to ‘0’
D13
MF
0
Set single-field display mode.
Select Y-peaking gain level.
00: 0, 01: 1/4, 10: 1/2, 11: 1
0: normal, 1: Fixed to single-field display
Select off-and-on cycle of field memory writing. (4 field step)
0000: normal
D12 to D9
STRO [3:0]
0000
D8
TATEON
0
D7 to D5
PIPNUM
[2:0]
000
D4
RON
0
D3 to D1
MSNUM
[2:0]
000
D0
MSON
0
D15 to D9
PHW [6:0]
D8 to D0
PVWN [8:0]
D15
BBACK
0001: strobe (once 6 fields)
1110: strobe (once 58 fields)
0010: strobe (once 10 fields)
1111: still
Sub-pictures’ set at multi-pictures
0: horizontal, 1: vertical
Set multi-picture numbers of the animation picture.
Sub-picture display ON/OFF.
0: OFF, 1: ON
Select multi-strobe pictures number.
12H
000: 1-picture, 001: 2-pictures, 010: 3-pictures, 011: 4-pictures, 100: 5-pictures,
101: 6-pictures
Select multi-strobe mode.
(0: normal strobe mode, 1: multi-strobe mode)
011000
Sub-pictures range in the main-picture. (horizontal width, rough)
1
001001 Sub-pictures range in the main-picture (vertical height)
010
, when main-picture is 60 Hz system.
Replace sub-picture by blue-back at write-memory.
13H
0
0: normal, 1: blue-back
Select blue-back level. (DRAMCLRN = 1 or BBACK = 1 only)
BLEVEL
[1:0]
00
D12
SELGAIN
00
Control internal Y-level.
D11 to D9
PHE0 [2:0]
000
Sub-pictures range in the main-picture. (horizontal width, fine)
D8 to D0
PVWP [8:0]
D14, D13
00: black, 01: blue1, 10: blue2, 11: blue3
0: 1.5 times, 1: Twice
001011 Sub-pictures range in the main-picture (vertical height)
100
, when main-picture is 50 Hz system.
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2002-02-06
TC90A67F
Sub
Address
14H
15H
16H
17H
18H
19H
1AH
Bit
Name
Preset
Comment
D15 to D8
PHS [7:0]
D7 to D0
PVSN [7:0]
1001100 Vertical starting point of the sub-pictures in the main-picture
01
, when main-picture is 60 Hz system.
D15 to D9
PHC [6:0]
000000 Set clock frequency of main-picture processing.
0
(set the dividing number of fH PLL.)
D8 to D0
PVSP [8:0]
010000 Vertical starting point of the sub-pictures in the main-picture
011
, when main-picture is 50 Hz system.
D15 to D8
CHS [7:0]
000110
Horizontal starting point to write into the memory in the sub-picture.
01
D7 to D0
CVSN [7:0]
D15 to D10
BRTRGB
[5:0]
000000
D9
¾
1
D8 to D0
CVSP [8:0]
D15
DRAMCLRN
0
Field-memory reset
D14
¾
1
Fix to ‘1’
D13
¾
0
Fix to ‘0’
D12 to D0
WADOS
[12:0]
D15 to D13
¾
D12 to D0
RADOS
[12:0]
D15 to D10
HSPL [5:0]
110010 Set number of horizontal sampling on the input sub-picture.
D9 to D5
CLVL [4:0]
00000
D4 to D0
CTRT [4:0]
00000
D15, D14
¾
00
D13 to D8
HUEBIAS
[5:0]
000000
D7 to D0
HUE [7:0]
000000 Adjustment the demodulation phase for R-Y and B-Y signals. (NTSC only)
00
10000000: -45°, 00000000: 0°, 01111111: +45°
001010
Horizontal starting point of the sub-pictures in the main-picture.
11
000010 Vertical starting point to write into the memory in the sub-picture
10
at 60 Hz system.
Control bright at RGB mode.
100000: -32 LSB, 000000: 0 LSB, 011111: +31 LSB
Fix to ‘1’
100010 Vertical starting point to write into the memory in the sub-picture
010
at 50 Hz system.
0: normal, 1: reset
000000 Set start-address to write the memory.
000000
(for the memory partition to memorize several sub-pictures at the same time.)
0
000
Fix to ‘0’
000000 Set start-address to read from the memory.
000000
(for the select of sub-pictures in the memory)
0
Set color-level.
10000: -6 dB, 00000: 0 dB, 01111: +6 dB
Set contrast level.
1BH
00000: +1 dB, 11111: +3.5 dB
Fix to ‘0’
Adjustment the demodulation phases for R-Y signal. (NTSC only)
000000: 0°, 111111: +45°
13
2002-02-06
TC90A67F
Sub
Address
1CH
Bit
Name
Preset
Comment
D15 to D10
MTXCB
[5:0]
110001 Set RGB matrix coefficient 1.
D9 to D5
MTXCG
[24:20]
01100
Set RGB matrix coefficient 2.
D4 to D0
MTXCG
[14:10]
01010
Set RGB matrix coefficient 3.
D15, D10
YGOS [5:0]
000000
D9 to D5
ROS [4:0]
00000
D4 to D0
BOS [4:0]
00000
D15, D14
YSDLY [1:0]
01
D13, D12
FRAMEW
[1:0]
00
D11 to D8
FRAMEYG
[3:0]
0000
Select frame signal level of PIP. (Y or G signal)
D7 to D4
FRAMER
[3:0]
0000
Select frame signal level of PIP. (R-Y or R signal)
D3 to D0
FRAMEB
[3:0]
0000
Select frame signal level of PIP. (B-Y or B signal)
D15, D14
TYDLY [1:0]
00
Y-output signal delay for U and V output signal. (fine).
D13
¾
0
Fix to ‘0’
D12
PMDFIX
0
Set DC offset of sub-picture. (Y or G signal)
1DH
100000: -32 LSB, 000000: 0 LSB, 011111: +31 LSB
Set DC offset of sub-picture. (R-Y or R signal)
10000: -16 LSB, 00000: 0 LSB, 01111: +15 LSB
Set DC offset of sub-picture. (B-Y or B signal)
1EH
1FH
10000: -16 LSB, 00000: 0 LSB, 01111: +15 LSB
Timing offset of Ys pulse. 00: -1 ck, 01: center, 10: +1 ck, 11: +2 ck (24 MHz)
Select the side frame width of sub-picture.
00: OFF (no-frame), 01: narrow, 10: center, 11: wide
Clock frequency to read from the memory.
0: auto, 1: fix
D11, D10
PMDS [1:0]
00
D9
OFF2527
0
Select Clock frequency to read from the memory.
(active at PMDFIX = 1 only) 00: 12 MHz, 01: 9 MHz, 10: 18 MHz, 11: 16 MHz
Set 50 Hz/ 60 Hz-conversion mode. (VWS = 1/3 mode only)
0: ON, 1: OFF
20H
D8
SELREV
0
Set reverse mode.
0: normal, 1: reverse
D7 to D3
¾
00000
D2
PFLDREV
1
Reverse PFIELD at internal circuit. 0: reverse, 1: normal
D1
CFLDREV
0
Reverse CFIELD at internal circuit. 0: normal, 1: reverse
D0
RGBON
1
Select output signal format.
D15 to D8
CHLOADN
[7:0]
111111 Set clock frequency of sub-picture processing at 60 Hz system.
10
(set the dividing number of H-PLL)
D7 to D0
CHLOADP
[7:0]
111110 Set clock frequency of main-picture processing at 50 Hz system.
01
(set the dividing number of H-PLL)
Fix to ‘0’
14
0: YUV, 1: RGB
2002-02-06
TC90A67F
Sub
Address
Bit
Name
Preset
21H
D15, D14
¾
00
D13 to D7
ACCPAL
[6:0]
011101 Set ACC reference level (for PAL).
0
0: Minimum level 127: Maximum level
D6 to D0
ACCNTSC
[6:0]
101000 Set ACC reference level (for NTSC).
1
0: Minimum level 127: Maximum level
D15, D14
¾
D13 to D7
KILON [6:0]
0: Minimum level 63: maximum level
000110 Set color killer ON level.
0
It must be set “KILON” < “KILOFF”
D6 to D0
KILOFF
[6:0]
0: Minimum level 63: maximum level
001010 Set color killer OFF level.
0
It must be set “KILON” < “KILOFF”
D15, D14
¾
D13 to D7
NTSOFF
[6:0]
Set level to turn over from NTSC to PAL in NTSC/PAL detector.
001010
0: Minimum level 63: maximum level
0
It must be set “NTSON” < “NTSOFF”
D6 to D0
NTSON
[6:0]
Set level to turn over from PAL to NTSC in NTSC/PAL detector.
000110
0: Minimum level 63: maximum level
0
It must be set “NTSON” < “NTSOFF”
D15 to D7
¾
D6 to D0
PIDREF
[6:0]
D15 to D12
¾
0000
Fix to ‘0’
D11 to D8
¾
1111
Fix to ‘1’
D7, D6
¾
00
Fix to ‘0’
D5, D4
FSSTM [1:0]
10
22H
23H
24H
25H
00
00
Comment
Fix to ‘0’
Fix to ‘0’
Fix to ‘0’
000000
Fix to ‘0’
000
111011 Sensitivity of PAL-IDENT detection.
0
0: Minimum Sensitivity 63: Maximum Sensitivity
Set cycle of color system detection in color sub-carrier frequency detector.
(1field step)
D3, D2
FSSEL [1:0]
00
0: 1 field
3: 4 fields
Set color system of sub-picture processing. (at FSMO = 11 only)
00: N-PAL, 01: M-PAL, 10: M-NTSC, 11: BG-PAL/4.43NTSC
Mode for color sub-carrier frequency search
D1, D0
FSMO [1:0]
01
00: M-NTSC only, 01: BG-PAL/4.43NTSC®M-NTSC,
10: N-PAL®M-PAL®M-NTSC, 11: FSSEL [1:0]
Set slice level for CCD.
26H
D15 to D10
SSLV [5:0]
100000
(this data is initial value of peak detector circuit at auto-slice mode.)
D9 to D5
CCDSBH
[4:0]
01100
Set minimum-width of high-period in start-bit for CCD.
D4 to D0
CCDSBL
[4:0]
00100
Set minimum-width of low-period in start-bit for CCD.
15
2002-02-06
TC90A67F
Sub
Address
Bit
Name
Preset
27H
D15, D14
¾
11
D13 to D3
¾
D2
FLDSEL
1
Control CCD slice 1.
D1
SELPLOOP
0
Control CCD slice 2.
D0
SLVFIX
0
Fix CCD slice level.
D15
¾
1
Fix to ‘1’
D14
¾
0
Fix to ‘0’
D13
¾
1
Fix to ‘1’
D12
¾
0
Fix to ‘0’
D11 to D8
CCDL [3:0]
1000
28H
Comment
Fix to ‘1’
000000
Fix to ‘0’
00000
0: fix, 1: auto-slice
Set line No. of data slicing for CCD.
1000: 21 H (NTSC)
29H
D7
F60
0
Force 60 Hz mode (sub-picture).
0: normal, 1: force
D6
F50
0
Force 50 Hz mode (sub-picture).
0: normal, 1: force
D5 to D1
¾
00000
D0
WS262
0
Reverse CFIELD polarity.
D15
¾
0
Fix to ‘0’
D14, D13
¾
11
Fix to ‘1’
D12
WS262
0
Reverse PFIELD polarity.
D11
WVINV
0
Fix to ‘0’
0: even high, 1: odd high
0: even high, 1: odd high
Set polarity of vertical sync pulse input at pin “PVD” . (main-picture)
0: Negative, 1: Positive
D10
WHINV
0
Set polarity of horizontal sync pulse input at pin “PHD”. (main-picture)
0: Positive, 1: Negative
D9
F60
0
Force 60 Hz mode (main-picture)
0: OFF, 1: ON
D8
F50
0
Force 50 Hz mode (main-picture)
0: OFF, 1: ON
D7 to D0
¾
000000
Fix to ‘0’
00
16
2002-02-06
TC90A67F
Read Command
Sub
Address
Bit
Name
00H
D15
CRI3DET
CRI detection.
D14 to D11
CRIN [3:0]
CRI number detection.
D10
CFIELD
Field-detection. (sub-picture)
1: 1st field, 0: 2nd field
D9
SBDET
Start-bit (001) detection.
0: not start-bit detected, 1: start-bit detected
D8
AEDGE
Comment
Caution of too near sampling point for back-edge of data.
0: OK, 1: too near
Caution of too near sampling point for front-edge of data.
D7
BEDGE
0: OK, 1: too near
01H
02H
D6 to D0
SLV [6:0]
D15 to D0
CCDDATA
[15:0]
D15
NOSIG
D14
CVMD525
Slice level data.
CCD data including parity bits.
Result of no-signal detection (sub-picture)
0: exist, 1: not-signal
Vertical sync frequency standard/non-standard detection. (sub-picture)
0: Non-standard, 1: Standard
D13
CNOVPN
Vertical sync detection. (sub-picture)
0: exist, 1: No vertical sync
D12
CVDET60
Vertical frequency detection. (sub-picture)
0: 50 Hz, 1: 60 Hz
D11, D10
BCF [1:0]
System mode detection. (sub-picture)
00: N-PAL, 01: M-PAL, 10: M-NTSC,
11: BG-PAL/4.43NTSC
D9
PVMD525
Vertical sync frequency standard/non-standard detection. (main-picture)
0: Non-standard, 1: Standard
D8
PNOVPN
Vertical sync detection. (main-picture)
0: exist, 1: No vertical sync
D7
PVDET60
Vertical frequency detection. (main-picture)
0: 50 Hz, 1: 60 Hz
D6
CKIL
Color Killer detection. (sub-picture)
0: Killer-off, 1: Killer-on
D5
PDUNLOCK H-PLL condition. (sub-picture)
D4
PALDET
PAL signal detection.
0: Lock, 1: Un-lock
0: NTSC or No-color, 1: PAL
CCD Data Slicer Supplementary Explanation
SLVFIX
SELFLOOP
FLDSEL
1
0
¾
Slice Level Control Circuit
Detected Slice Level Feedback
Motion Field at Auto Slice
ON
ON
1st and 2nd field
Auto slice function works both field. (CCD details sliced at suitable level)
ON
1
1
¾
0
1
¾
OFF
1st and 2nd field
Slice level is detecting from value of SSLV resistor, and sliced the most suitable value.
(Detected slice level is not feedback at the next field)
ON
¾
OFF
Slice level is fixed value of SSLV resistor.
ON
ON
0
2nd field (CFIELD = 0)
Renewed slice level reading value of SLV resistor only 2nd field.
0
0
ON
ON
1
1st field (CFIELD = 1)
Renewed slice level reading value of SLV resistor only 1st field.
17
2002-02-06
2
0
0
START
START
SLAVE ADDRESS
(0010111)
0
A3
SLAVE ADDRESS
(0010111)
1
A4
R/W
ACK
R/WACK
1
A2
1
A0
SUB ADDRESS
SUB ADDRESS
1
A1
1/0
R/W
ACK END START
ACK
ACK
SLAVE ADDRESS
(0010111)
DATA (MSB)
R/W
ACK
DATA (LSB)
DATA (MSB)
ACK END
ACK
DATA (LSB)
ACK END
18
2002-02-06
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined
by Philips.
SDA
SCL
Read Format
SDA
SCL
Write Format
A5
A6
Slave Address
Sub-pictures range in the main-picture. (horizontal width)
Outline of I C BUS Control Format
TC90A67F
TC90A67F
Maximum Ratings (VSS = 0 V, Ta = 25°C)
Characteristics
Symbol
Rating
Unit
Supply voltage
VDD
VSS to VSS + 4.5
V
Applied voltage
VIN
-0.3 to VDD + 0.3
V
Applied current
IIN
±10
mA
Power dissipation
PD
1538
mW
TSTG
-55 to 125
°C
Storage temperature
1538
1500
Power dissipation
PD
(mW)
TD-PD (on board mounting)
1000
846
500
0
25
50
70
100
125
Ambient temperature (°C)
Recommended Operating Conditions
Characteristics
Symbol
Rating
Unit
Supply voltage
VDD
3.0 to 3.6
V
Input voltage
VIN
0 to VDD
V
Output voltage
VOUT
0 to VDD
V
Ambient temperature
TOPR
-10 to 70
°C
19
2002-02-06
TC90A67F
Electrical Characteristics
DC Characteristics
Digital Part Operating Condition: VDD = 3.3 V, Ta = 25°C
Characteristics
Consumption current
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
Applicable
Terminals
IDD
¾
¾
¾
160
230
mA
¾
High
input
voltage
CMOS input
VIH1
¾
¾
VDD ´
0.8
¾
VDD
V
(Note1)
Schmitt trigger
input
VIH2
¾
¾
VDD ´
0.8
¾
VDD
V
(Note2)
Low level
input
voltage
CMOS input
VIL1
¾
¾
¾
¾
0.8
V
(Note1)
Schmitt trigger
input
VIL2
¾
¾
¾
¾
0.8
V
(Note2)
High level
IIH
¾
¾
-10
¾
+10
mA
(Note1)
(Note2)
Low level
IIL
¾
¾
-10
¾
+10
mA
(Note1)
(Note2)
High level
VOH
¾
¾
2.4
¾
¾
V
(Note3)
Low level
VOL
¾
¾
¾
¾
0.4
V
(Note3)
Input
current
Output
voltage
Note1: CKC, CKCSEL, TEST, SDA, PIPEN, CKPSEL, CKP, TESTM0, TESTM1, TESTM2, TEST2
Note2: RESET, SCL, PVD, PHD
Note3: CLMP, CSTD, PFIELD, CFIELD, CVREF, CHREF, CKILL, VCHIP, Ys, PHREF
ADC Characteristics Operating Condition: VDD = 3.3 V, Ta = 25°C
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
Applicable
Terminals
Resolution
RS1
¾
¾
¾
¾
8
bit
¾
Input level
ADIN
¾
¾
1.32
¾
Vp-p
CVI
BIASA
¾
¾
0.9
V
BIASA
VREFH
¾
¾
2.3
V
VREFH
VREFL
¾
¾
1.0
V
VREFL
Non-linear error
ILE1
¾
(8 bit precision)
¾
¾
±3
LSB
¾
Differential
non-linear error
DLE1
¾
(8 bit precision)
¾
¾
±2
LSB
¾
DG
DG
¾
¾
0
¾
6.5
%
¾
DP
DP
¾
¾
0
¾
4.0
deg
¾
Characteristics
Pin voltage
A/D
converter
AVDD = 3.3 V
20
2002-02-06
TC90A67F
DAC, VCO Characteristics Operating Condition: VDD = 3.3 V, Ta = 25°C
Characteristics
Resolution
Output level
D/A
converter
(VIDEO)
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
Applicable
Terminals
RS2
¾
¾
¾
¾
8
bit
¾
YOUT
¾
(VDD - VREFD)
¾
¾
1.5
Vp-p
YOUT
ROUT
¾
(VDD - VREFD)
¾
¾
1.5
Vp-p
ROUT
BOUT
¾
(VDD - VREFD)
¾
¾
1.5
Vp-p
BOUT
Non-linear error
ILE2
¾
(8 bit precision)
¾
¾
±1
LSB
¾
Differential
non-linear error
DLE2
¾
(8 bit precision)
¾
¾
±1
LSB
¾
BIAS1
¾
¾
0.8
1.0
1.4
V
BIAS1
Pin voltage
D/A
converter
(CLOCK)
VCO
BIAS2
¾
¾
1.8
2.0
2.2
V
BIAS2
Reference voltage
level
VREFD
¾
¾
1.8
¾
¾
V
VREFD
Output impedance
ZOUT1
¾
¾
¾
200
¾
W
YOUT,
ROUT,
BOUT
Resolution
RSD2
¾
¾
¾
¾
6
bit
¾
Output level
CKOUT
¾
(VDD - VREF)
¾
¾
2.0
Vp-p
CKOUT
Non-linear error
ILE3
¾
(6 bit precision)
¾
¾
±3
LSB
¾
Differential
non-linear error
DLE3
¾
(6 bit precision)
¾
¾
±2
LSB
¾
Pin voltage
BIASD
¾
¾
0.8
1.0
1.4
V
BIASD
Reference voltage
level
VREF
¾
¾
1.3
¾
¾
V
VREF
Output impedance
ZOUT2
¾
¾
¾
200
¾
W
CKOUT
Pull-in frequency
FCK1
¾
¾
5.4
6.0
6.6
MHz
¾
Input amplitude
VCK
¾
¾
1.0
2.0
¾
V
CKIN
Pull-in oscillation
frequency
FCK2
¾
¾
21.6
24.0
26.4
MHz
¾
FILTER terminal
voltage
FILTER
¾
¾
0.8
¾
2.7
V
FILTER
21
2002-02-06
3
0.1 mF
C33
6
7
C32 R19
10 mF 560 W
5
+3.3 V
VSS
Y (G)
OUT
R-Y (R)
OUT
B-Y (B)
OUT
4
Q3
2SC1815
14
13
12
11
10
9
8
Q4
2SC1815
Q5
2SC1815
LQ19
LQ18
R23
4.7 kW
R22
4.7 kW
R21
4.7 kW
TLC2933
LQ17
1
2
3
4
5
6
7
C30
0.1 mF
YOUT
ROUT
BOUT
C26
VIDEO
INPUT
R1
510 W
C29
0.1 mF
0.1 mF
C28
0.1 mF
C27
10 kW 0.1 mF
R17
0.1 mF
C25
0.1 mF
C24
TC90A67F 1
80 YOUT
79 AVDD
78 ROUT
77 AVSS
76 BOUT
75 AVDD
74 NC
73 BIAS1
72 NC
71 BIAS2
70 VREFD
69 NC
68 NC
67 VSS
66 VDD
65 TEST2
10 mF
C2
SW3
R14
30 kW
R15
30 kW
C22
C23
SW2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
TESTM2
AVSS
2
2
4
3
1 mF
2SC1815
VIDEO
C3
PHD
5
CVI
C41
1
6
7
VSS
74HC14AP
TC90A67F
(QFP80)
CVREF
CFIELD
PFIELD
CVREF 39
CFIELD 38
PFIELD 37
22
LQ10
R9
1.5 kW
2SC1B15
CKIN
CKC
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
9
SW1
VDD 25
TEST 26
VSS 27
XI 28
XO 29
NC 30
VDD 31
NC 32
NC 33
CSTD 34
VSS 35
VDD 36
CHREF
CHREF 40
8
CKPSEL
8
NC
9
PHREF
NC
FILTER
Q 1 mF
14 13 12 11 10
C37
C39
SCL
AVDD
HD
R20
2 kW
R18
3 kW
R24
470 W
R25
470 W
R26
470 W
TLC2933
100
mF
LQ14
LQ15
LQ2
C31
0.1
mF
C34
6 pF
100
mF
VDD
NC
AVSS
LQ16
LQ1
C35
6 pF
C38
C40
C36
6 pF
0.1
mF
0.1
mF
TESTM0
VREFH
VDD
AVDD
PHD
LQ3
NC
AVSS
TESTM1
BIASA
C4 0.1 mF
33 k W
Q1
PHREF
LQ8
R16
8.2 kW
0.1 mF
RESET
VSS
SDA
SCL
Ys
PVD
LQ4
VCHIP
VCHIP
CKC
Application Circuit
C1
R3
CKILL
CKILL
CKCSEL
NC
4 pF
C5 0.1 mF
68 pF
R2
1 kW
R4
47 kW
R5
1 kW
NC
NC
LQ9
0.1 mF
C16
C20
0.1 mF
CSTD
LQ13
12 pF
C17
C18
1000 pF
R13
100 W
C21
R12
0.1 mF
PVD
BIASD
C8
0.1 mF
C9
0.1 mF
Q2
R8
R7
8.2 kW 10 kW
C10
0.1 mF
C11
C6 0.1 mF
R6
10 kW
Ys
NC
360 W
CKP
LQ5
VSS
VREF
R10
C12
R11
AVDD
C7 0.1 mF
LQ6
PIPEN
AVSS
820 W 0.01 mF
0.1 mF
270
kW
NC
CLMP
CKOUT
C13
VREFL
LQ7
SDA
CKIN
C14
0.1 mF
C15
0.1 mF
180 pF
L1
CY1
42 MHz 1.5
mH
C19
LQ12
LQ11
18 pF
2002-02-06
TC90A67F
TC90A67F
Package Dimensions
Weight: 1.6 g (typ.)
23
2002-02-06
TC90A67F
RESTRICTIONS ON PRODUCT USE
000707EBA
· TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
· The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
· The products described in this document are subject to the foreign exchange and foreign trade laws.
· The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
· The information contained herein is subject to change without notice.
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2002-02-06