VISHAY SQ3419EEV-T1-GE3

SQ3419EEV
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Vishay Siliconix
Automotive P-Channel 40 V (D-S) 175 °C MOSFET
FEATURES
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFET
• AEC-Q101 Qualifiedd
• 100 % Rg and UIS Tested
• Typical ESD Protection 800 V
• Compliant to RoHS Directive 2002/95/EC
PRODUCT SUMMARY
VDS (V)
- 40
RDS(on) () at VGS = - 10 V
0.050
RDS(on) () at VGS = - 4.5 V
0.078
ID (A)
- 7.4
Configuration
Single
TSOP-6
Top V iew
1
(1, 2, 5, 6) D
6
(3) G
3 mm
2
5
3
4
2.85 mm
Marking Code: 8Cxxx
(4) S
P-Channel MOSFET
ORDERING INFORMATION
Package
TSOP-6
Lead (Pb)-free and Halogen-free
SQ3419EEV-T1-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
- 40
Gate-Source Voltage
VGS
± 12
Continuous Drain Current
TC = 25 °C
ID
TC = 125 °C
Continuous Source Current (Diode Conduction)a
IS
- 4.3
- 6.3
IDM
- 29
Single Pulse Avalanche Current
IAS
- 20
EAS
20
Maximum Power Dissipationb
L = 0.1 mH
TC = 25 °C
PD
TC = 125 °C
Operating Junction and Storage Temperature Range
V
- 7.4
Pulsed Drain Current
Single Pulse Avalanche Energy
UNIT
5
1.6
A
mJ
W
TJ, Tstg
- 55 to + 175
°C
SYMBOL
LIMIT
UNIT
RthJA
110
RthJF
30
THERMAL RESISTANCE RATINGS
PARAMETER
Junction-to-Ambient
PCB
Mountc
Junction-to-Foot (Drain)
°C/W
Notes
a. Package limited.
b. Pulse test; pulse width  300 μs, duty cycle  2 %.
c. When mounted on 1" square PCB (FR-4 material).
d. Parametric verification ongoing.
S11-2124-Rev. B, 07-Nov-11
1
Document Number: 66714
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SQ3419EEV
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Vishay Siliconix
SPECIFICATIONS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
Gate-Source Threshold Voltage
Gate-Source Leakage
VDS
VGS = 0 V, ID = - 250 μA
- 40
-
-
VGS(th)
VDS = VGS, ID = - 250 μA
- 1.5
-
- 2.5
VDS = 0 V, VGS = ± 12 V
IGSS
-
-
± 2000
VGS = 0 V
VDS = - 40 V
-
-
-1
-
-
- 50
Zero Gate Voltage Drain Current
IDSS
VGS = 0 V
VDS = - 40 V, TJ = 125 °C
VGS = 0 V
VDS = - 40 V, TJ = 175 °C
-
-
- 150
On-State Drain Currenta
ID(on)
VGS = - 10 V
VDS=- 5 V
- 10
-
-
VGS = - 10 V
ID = - 2.5 A
-
0.041
0.050
VGS = - 4.5 V
ID = - 2 A
-
0.065
0.078
-
10
-
-
850
1065
Drain-Source On-State Resistancea
Forward Transconductanceb
RDS(on)
gfs
VDS = - 15 V, ID = - 4 A
V
nA
μA
A

S
Dynamicb
Input Capacitance
Ciss
Output Capacitance
Coss
-
140
175
Reverse Transfer Capacitance
Crss
-
95
120
Total Gate Chargec
Qg
-
10
15
-
2.8
-
-
4.7
-
2
7
12
-
9
14
-
8
12
-
26
39
-
10
15
Gate-Source
Chargec
Gate-Drain Chargec
Gate Resistance
Turn-On Delay Timec
Rise Timec
Turn-Off Delay
Qgs
Fall Timec
Source-Drain Diode Ratings and
VGS = - 4.5 V
VDS = - 20 V, f = 1 MHz
VDS = - 20 V, ID = - 4 A
Qgd
Rg
f = 1 MHz
td(on)
tr
Timec
VGS = 0 V
td(off)
VDD = - 20 V, RL = 5 
ID  - 4 A, VGEN = - 10 V, Rg = 1 
tf
pF
nC

ns
Characteristicsb
Pulsed Currenta
ISM
Forward Voltage
VSD
IF = - 1.6 A, VGS = 0 V
-
-
- 29
A
-
- 0.75
- 1.1
V
Notes
a. Pulse test; pulse width  300 μs, duty cycle  2 %.
b. Guaranteed by design, not subject to production testing.
c. Independent of operating temperature.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
S11-2124-Rev. B, 07-Nov-11
2
Document Number: 66714
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SQ3419EEV
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Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
10-0
0.005
10-1
10-2
I GSS - Gate Current (A)
I GSS - Gate Current (mA)
0.004
0.003
0.002
T J = 25 °C
0.001
10-3
10-4
10-5
TJ = 150 °C
10-6
TJ = 25 °C
10-7
10-8
10-9
0
10-10
0
5
10
15
20
VGS - Gate-to-Source Voltage (V)
0
25
5
10
15
20
VGS - Gate-to-Source Voltage (V)
25
Gate Current vs. Gate-Source Voltage
Gate Current vs. Gate-Source Voltage
30
30
V GS = 10 V thru 6 V
24
V GS = 5 V
ID - Drain Current (A)
ID - Drain Current (A)
24
18
12
V GS = 4 V
18
12
6
6
T C = 25 °C
T C = 125 °C
V GS = 3 V
T C = - 55 °C
0
0
0
2
4
6
8
VDS - Drain-to-Source Voltage (V)
0
10
2
4
6
8
VGS - Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
15
0.15
T C = - 55 °C
12
RDS(on) - On-Resistance (Ω)
g fs - Transconductance (S)
10
T C = 25 °C
9
T C = 125 °C
6
3
0.12
0.09
V GS = 4.5 V
0.06
V GS = 10 V
0.03
0
0.00
0
2
4
6
ID - Drain Current (A)
8
10
0
12
18
ID - Drain Current (A)
24
30
On-Resistance vs. Drain Current
Transconductance
S11-2124-Rev. B, 07-Nov-11
6
3
Document Number: 66714
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SQ3419EEV
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TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
1400
6
1200
5
1000
VGS - Gate-to-Source Voltage (V)
C - Capacitance (pF)
ID = 4 A
Ciss
800
600
400
Coss
200
V DS = 20 V
4
3
2
1
Crss
0
0
0
10
20
30
VDS - Drain-to-Source Voltage (V)
0
40
3
Capacitance
100
ID = 5 A
1.7
10
V GS = 10 V
IS - Source Current (A)
RDS(on) - On-Resistance (Normalized)
15
Gate Charge
2.0
1.4
V GS = 4.5 V
1.1
0.8
T J = 150 °C
1
T J = 25 °C
0.1
0.01
0.5
- 50
0.001
- 25
0
25
50
75
100
125
150
175
0
0.2
TJ - Junction Temperature (°C)
0.4
0.6
0.8
1.0
VSD - Source-to-Drain Voltage (V)
1.2
Source-Drain Diode Forward Voltage
On-Resistance vs. Junction Temperature
0.20
1.0
0.16
0.7
VGS(th) Variance (V)
RDS(on) - On-Resistance (Ω)
6
9
12
Qg - Total Gate Charge (nC)
0.12
T J = 150 °C
0.08
0.04
ID = 250 μA
0.4
ID = 5 mA
0.1
- 0.2
T J = 25 °C
0
0
2
4
6
8
- 0.5
- 50
10
VGS - Gate-to-Source Voltage (V)
0
25
50
75 100
TJ - Temperature (°C)
125
150
175
Threshold Voltage
On-Resistance vs. Gate-Source Voltage
S11-2124-Rev. B, 07-Nov-11
- 25
4
Document Number: 66714
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SQ3419EEV
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Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
VDS - Drain-to-Source Voltage (V)
- 40
ID = 1 mA
- 43
- 46
- 49
- 52
- 55
- 50
- 25
0
25
50
75 100 125
TJ - Junction Temperature (°C)
150
175
Drain Source Breakdown vs. Junction Temperature
THERMAL RATINGS (TA = 25 °C, unless otherwise noted)
100 µs
IDM Limited
10
ID - Drain Current (A)
Limited by RDS(on)*
1 ms
1
10 ms
100 ms
1 s, 10 s, DC
0.1
TC = 25 °C
Single Pulse
0.01
0.01
BVDSS Limited
0.1
1
10
100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area
S11-2124-Rev. B, 07-Nov-11
5
Document Number: 66714
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SQ3419EEV
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Vishay Siliconix
THERMAL RATINGS (TA = 25 °C, unless otherwise noted)
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
Notes:
0.1
PDM
0.1
0.05
t1
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = R thJA = 110 °C/W
0.02
3. T JM - TA = PDMZthJA(t)
Single Pulse
4. Surface Mounted
0.01
10- 4
10- 3
10- 2
10- 1
1
Square Wave Pulse Duration (s)
10
100
600
Normalized Thermal Transient Impedance, Junction-to-Ambient
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10-4
10-3
10-2
10-1
Square Wave Pulse Duration (s)
1
10
Normalized Thermal Transient Impedance, Junction-to-Foot
Note
• The characteristics shown in the two graphs
- Normalized Transient Thermal Impedance Junction-to-Ambient (25 °C)
- Normalized Transient Thermal Impedance Junction-to-Foot (25 °C)
are given for general guidelines only to enable the user to get a “ball park” indication of part capabilities. The data are extracted from single
pulse transient thermal impedance characteristics which are developed from empirical measurements. The latter is valid for the part
mounted on printed circuit board - FR4, size 1" x 1" x 0.062", double sided with 2 oz. copper, 100 % on both sides. The part capabilities
can widely vary depending on actual application parameters and operating conditions.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?66714.
S11-2124-Rev. B, 07-Nov-11
6
Document Number: 66714
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
TSOP: 5/6−LEAD
JEDEC Part Number: MO-193C
e1
e1
5
4
6
E1
1
2
5
4
E
E1
1
3
2
3
-B-
e
b
E
-B-
e
0.15 M C B A
5-LEAD TSOP
b
0.15 M C B A
6-LEAD TSOP
4x 1
-A-
D
0.17 Ref
c
R
R
A2 A
L2
Gauge Plane
Seating Plane
Seating Plane
0.08
C
L
A1
-C-
(L1)
4x 1
MILLIMETERS
Dim
A
A1
A2
b
c
D
E
E1
e
e1
L
L1
L2
R
Min
Nom
Max
Min
Nom
Max
0.91
-
1.10
0.036
-
0.043
0.01
-
0.10
0.0004
-
0.004
0.90
-
1.00
0.035
0.038
0.039
0.30
0.32
0.45
0.012
0.013
0.018
0.10
0.15
0.20
0.004
0.006
0.008
2.95
3.05
3.10
0.116
0.120
0.122
2.70
2.85
2.98
0.106
0.112
0.117
1.55
1.65
1.70
0.061
0.065
0.067
0.95 BSC
0.0374 BSC
1.80
1.90
2.00
0.071
0.075
0.079
0.32
-
0.50
0.012
-
0.020
0.60 Ref
0.024 Ref
0.25 BSC
0.010 BSC
0.10
-
-
0.004
-
-
0
4
8
0
4
8
7 Nom
1
ECN: C-06593-Rev. I, 18-Dec-06
DWG: 5540
Document Number: 71200
18-Dec-06
INCHES
7 Nom
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AN823
Vishay Siliconix
Mounting LITTLE FOOTR TSOP-6 Power MOSFETs
Surface mounted power MOSFET packaging has been based on
integrated circuit and small signal packages. Those packages
have been modified to provide the improvements in heat transfer
required by power MOSFETs. Leadframe materials and design,
molding compounds, and die attach materials have been
changed. What has remained the same is the footprint of the
packages.
The basis of the pad design for surface mounted power MOSFET
is the basic footprint for the package. For the TSOP-6 package
outline drawing see http://www.vishay.com/doc?71200 and see
http://www.vishay.com/doc?72610 for the minimum pad footprint.
In converting the footprint to the pad set for a power MOSFET, you
must remember that not only do you want to make electrical
connection to the package, but you must made thermal connection
and provide a means to draw heat from the package, and move it
away from the package.
In the case of the TSOP-6 package, the electrical connections are
very simple. Pins 1, 2, 5, and 6 are the drain of the MOSFET and
are connected together. For a small signal device or integrated
circuit, typical connections would be made with traces that are
0.020 inches wide. Since the drain pins serve the additional
function of providing the thermal connection to the package, this
level of connection is inadequate. The total cross section of the
copper may be adequate to carry the current required for the
application, but it presents a large thermal impedance. Also, heat
spreads in a circular fashion from the heat source. In this case the
drain pins are the heat sources when looking at heat spread on the
PC board.
Since surface mounted packages are small, and reflow soldering
is the most common form of soldering for surface mount
components, “thermal” connections from the planar copper to the
pads have not been used. Even if additional planar copper area is
used, there should be no problems in the soldering process. The
actual solder connections are defined by the solder mask
openings. By combining the basic footprint with the copper plane
on the drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low impedance
path for heat to move away from the device.
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder reflow
reliability requirements. Devices are subjected to solder reflow as a
test preconditioning and are then reliability-tested using
temperature cycle, bias humidity, HAST, or pressure pot. The
solder reflow temperature profile used, and the temperatures and
time duration, are shown in Figures 2 and 3.
Figure 1 shows the copper spreading recommended footprint for
the TSOP-6 package. This pattern shows the starting point for
utilizing the board area available for the heat spreading copper. To
create this pattern, a plane of copper overlays the basic pattern on
pins 1,2,5, and 6. The copper plane connects the drain pins
electrically, but more importantly provides planar copper to draw
heat from the drain leads and start the process of spreading the
heat so it can be dissipated into the ambient air. Notice that the
planar copper is shaped like a “T” to move heat away from the
drain leads in all directions. This pattern uses all the available area
underneath the body for this purpose.
0.167
4.25
0.074
1.875
0.014
0.35
0.122
3.1
0.026
0.65
0.049
1.25
0.049
1.25
0.010
0.25
FIGURE 1. Recommended Copper Spreading Footprint
Document Number: 71743
27-Feb-04
Ramp-Up Rate
+6_C/Second Maximum
Temperature @ 155 " 15_C
120 Seconds Maximum
Temperature Above 180_C
70 − 180 Seconds
Maximum Temperature
240 +5/−0_C
Time at Maximum Temperature
20 − 40 Seconds
Ramp-Down Rate
+6_C/Second Maximum
FIGURE 2. Solder Reflow Temperature Profile
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1
AN823
Vishay Siliconix
10 s (max)
255 − 260_C
1X4_C/s (max)
3-6_C/s (max)
217_C
140 − 170_C
60 s (max)
60-120 s (min)
Pre-Heating Zone
3_C/s (max)
Reflow Zone
Maximum peak temperature at 240_C is allowed.
FIGURE 3. Solder Reflow Temperature and Time Durations
THERMAL PERFORMANCE
TABLE 1.
Equivalent Steady State Performance—TSOP-6
Thermal Resistance Rqjf
30_C/W
On-Resistance vs. Junction Temperature
1.6
VGS = 4.5 V
ID = 6.1 A
1.4
rDS(on) − On-Resiistance
(Normalized)
A basic measure of a device’s thermal performance is the
junction-to-case thermal resistance, Rqjc, or the
junction-to-foot thermal resistance, Rqjf. This parameter is
measured for the device mounted to an infinite heat sink and
is therefore a characterization of the device only, in other
words, independent of the properties of the object to which the
device is mounted. Table 1 shows the thermal performance
of the TSOP-6.
1.2
1.0
0.8
0.6
−50
SYSTEM AND ELECTRICAL IMPACT OF
TSOP-6
−25
0
25
50
75
100
125
150
TJ − Junction Temperature (_C)
FIGURE 4. Si3434DV
In any design, one must take into account the change in
MOSFET rDS(on) with temperature (Figure 4).
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Document Number: 71743
27-Feb-04
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR TSOP-6
0.099
0.039
0.020
0.019
(1.001)
(0.508)
(0.493)
0.064
(1.626)
0.028
(0.699)
(3.023)
0.119
(2.510)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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Document Number: 72610
Revision: 21-Jan-08
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Vishay
Disclaimer
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product with the properties described in the product specification is suitable for use in a particular application. Parameters
provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
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including but not limited to the warranty expressed therein.
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Document Number: 91000
Revision: 11-Mar-11
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