Preliminary Technical Data 800 MHz Clock Distribution IC,1.5 GHz Inputs, Dividers, Delay Adjust, Five Outputs AD9512 FEATURES Two 1.5 GHz, differential clock inputs 5 programmable dividers, 1 to 32, all integers Phase select for output-to-output coarse delay adjust 3 independent 800 MHz LVPECL outputs Additive output jitter 225 fs rms 2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs Additive output jitter 275 fs rms Fine delay adjust on 1 output, 6-bit delay word 4-wire or 3-wire serial control port Space-saving, 48-lead LFCSP FUNCTIONAL BLOCK DIAGRAM VS FUNCTION DSYNC DSYNCB SYNCB, RESETB PDB DETECT SYNC GND RSET VREF AD9512 SYNC STATUS PROGRAMMABLE DIVIDERS & PHASE ADJUST STATUS LVPECL OUT0 /1,/2,/3 ... /31,/32 OUT0B LVPECL OUT1 /1,/2,/3 ... /31,/32 OUT1B CLK1 LVPECL CLK1B OUT2 /1,/2,/3 ... /31,/32 OUT2B CLK2 CLK2B LVDS/CMOS OUT3 /1,/2,/3 ... /31,/32 APPLICATIONS Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDS, DDC, DUC, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure GENERAL DESCRIPTION The AD9512 provides a multi-output clock distribution in a design that emphasizes low jitter and phase noise in order to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. SCLK SDIO SDO CSB SERIAL CONTROL PORT OUT3B DELAY ADJUST LVDS/CMOS /1,/2,/3 ... /31,/32 ∆T OUT4 OUT4B Figure 1. The AD9512 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter. The AD9512 is available in a 48-lead LFCSP and may be operated from a single 3.3 V supply. The temperature range is −40°C to +85°C. There are five independent clock outputs. Three outputs are LVPECL, and two are selectable as either LVDS or CMOS levels. The LVPECL and LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz. Each output has a programmable divider, which may be bypassed or set to divide by any integer up to 32. The phase of one clock output relative to another clock output may be varied by means of a divider phase select function that serves as a coarse timing adjustment. One of the LVDS/CMOS outputs also features a programmable delay element with a range of up to 10 ns of delay. This fine tuning delay block has 6-bit resolution, giving 64 possible delays from which to choose. Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD9512 Preliminary Technical Data DSYNC 37 GND 38 GND 39 VS 40 VS 41 OUT0B 42 OUT0 43 GND 44 VS 45 RSET 46 GND 47 VS 48 VS PIN CONFIGURATION 1 36 VS pin 1 indicator DSYNCB 2 VS 3 VS 4 DNC 5 VS 6 35 OUT3 34 OUT3B AD9512 Top View (Not to scale) 48-lead LFCSP 7 x 7 x 0.85 CLK2 7 CLK2B 8 33 VS 32 VS 31 OUT4 30 OUT4B 29 VS GND 24 VS 23 22 VS SDIO STATUS 13 OUT2 21 VS OUT2B 20 25 19 FUNCTION 12 GND OUT1B 18 26 VS 11 17 CLK1B CSB OUT1 SDO 16 27 15 28 VS 10 VS SCLK 14 9 CLK1 Figure 2. Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be attached to ground, GND. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05287-0-11/04(PrA) Rev. 0 | Page 2 of 2