Less than 20fsRMS Additive Jitter Clock Distribution Solution with EZSync

Less than 20fsRMS Additive Jitter
Clock Distribution Solution with EZSync
Up to
1.8GHz
DEL
0-63
SYNC
EZSYNC
LTC6954
DIV
1-63
DEL
0-63
DIV
1-63
DEL
0-63
DIV
1-63
LVPECL,
LVDS
or
CMOS
Ultralow Additive Jitter for Uncompromised Data Converter SNR Performance
With less than 20fsRMS additive jitter over the 12kHz to 20MHz bandwidth, the LTC®6954 is ideal for distributing the low jitter clocks
necessary to achieve the best SNR when driving high resolution data converters. Besides minimizing jitter, the LTC6954 features
EZSyncTM synchronization method that guarantees repeatable edge-synchronized outputs from one or multiple chips.
Features
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Three Independent, Low Noise Outputs
Additive Jitter < 20fsRMS (12kHz to 20MHz)
Additive Jitter < 85fsRMS (10Hz to Nyquist)
Up to 1.8GHz Maximum Input Frequency
EZSync Clock Synchronization Compatible
Clock Dividers Covering All Integers from 1 to 63
Phase Delays Covering All Integers from 0 to 63
–40°C to 105°C Junction Temperature Range
Part Number Description
LTC6954-1
3 LVPECL Outputs
LTC6954-2
2 LVPECL and 1 LVDS/CMOS Outputs
LTC6954-3
1 LVPECL and 2 LVDS/CMOS Outputs
LTC6954-4
3 LVDS/CMOS Outputs
LVPECL Output Additive Phase Noise,
fIN = 622.08MHz
–120
ADDITIVE PHASE NOISE (dBc/Hz)
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SINGLE-ENDED SINE WAVE INPUT
+7dBm AT 622.08MHz
–130
–140
–150
DIV = 1
–160
DIV = 4
–170
–180
DIV = 16
10
L, LT, LTC, LTM, Linear Technology and the Linear logo are
registered trademarks and EZSync is a trademark of Linear
Technology Corporation. All other trademarks are the property of
their respective owners.
100
1k
10k 100k
1M
OFFSET FREQUENCY (Hz)
10M
EZSync Multichip Synchronization Simplifies the Generation
of Repeatable Edge-Synchronized Outputs
REF
PLL
VCO
SYNC
EZSYNC
LTC6950
DEL
0-63
DIV
1-63
PECL0
DEL
0-63
DIV
1-63
PECL1
DEL
0-63
DIV
1-63
PECL2
DEL
0-63
DIV
1-63
PECL3
DEL
0-63
DIV
1-63
LVDS/
CMOS
EZSYNC
LTC6954
DEL
0-63
DIV
1-63
OUT0
DEL
0-63
DIV
1-63
OUT1
DEL
0-63
DIV
1-63
OUT2
With EZSync Enabled and the PECL0 Output of the LTC6950 Driving the LTC6954 Input,
All Seven Outputs of the Two Devices Are Rising-Edge Synchronized
EZSync Disabled:
Random Phase Relationship Between the Outputs
of the LTC6950 and LTC6954 Clock Dividers
EZSync Enabled:
Repeatable Rising-Edge Aligned Outputs
of the LTC6950 and LTC6954 Clock Dividers
LTC6950, PECL1
LTC6954, OUT0
LTC6954, OUT1
LTC6954, OUT2
2.5ns/DIV
2.5ns/DIV
www.linear.com/6954 n 1-800-4-LINEAR
1015