TI TLC272AID

TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
D Trimmed Offset Voltage:
D
D
D
D
D
D
D
D
1OUT
1IN –
1IN +
GND
1
8
2
7
3
6
4
5
VDD
2OUT
2IN –
2IN +
FK PACKAGE
(TOP VIEW)
NC
1OUT
NC
VDD
NC
D
TLC277 . . . 500 µV Max at 25°C,
VDD = 5 V
Input Offset Voltage Drift . . . Typically
0.1 µV/Month, Including the First 30 Days
Wide Range of Supply Voltages Over
Specified Temperature Range:
0°C to 70°C . . . 3 V to 16 V
– 40°C to 85°C . . . 4 V to 16 V
– 55°C to 125°C . . . 4 V to 16 V
Single-Supply Operation
Common-Mode Input Voltage Range
Extends Below the Negative Rail (C-Suffix,
I-Suffix types)
Low Noise . . . Typically 25 nV/√Hz at
f = 1 kHz
Output Voltage Range Includes Negative
Rail
High Input impedance . . . 1012 Ω Typ
ESD-Protection Circuitry
Small-Outline Package Option Also
Available in Tape and Reel
Designed-In Latch-Up Immunity
NC
1IN –
NC
1IN +
NC
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
NC
2OUT
NC
2IN –
NC
NC
GND
NC
2IN +
NC
D
D, JG, P, OR PW PACKAGE
(TOP VIEW)
NC – No internal connection
description
The TLC272 and TLC277 precision dual
operational amplifiers combine a wide range of
input offset voltage grades with low offset voltage
drift, high input impedance, low noise, and speeds
approaching those of general-purpose BiFET
devices.
The extremely high input impedance, low bias
currents, and high slew rates make these costeffective devices ideal for applications previously
reserved for BiFET and NFET products. Four
offset voltage grades are available (C-suffix and
I-suffix types), ranging from the low-cost TLC272
(10 mV) to the high-precision TLC277 (500 µV).
These advantages, in combination with good
common-mode rejection and supply voltage
rejection, make these devices a good choice for
new state-of-the-art designs as well as for
upgrading existing designs.
30
25
Percentage of Units – %
These devices use Texas Instruments silicongate LinCMOS technology, which provides
offset voltage stability far exceeding the stability
available with conventional metal-gate processes.
DISTRIBUTION OF TLC277
INPUT OFFSET VOLTAGE
473 Units Tested From 2 Wafer Lots
VDD = 5 V
TA = 25°C
P Package
20
15
10
5
0
– 800
– 400
0
400
VIO – Input Offset Voltage – µV
800
LinCMOS is a trademark of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
description (continued)
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
VIOmax
AT 25°C
SMALL
OUTLINE
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
(JG)
PLASTIC
DIP
(P)
TSSOP
(PW)
CHIP
FORM
(Y)
0°C to 70°c
500 µV
2 mV
5 mV
10mV
TLC277CD
TLC272BCD
TLC272ACD
TLC272CD
—
—
—
—
—
—
—
—
TLC277CP
TLC272BCP
TLC272ACP
TLC272CP
—
—
—
TLC272CPW
—
—
—
TLC272Y
– 40°C to 85°C
500 µV
2 mV
5 mV
10 mV
TLC277ID
TLC272BID
TLC272AID
TLC272ID
—
—
—
—
—
—
—
—
TLC277IP
TLC272BIP
TLC272AIP
TLC272IP
—
—
—
—
—
—
—
—
The D package is available taped and reeled. Add R suffix to the device type (e.g., TLC277CDR).
In general, many features associated with bipolar technology are available on LinCMOS operational amplifiers
without the power penalties of bipolar technology. General applications such as transducer interfacing, analog
calculations, amplifier blocks, active filters, and signal buffering are easily designed with the TLC272 and
TLC277. The devices also exhibit low voltage single-supply operation, making them ideally suited for remote
and inaccessible battery-powered applications. The common-mode input voltage range includes the negative
rail.
A wide range of packaging options is available, including small-outline and chip carrier versions for high-density
system applications.
The device inputs and outputs are designed to withstand –100-mA surge currents without sustaining latch-up.
The TLC272 and TLC277 incorporate internal ESD-protection circuits that prevent functional failures at voltages
up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling
these devices as exposure to ESD may result in the degradation of the device parametric performance.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from – 40°C to 85°C. The M-suffix devices are characterized for operation over the full military
temperature range of – 55°C to 125°C.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
equivalent schematic (each amplifier)
VDD
P3
P4
R6
R1
N5
R2
IN –
P5
P1
P6
P2
IN +
R5
C1
OUT
N3
N1
R3
N2
D1
N4
R4
D2
N6
N7
R7
GND
TLC272Y chip information
This chip, when properly assembled, displays characteristics similar to the TLC272C. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
1IN +
(3)
(2)
1IN –
2OUT
VDD
(8)
+
(1)
+
(7)
–
60
1OUT
–
(5)
(6)
2IN +
2IN –
(4)
GND
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ± 10%.
ALL DIMENSIONS ARE IN MILS.
73
POST OFFICE BOX 655303
PIN (4) IS INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
• DALLAS, TEXAS 75265
3
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VDD
Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD
Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
output current, IO (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 30 mA
Total current into VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA
Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA
Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, P, or PW package . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN –.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded (see application section).
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D
725 mW
5.8 mW/°C
464 mW
377 mW
N/A
FK
1375 mW
11 mW/°C
880 mW
715 mW
275 mW
JG
1050 mW
8.4 mW/°C
672 mW
546 mW
210 mW
P
1000 mW
8.0 mW/°C
640 mW
520 mW
N/A
PW
525 mW
4.2 mW/°C
336 mW
N/A
N/A
recommended operating conditions
Supply voltage, VDD
Common mode input voltage,
Common-mode
voltage VIC
VDD = 5 V
VDD = 10 V
Operating free-air temperature, TA
4
POST OFFICE BOX 655303
C SUFFIX
I SUFFIX
M SUFFIX
MIN
MAX
MIN
MAX
MIN
MAX
3
16
4
16
4
16
– 0.2
3.5
– 0.2
3.5
0
3.5
– 0.2
8.5
– 0.2
8.5
0
8.5
0
70
– 40
85
– 55
125
• DALLAS, TEXAS 75265
UNIT
V
V
°C
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC272C, TLC272AC,
TLC272BC, TLC277C
MIN
VIO
TLC272C
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
TLC272AC
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
Input offset voltage
TLC272BC
TLC277C
αVIO
Temperature coefficient of input offset voltage
IIO
Input offset current (see Note 4)
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
2 5 V,
V
VO = 2.5
IIB
VICR
VOH
VOL
AVD
CMRR
kSVR
IDD
25V
VIC = 2.5
Input bias current (see Note 4)
25°C
VID = 100 mV,
Low-level
Low
level out
output
ut voltage
VID = –100
100 mV,
Large-signal
Large
signal differential voltage am
amplification
lification
Common-mode
Common
mode rejection ratio
VO = 0.25 V to 2 V,
RL = 10 kΩ
IOL = 0
RL = 10 kΩ
VIC = VICRmin
Supply-voltage
S
l
lt
rejection
j ti ratio
ti
(∆VDD /∆VIO)
VDD = 5 V to 10 V,
Supply
y current ((two amplifiers))
VO = 2.5
2 5 V,
V
No load
VO = 1.4 V
VIC = 2.5
2 5 V,
V
MAX
1.1
10
Full range
UNIT
12
25°C
0.9
5
230
2000
Full range
mV
6.5
25°C
Full range
3000
25°C
200
Full range
500
µV
V
1500
25°C to
70°C
1.8
25°C
0.1
60
70°C
7
300
25°C
0.6
60
70°C
40
600
25°C
– 0.2
to
4
Full range
– 0.2
to
3.5
25°C
3.2
3.8
0°C
3
3.8
70°C
3
3.8
Common mode in
Common-mode
input
ut voltage range
(see Note 5)
High-level
output
High
level out
ut voltage
TYP
µV/°C
– 0.3
to
4.2
pA
pA
V
V
V
25°C
0
50
0°C
0
50
70°C
0
50
25°C
5
23
0°C
4
27
70°C
4
20
25°C
65
80
0°C
60
84
70°C
60
85
25°C
65
95
0°C
60
94
70°C
60
96
mV
V/mV
dB
dB
25°C
1.4
3.2
0°C
1.6
3.6
70°C
1.2
2.6
mA
† Full range is 0°C to 70°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC272C, TLC272AC,
TLC272BC, TLC277C
MIN
VIO
TLC272C
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
TLC272AC
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
Input offset voltage
TLC272BC
TLC277C
αVIO
Temperature coefficient of input offset voltage
IIO
Input offset current (see Note 4)
VO = 1.4 V,
RS = 50 Ω,
VO = 1.4 V,
RS = 50 Ω,
VICR
VOH
VOL
AVD
CMRR
kSVR
IDD
VIC = 0,
RL = 10 kΩ
VIC = 5 V
Input bias current (see Note 4)
VID = 100 mV,
Low-level
Low
level out
output
ut voltage
VID = –100
100 mV,
Large-signal
Large
signal differential voltage am
amplification
lification
Common-mode
Common
mode rejection ratio
VO = 1 V to 6 V,
RL = 10 kΩ
IOL = 0
RL = 10 kΩ
VIC = VICRmin
Supply-voltage
S
l
lt
rejection
j ti ratio
ti
(∆VDD /∆VIO)
VDD = 5 V to 10 V,
Supply
y current ((two amplifiers))
VO = 5 V,
V
No load
VO = 1.4 V
VIC = 5 V,
V
1.1
10
0.9
5
290
2000
Full range
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
mV
6.5
25°C
Full range
3000
25°C
250
Full range
800
µV
V
1900
µV/°C
2
25°C
0.1
60
70°C
7
300
25°C
0.7
60
70°C
50
600
25°C
– 0.2
to
9
Full range
– 0.2
to
8.5
– 0.3
to
9.2
pA
pA
V
V
25°C
8
8.5
0°C
7.8
8.5
70°C
7.8
8.4
V
25°C
0
50
0°C
0
50
70°C
0
50
25°C
10
36
0°C
7.5
42
70°C
7.5
32
25°C
65
85
0°C
60
88
70°C
60
88
25°C
65
95
0°C
60
94
70°C
60
96
mV
V/mV
dB
dB
25°C
1.9
4
0°C
2.3
4.4
70°C
1.6
3.4
† Full range is 0°C to 70°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
6
UNIT
12
25°C
Common mode in
Common-mode
input
ut voltage range
(see Note 5)
High-level
output
High
level out
ut voltage
MAX
Full range
25°C to
70°C
V
VO = 5 V,
IIB
VIC = 0,
RL = 10 kΩ
25°C
TYP
mA
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC272I, TLC272AI,
TLC272BI, TLC277I
MIN
VIO
TLC272I
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
TLC272AI
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
Input offset voltage
TLC272BI
TLC277I
αVIO
Temperature coefficient of input offset voltage
IIO
Input offset current (see Note 4)
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
2 5 V,
V
VO = 2.5
IIB
25V
VIC = 2.5
Input bias current (see Note 4)
25°C
VOL
AVD
CMRR
kSVR
VID = 100 mV,
Low-level
Low
level out
output
ut voltage
VID = –100
100 mV,
L
Large-signal
i
l differential
diff
ti l voltage
lt
amplification
lifi ti
Common-mode
Common
mode rejection ratio
VO = 1 V to 6 V,
RL = 10 kΩ
IOL = 0
RL = 10 kΩ
VIC = VICRmin
S
l
lt
j ti ratio
ti
Supply-voltage
rejection
(∆VDD /∆VIO)
VDD = 5 V to 10 V,
Supply
y current ((two amplifiers))
VO = 2.5
2 5 V,
V
No load
VO = 1.4 V
10
0.9
5
230
2000
Full range
Full range
3500
200
25°C
Full range
500
25°C to
85°C
1.8
25°C
0.1
60
85°C
24
15
25°C
0.6
60
85°C
200
35
– 0.2
to
4
µV/°C
– 0.3
to
4.2
– 0.2
to
3.5
25°C
3.2
3.8
– 40°C
3
3.8
85°C
3
3.8
V
25°C
0
50
– 40°C
0
50
85°C
0
50
25°C
5
23
– 40°C
3.5
32
85°C
3.5
19
25°C
65
80
– 40°C
60
81
85°C
60
86
25°C
65
95
– 40°C
60
92
85°C
60
96
mV
V/mV
dB
dB
3.2
1.9
4.4
1.1
85°C
† Full range is – 40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
2.4
• DALLAS, TEXAS 75265
pA
V
1.4
POST OFFICE BOX 655303
pA
V
25°C
VIC = 2.5
2 5 V,
V
µV
V
2000
– 40°C
IDD
mV
7
25°C
Common mode in
Common-mode
input
ut voltage range
(see Note 5)
High-level
High
level out
output
ut voltage
1.1
UNIT
13
25°C
Full range
VOH
MAX
Full range
25°C
VICR
TYP
mA
7
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA†
TLC272I, TLC272AI,
TLC272BI, TLC277I
MIN
VIO
TLC272I
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
TLC272AI
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
Input offset voltage
TLC272BI
TLC277I
αVIO
Temperature coefficient of input offset voltage
IIO
Input offset current (see Note 4)
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
VICR
VOH
VOL
AVD
CMRR
kSVR
VIC = 5 V
Input bias current (see Note 4)
VID = 100 mV,
Low-level
Low
level out
output
ut voltage
VID = –100
100 mV,
Large-signal
amplification
Large
signal differential voltage am
lification
Common-mode
Common
mode rejection ratio
VO = 1 V to 6 V,
RL = 10 kΩ
IOL = 0
RL = 10 kΩ
VIC = VICRmin
S
l
lt
j ti ratio
ti
Supply-voltage
rejection
(∆VDD /∆VIO)
VDD = 5 V to 10 V,
Supply
y current ((two amplifiers))
VO = 5 V,
V
No load
VO = 1.4 V
1.1
10
0.9
5
290
2000
Full range
Full range
3500
250
25°C
Full range
800
µV/°C
2
25°C
0.1
60
85°C
26
1000
25°C
0.7
60
85°C
220
2000
25°C
– 0.2
to
9
Full range
– 0.2
to
8.5
– 0.3
to
9.2
25°C
8
8.5
– 40°C
7.8
8.5
85°C
7.8
8.5
V
25°C
0
50
– 40°C
0
50
85°C
0
50
25°C
10
36
– 40°C
7
46
85°C
7
31
25°C
65
85
– 40°C
60
87
85°C
60
88
25°C
65
95
– 40°C
60
92
85°C
60
96
mV
V/mV
dB
dB
4
5
1.5
85°C
† Full range is – 40°C to 85°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
3.2
• DALLAS, TEXAS 75265
pA
V
2.8
POST OFFICE BOX 655303
pA
V
1.4
8
µV
V
2900
25°C
VIC = 5 V,
V
mV
7
25°C
– 40°C
IDD
UNIT
13
25°C
Common mode in
Common-mode
input
ut voltage range
(see Note 5)
High-level
High
level out
output
ut voltage
MAX
Full range
25°C to
85°C
V
VO = 5 V,
IIB
25°C
TYP
mA
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
VIO
TEST CONDITIONS
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
Full range
TLC277M
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
Full range
Input offset voltage
Temperature coefficient of input offset
voltage
IIO
Input offset current (see Note 4)
VO = 2.5
25V
VIC = 2.5
25V
Input bias current (see Note 4)
VOL
AVD
CMRR
kSVR
Low-level
Low
level out
output
ut voltage
VID = – 100 mV,
Large-signal
Large
signal differential voltage am
amplification
lification
Common-mode
Common
mode rejection ratio
Supply-voltage
S
l
lt
rejection
j ti ratio
ti
(∆VDD /∆VIO)
VO = 0.25 V to 2 V
RL = 10 kΩ
IOL = 0
RL = 10 kΩ
VIC = VICRmin
VDD = 5 V to 10 V,
VO = 1.4 V
1.1
10
200
500
3750
2.1
0.1
60
pA
1.4
15
nA
25°C
0.6
60
pA
9
35
nA
0
to
4
– 0.3
to
4.2
V
0
to
3.5
V
25°C
3.2
3.8
– 55°C
3
3.8
125°C
3
3.8
V
25°C
0
50
– 55°C
0
50
125°C
0
50
25°C
5
23
– 55°C
3.5
35
125°C
3.5
16
25°C
65
80
– 55°C
60
81
125°C
60
84
25°C
65
95
– 55°C
60
90
125°C
60
dB
dB
97
3.2
2
5
1
125°C
† Full range is – 55°C to 125°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
2.2
POST OFFICE BOX 655303
VIC = 2.5
2 5 V,
V
• DALLAS, TEXAS 75265
mV
V/mV
– 55°C
VO = 2.5
2 5 V,
V
No load
µV
V
25°C
1.4
Supply
y current ((two amplifiers))
mV
µV/°C
25°C
IDD
UNIT
125°C
Common mode in
Common-mode
input
ut voltage range
(see Note 5)
VID = 100 mV,
MAX
12
125°C
High-level
High
level out
output
ut voltage
TYP
25°C to
125°C
Full range
VOH
MIN
25°C
25°C
VICR
TLC272M, TLC277M
25°C
TLC272M
αVIO
IIB
TA†
mA
9
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted)
PARAMETER
VIO
TEST CONDITIONS
TLC272M
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
Full range
TLC277M
VO = 1.4 V,
RS = 50 Ω,
VIC = 0,
RL = 10 kΩ
Full range
Input offset voltage
αVIO
Temperature coefficient of input offset
voltage
IIO
Input offset current (see Note 4)
VO = 5 V,
V
IIB
VICR
VOH
VOL
AVD
CMRR
kSVR
TA†
VIC = 5 V
Input bias current (see Note 4)
Low-level
Low
level out
output
ut voltage
Large-signal
L
i
l differential
diff
ti l voltage
lt
amplification
Common-mode
Common
mode rejection ratio
VID = – 100 mV,
VO = 1 V to 6 V,
RL = 10 kΩ
IOL = 0
RL = 10 kΩ
VIC = VICRmin
S
l
lt
j ti ratio
ti
Supply-voltage
rejection
(∆VDD /∆VIO)
VDD = 5 V to 10 V,
Supply
y current ((two amplifiers))
VO = 5 V,
V
No load
VO = 1.4 V
VIC = 5 V,
V
MAX
1.1
10
250
25°C to
125°C
2.2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
mV
µV
V
µV/°C
25°C
0.1
60
pA
125°C
1.8
15
nA
25°C
0.7
60
pA
10
35
nA
25°C
0
to
9
Full range
0
to
8.5
– 0.3
to
9.2
V
V
25°C
8
8.5
– 55°C
7.8
8.5
125°C
7.8
8.4
V
25°C
0
50
– 55°C
0
50
125°C
0
50
25°C
10
36
– 55°C
7
50
125°C
7
27
25°C
65
85
– 55°C
60
87
125°C
60
86
25°C
65
95
– 55°C
60
90
125°C
60
97
1.9
mV
V/mV
dB
dB
4
– 55°C
3
6
125°C
1.3
2.8
† Full range is – 55°C to 125°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
10
800
4300
125°C
VID = 100 mV,
TYP
12
25°C
25°C
IDD
MIN
25°C
Common mode in
Common-mode
input
ut voltage range
(see Note 5)
High-level
High
level out
output
ut voltage
TLC272M, TLC277M
mA
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
electrical characteristics, VDD = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
VIO
Input offset voltage
αVIO
TEST CONDITIONS
VO = 1.4 V,
RS = 50 Ω,
TLC272Y
MIN
VIC = 0,
RL = 10 kΩ
TYP
MAX
11
1.1
10
UNIT
mV
Temperature coefficient of input offset voltage
1.8
µV/°C
IIO
IIB
Input offset current (see Note 4)
0.1
pA
0.6
pA
VICR
Common-mode input voltage range (see Note 5)
– 0.2
to
4
– 0.3
to
4.2
V
VOH
VOL
High-level output voltage
3.2
3.8
AVD
CMRR
Large-signal differential voltage amplification
kSVR
Supply-voltage rejection ratio (∆VDD /∆VIO)
IDD
Supply current (two amplifiers)
2 5 V,
V
VO = 2.5
Input bias current (see Note 4)
VID = 100 mV,
VID = –100 mV,
Low-level output voltage
Common-mode rejection ratio
VO = 0.25 V to 2 V
VIC = VICRmin
VDD = 5 V to 10 V,
VO = 2.5 V,
No load
25V
VIC = 2.5
RL = 10 kΩ
IOL = 0
RL = 10 kΩ
VO = 1.4 V
VIC = 2.5 V,
0
V
50
mV
5
23
V/mV
65
80
dB
65
95
dB
1.4
3.2
mA
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
electrical characteristics, VDD = 10 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VO = 1.4 V,
RS = 50 Ω,
TLC272Y
MIN
VIC = 0,
RL = 10 kΩ
TYP
MAX
11
1.1
10
UNIT
VIO
Input offset voltage
αVIO
Temperature coefficient of input offset voltage
1.8
µV/°C
IIO
IIB
Input offset current (see Note 4)
0.1
pA
VO = 5 V,
V
Input bias current (see Note 4)
VICR
Common-mode input voltage range (see Note 5)
VOH
VOL
High-level output voltage
AVD
CMRR
Large-signal differential voltage amplification
kSVR
Supply-voltage rejection ratio (∆VDD /∆VIO)
IDD
Supply current (two amplifiers)
VID = 100 mV,
VID = –100 mV,
Low-level output voltage
Common-mode rejection ratio
VO = 1 V to 6 V,
VIC = VICRmin
VDD = 5 V to 10 V,
VO = 5 V,
No load
VIC = 5 V
RL = 10 kΩ
IOL = 0
RL = 10 kΩ
VO = 1.4 V
VIC = 5 V,
mV
0.7
pA
– 0.2
to
9
– 0.3
to
9.2
V
8
8.5
0
V
50
mV
10
36
V/mV
65
85
dB
65
95
dB
1.9
4
mA
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLC272C, TLC272AC,
TLC272BC, TLC277C
MIN
VIPP = 1 V
SR
Slew rate at unity gain
RL = 10 kΩ,
pF,
CL = 20 pF
See Figure 1
VIPP = 2.5 V
Vn
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
RS = 20 Ω,
BOM
Maximum out
output-swing
ut swing bandwidth
VO = VOH,
RL = 10 kΩ,
kΩ
CL = 20 pF,
F
See Figure 1
B1
φm
Unity-gain
Unity
gain bandwidth
Phase margin
g
VI = 10 mV,
V
See Figure 3
VI = 10 mV,
V
CL = 20 pF
pF,
CL = 20 pF,
F
f = B1,
See Figure 3
TYP
25°C
3.6
0°C
4
70°C
3
25°C
2.9
0°C
3.1
70°C
2.5
25°C
25
25°C
320
0°C
340
70°C
260
25°C
1.7
0°C
2
70°C
1.3
25°C
46°
0°C
47°
70°C
43°
UNIT
MAX
V/ s
V/µs
nV/√Hz
kHz
MHz
operating characteristics at specified free-air temperature, VDD = 10 V
PARAMETER
TEST CONDITIONS
TA
TLC272C, TLC272AC,
TLC272BC, TLC277C
MIN
VIPP = 1 V
SR
Slew rate at unity gain
RL = 10 kΩ,
pF,
CL = 20 pF
See Figure 1
VIPP = 5.5 V
Vn
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
RS = 20 Ω,
BOM
Maximum out
output-swing
ut swing bandwidth
VO = VOH,
RL = 10 kΩ,
kΩ
F
CL = 20 pF,
See Figure 1
VI = 10 mV,
V
See Figure 3
CL = 20 pF,
F
B1
φm
12
Unity-gain
Unity
gain bandwidth
Phase margin
g
VI = 10 mV,
V
CL = 20 pF
pF,
POST OFFICE BOX 655303
f = B1,
See Figure 3
• DALLAS, TEXAS 75265
TYP
25°C
5.3
0°C
5.9
70°C
4.3
25°C
4.6
0°C
5.1
70°C
3.8
25°C
25
25°C
200
0°C
220
70°C
140
25°C
2.2
0°C
2.5
70°C
1.8
25°C
49°
0°C
50°
70°C
46°
UNIT
MAX
V/ s
V/µs
nV/√Hz
kHz
MHz
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
TA
TLC272I, TLC272AI,
TLC272BI, TLC277I
MIN
VIPP = 1 V
SR
Slew rate at unity gain
RL = 10 kΩ,
pF,
CL = 20 pF
See Figure 1
VIPP = 2.5 V
Vn
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
RS = 20 Ω,
BOM
Maximum out
output-swing
ut swing bandwidth
VO = VOH,
RL = 10 kΩ,
kΩ
CL = 20 pF,
F
See Figure 1
VI = 10 mV,
V
See Figure 3
CL = 20 pF,
F
B1
φm
Unity-gain
Unity
gain bandwidth
Phase margin
g
VI = 10 mV,
V
CL = 20 pF
pF,
f = B1,
See Figure 3
TYP
25°C
3.6
– 40°C
4.5
85°C
2.8
25°C
2.9
– 40°C
3.5
85°C
2.3
25°C
25
25°C
320
– 40°C
380
85°C
250
25°C
1.7
– 40°C
2.6
85°C
1.2
25°C
46°
– 40°C
49°
85°C
43°
UNIT
MAX
V/ s
V/µs
nV/√Hz
kHz
MHz
operating characteristics at specified free-air temperature, VDD = 10 V
PARAMETER
TEST CONDITIONS
TA
TLC272I, TLC272AI,
TLC272BI, TLC277I
MIN
VIPP = 1 V
SR
Slew rate at unity gain
RL = 10 kΩ,
pF,
CL = 20 pF
See Figure 1
VIPP = 5.5 V
Vn
BOM
B1
φm
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
RS = 20 Ω,
Maximum out
output-swing
ut swing bandwidth
VO = VOH,
RL = 10 kΩ,
kΩ
F
CL = 20 pF,
See Figure 1
VI = 10 mV,
V
See Figure 3
CL = 20 pF,
F
Unity-gain
Unity
gain bandwidth
Phase margin
g
VI = 10 mV,
V
CL = 20 pF
pF,
POST OFFICE BOX 655303
f = B1,
See Figure 3
• DALLAS, TEXAS 75265
TYP
25°C
5.3
– 40°C
6.8
85°C
4
25°C
4.6
– 40°C
5.8
85°C
3.5
25°C
25
25°C
200
– 40°C
260
85°C
130
25°C
2.2
– 40°C
3.1
85°C
1.7
25°C
49°
– 40°C
52°
85°C
46°
UNIT
MAX
V/ s
V/µs
nV/√Hz
kHz
MHz
13
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TEST CONDITIONS
VIPP = 1 V
SR
Slew rate at unity gain
RL = 10 kΩ,
pF,
CL = 20 pF
See Figure 1
VIPP = 2.5 V
Vn
BOM
B1
φm
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
RS = 20 Ω,
Maximum out
output-swing
ut swing bandwidth
VO = VOH,
RL = 10 kΩ,
kΩ
F
CL = 20 pF,
See Figure 1
VI = 10 mV,
V
See Figure 3
CL = 20 pF,
F
Unity-gain
Unity
gain bandwidth
Phase margin
g
VI = 10 mV,
V
CL = 20 pF
pF,
f = B1,
See Figure 3
TA
TLC272M, TLC277M
MIN
TYP
25°C
3.6
– 55°C
4.7
125°C
2.3
25°C
2.9
– 55°C
3.7
125°C
2
25°C
25
25°C
320
– 55°C
400
125°C
230
25°C
1.7
– 55°C
2.9
125°C
1.1
25°C
46°
– 55°C
49°
125°C
41°
MAX
UNIT
V/ s
V/µs
nV/√Hz
kHz
MHz
operating characteristics at specified free-air temperature, VDD = 10 V
PARAMETER
TEST CONDITIONS
VIPP = 1 V
SR
Slew rate at unity gain
RL = 10 kΩ,
pF,
CL = 20 pF
See Figure 1
VIPP = 5.5 V
Vn
Equivalent input noise voltage
f = 1 kHz,
See Figure 2
RS = 20 Ω,
BOM
Maximum out
output-swing
ut swing bandwidth
VO = VOH,
RL = 10 kΩ,
kΩ
F
CL = 20 pF,
See Figure 1
B1
φm
14
Unity-gain
Unity
gain bandwidth
Phase margin
g
VI = 10 mV,
V
See Figure 3
VI = 10 mV,
V
CL = 20 pF
pF,
POST OFFICE BOX 655303
CL = 20 pF,
F
f = B1,
See Figure 3
• DALLAS, TEXAS 75265
TA
TLC272M, TLC277M
MIN
TYP
25°C
5.3
– 55°C
7.1
125°C
3.1
25°C
4.6
– 55°C
6.1
125°C
2.7
25°C
25
25°C
200
– 55°C
280
125°C
110
25°C
2.2
– 55°C
3.4
125°C
1.6
25°C
49°
– 55°C
52°
125°C
44°
MAX
UNIT
V/ s
V/µs
nV/√Hz
kHz
MHz
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
operating characteristics, VDD = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
MAX
UNIT
3.6
RS = 20 Ω,
See Figure 2
25
nV/√Hz
VO = VOH,
See Figure 1
CL = 20 pF,
RL = 10 kΩ,
320
kHz
VI = 10 mV,
VI = 10 mV,
See Figure 3
CL = 20 pF,
See Figure 3
1.7
MHz
f = B1,
CL = 20 pF,
46°
Slew rate at unity gain
RL = 10 kΩ,
See Figure 1
CL = 20 pF,
F,
Vn
Equivalent input noise voltage
f = 1 kHz,
BOM
Maximum output-swing bandwidth
B1
Unity-gain bandwidth
Phase margin
TYP
VIPP = 1 V
VIPP = 2.5 V
SR
φm
TLC272Y
MIN
V/ s
V/µs
2.9
operating characteristics, VDD = 10 V, TA = 25°C
PARAMETER
TEST CONDITIONS
UNIT
RS = 20 Ω,
See Figure 2
25
nV/√Hz
CL = 20 pF,
RL = 10 kΩ,
200
kHz
CL = 20 pF,
See Figure 3
2.2
MHz
f = B1,
CL = 20 pF,
49°
RL = 10 kΩ,
See Figure 1
CL = 20 pF,
F,
Vn
Equivalent input noise voltage
f = 1 kHz,
BOM
Maximum output-swing bandwidth
VO = VOH,
See Figure 1
B1
Unity-gain bandwidth
VI = 10 mV,
VI = 10 mV,
See Figure 3
POST OFFICE BOX 655303
MAX
5.3
Slew rate at unity gain
Phase margin
TYP
VIPP = 1 V
VIPP = 5.5 V
SR
φm
TLC272Y
MIN
• DALLAS, TEXAS 75265
4.6
V/ s
V/µs
15
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION
single-supply versus split-supply test circuits
Because the TLC272 and TLC277 are optimized for single-supply operation, circuit configurations used for the
various tests often present some inconvenience since the input signal, in many cases, must be offset from
ground. This inconvenience can be avoided by testing the device with split supplies and the output load tied to
the negative rail. A comparison of single-supply versus split-supply test circuits is shown below. The use of either
circuit gives the same result.
VDD
VDD +
–
–
VO
VO
+
CL
+
VI
VI
RL
CL
RL
VDD –
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 1. Unity-Gain Amplifier
2 kΩ
VDD
VDD +
–
–
20 Ω
2 kΩ
1/2 VDD
VO
VO
+
+
20 Ω
20 Ω
20 Ω
VDD –
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 2. Noise-Test Circuit
10 kΩ
VDD
VDD +
100 Ω
–
100 Ω
–
VI
10 kΩ
VI
VO
+
+
1/2 VDD
VO
CL
CL
VDD –
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 3. Gain-of-100 Inverting Amplifier
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION
input bias current
Because of the high input impedance of the TLC272 and TLC277 operational amplifiers, attempts to measure
the input bias current can result in erroneous readings. The bias current at normal room ambient temperature
is typically less than 1 pA, a value that is easily exceeded by leakages on the test socket. Two suggestions are
offered to avoid erroneous measurements:
1. Isolate the device from other potential leakage sources. Use a grounded shield around and between the
device inputs (see Figure 4). Leakages that would otherwise flow to the inputs are shunted away.
2. Compensate for the leakage of the test socket by actually performing an input bias current test (using
a picoammeter) with no device in the test socket. The actual input bias current can then be calculated
by subtracting the open-socket leakage readings from the readings obtained with a device in the test
socket.
One word of caution: many automatic testers as well as some bench-top operational amplifier testers use the
servo-loop technique with a resistor in series with the device input to measure the input bias current (the voltage
drop across the series resistor is measured and the bias current is calculated). This method requires that a
device be inserted into the test socket to obtain a correct reading; therefore, an open-socket reading is not
feasible using this method.
8
5
V = VIC
1
4
Figure 4. Isolation Metal Around Device Inputs
(JG and P packages)
low-level output voltage
To obtain low-supply-voltage operation, some compromise was necessary in the input stage. This compromise
results in the device low-level output being dependent on the common-mode input voltage level as well as the
differential input voltage level. When attempting to correlate low-level output readings with those quoted in the
electrical specifications, these two conditions should be observed. If conditions other than these are to be used,
please refer to Figures 14 through 19 in the Typical Characteristics of this data sheet.
input offset voltage temperature coefficient
Erroneous readings often result from attempts to measure temperature coefficient of input offset voltage. This
parameter is actually a calculation using input offset voltage measurements obtained at two different
temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device
and the test socket. This moisture results in leakage and contact resistance, which can cause erroneous input
offset voltage readings. The isolation techniques previously mentioned have no effect on the leakage since the
moisture also covers the isolation metal itself, thereby rendering it useless. It is suggested that these
measurements be performed at temperatures above freezing to minimize error.
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TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION
full-power response
Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage
swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is
generally measured by monitoring the distortion level of the output while increasing the frequency of a sinusoidal
input signal until the maximum frequency is found above which the output contains significant distortion. The
full-peak response is defined as the maximum output frequency, without regard to distortion, above which full
peak-to-peak output swing cannot be maintained.
Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified
in this data sheet and is measured using the circuit of Figure 1. The initial setup involves the use of a sinusoidal
input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is
increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same
amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained
(Figure 5). A square wave is used to allow a more accurate determination of the point at which the maximum
peak-to-peak output is reached.
(a) f = 1 kHz
(b) BOM > f > 1 kHz
(c) f = BOM
(d) f > BOM
Figure 5. Full-Power-Response Output Signal
test time
Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume,
short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET
devices and require longer test times than their bipolar and BiFET counterparts. The problem becomes more
pronounced with reduced supply levels and lower temperatures.
18
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TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
αVIO
Input offset voltage
Distribution
6, 7
Temperature coefficient of input offset voltage
Distribution
8, 9
VOH
High-level
High
level out
output
ut voltage
vs High-level out
output
ut current
vs Su
Supply
ly voltage
vs Free-air temperature
10, 11
12
13
VOL
Low level output voltage
Low-level
input
vs Common-mode in
ut voltage
vs Differential input
in ut voltage
vs Free
Free-air
air tem
temperature
erature
vs Low-level output current
14, 15
16
17
18, 19
AVD
Large-signal
amplification
Large
signal differential voltage am
lification
vs Su
Supply
ly voltage
Free-air
temperature
vs Free
air tem
erature
vs Frequency
20
21
32, 33
IIB
IIO
Input bias current
vs Free-air temperature
22
Input offset current
vs Free-air temperature
22
VIC
Common-mode input voltage
vs Supply voltage
23
IDD
Supply current
Supply
vs Su
ly voltage
vs Free-air temperature
24
25
SR
Slew rate
vs Su
Supply
ly voltage
vs Free-air temperature
26
27
Normalized slew rate
vs Free-air temperature
28
Maximum peak-to-peak output voltage
vs Frequency
29
B1
Unity gain bandwidth
Unity-gain
vs Free
Free-air
air tem
temperature
erature
vs Supply voltage
30
31
φm
Phase margin
vs Su
Supply
ly voltage
Free-air
temperature
vs Free
air tem
erature
vs Load capacitance
34
35
36
Vn
Equivalent input noise voltage
vs Frequency
37
Phase shift
vs Frequency
32, 33
VO(PP)
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TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLC272
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLC272
INPUT OFFSET VOLTAGE
Percentage of Units – %
50
40
ÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌÌ
60
753 Amplifiers Tested From 6 Wafer Lots
VDD = 5 V
TA = 25°C
P Package
50
Percentage of Units – %
60
30
20
40
ÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
753 Amplifiers Tested From 6 Wafer Lots
VDD = 10 V
TA = 25°C
P Package
30
20
10
10
0
–5
0
–4
–3 –2 –1
0
1
2
3
VIO – Input Offset Voltage – mV
4
–5
5
–4
DISTRIBUTION OF TLC272 AND TLC277
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
40
DISTRIBUTION OF TLC272 AND TLC277
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌ
60
324 Amplifiers Tested From 8 Wafer Lots
VDD = 5 V
TA = 25°C to 125°C
P Package
Outliers:
(1) 20.5 µV/°C
50
Percentage of Units – %
Percentage of Units – %
50
30
20
40
324 Amplifiers Tested From 8 Wafer Lots
VDD = 5 V
TA = 25°C to 125°C
P Package
Outliers:
(1) 21.2 µV/°C
30
20
10
10
0
0
2
4
6
8
– 10 – 8 – 6 – 4 – 2
αVIO – Temperature Coefficient – µV/°C
10
0
2
4
6
8
– 10 – 8 – 6 – 4 – 2 0
αVIO – Temperature Coefficient – µV/°C
Figure 9
Figure 8
20
5
4
Figure 7
Figure 6
60
–3 –2 –1
0
1
2
3
VIO – Input Offset Voltage – mV
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TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS†
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
16
VID = 100 mV
TA = 25°C
See Note A
4
VOH
VOH – High-Level Output Voltage – V
VOH
VOH – High-Level Output Voltage – V
5
VDD = 5 V
3
VDD = 4 V
VDD = 3 V
2
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
1
0
–2
–4
–6
–8
IOH – High-Level Output Current – mA
0
– 10
14
VDD = 16 V
VID = 100 mV
TA = 25°C
12
10
8
VDD = 10 V
6
4
2
0
0
– 5 – 10 – 15 – 20 – 25 – 30 – 35 – 40
IOH – High-Level Output Current – mA
NOTE A: The 3-V curve only applies to the C version.
Figure 10
Figure 11
HIGH-LEVEL OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
14
12
ÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌ
VDD – 1.6
VID = 100 mV
RL = 10 kΩ
TA = 25°C
VOH
VOH – High-Level Output Voltage – V
VOH
VOH – High-Level Output Voltage – V
16
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
10
ÁÁ
ÁÁ
ÁÁ
8
6
IOH = – 5 mA
VID = 100 mA
VDD – 1.7
VDD = 5 V
VDD –1.8
VDD – 1.9
VDD – 2
VDD = 10 V
VDD –2.1
ÁÁ
ÁÁ
ÁÁ
4
2
0
0
2
4
6
8
10
12
VDD – Supply Voltage – V
14
16
VDD – 2.2
VDD –2.3
VDD –2.4
– 75
– 50
Figure 12
– 25
0
20
50
75 100
TA – Free-Air Temperature – °C
125
Figure 13
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS†
LOW-LEVEL OUTPUT VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
500
VDD = 5 V
IOL = 5 mA
650
TA = 25°C
600
550
VID = – 100 mV
500
450
ÁÁ
ÁÁ
ÁÁ
VID = – 1 V
350
300
0.5
1
1.5
2
2.5
3
3.5
VIC – Common-Mode Input Voltage – V
TA = 25°C
450
400
VID = – 100 mV
VID = – 1 V
350
VID = – 2.5 V
ÁÁ
ÁÁ
400
0
VDD = 10 V
IOL = 5 mA
VOL
VOL – Low-Level Output Voltage – mV
VOL
VOL – Low-Level Output Voltage – mV
700
4
300
250
0
1
2
4
6
8
3
5
7
9
VIC – Common-Mode Input Voltage – V
Figure 14
Figure 15
LOW-LEVEL OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
900
IOL = 5 mA
VIC = |VID/2|
TA = 25°C
700
VOL – Low-Level Output Voltage – mV
VOL
VOL
VOL – Low-Level Output Voltage – mV
800
600
500
VDD = 5 V
400
300
ÁÁ
ÁÁ
ÁÁ
VDD = 10 V
200
100
0
800
700
IOL = 5 mA
VID = – 1 V
VIC = 0.5 V
VDD = 5 V
600
500
400
ÁÁ
ÁÁ
ÁÁ
VDD = 10 V
300
200
100
0
–1
– 2 – 3 – 4 – 5 – 6 – 7 – 8 – 9 – 10
VID – Differential Input Voltage – V
0
– 75
– 50
Figure 16
– 25
0
25
50
75 100
TA – Free-Air Temperature – °C
Figure 17
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
22
10
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TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS†
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VOL
VOL – Low-Level Output Voltage – V
0.9
0.8
0.7
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
3.0
VID = – 1 V
VIC = 0.5 V
TA = 25°C
See Note A
VOL – Low-Level Output Voltage – V
VOL
1.0
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VDD = 5 V
VDD = 4 V
0.6
VDD = 3 V
0.5
0.4
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
IOL – Low-Level Output Current – mA
2.5
2.0
ÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
VID = – 1 V
VIC = 0.5 V
TA = 25°C
VDD = 16 V
VDD = 10 V
1.5
1.0
0.5
8
0
0
5
10
15
20
25
IOL – Low-Level Output Current – mA
30
NOTE A: The 3-V curve only applies to the C version.
Figure 19
Figure 18
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
SUPPLY VOLTAGE
60
ÌÌÌÌ
50
TA = 0°C
40
ÌÌÌÌ
ÌÌÌÌ ÁÁ
ÌÌÌÌÌÁÁ
ÁÁ
30
TA = 25°C
TA = 85°C
20
TA = 125°C
10
0
0
2
4
6
8
10
12
VDD – Supply Voltage – V
14
16
RL = 10 kΩ
45
AVD
AVD – Large-Signal Differential
Voltage Amplification – V/mV
AVD
AVD – Large-Signal Differential
Voltage Amplification – V/mV
50
TA = – 55°C
RL = 10 kΩ
ÁÁ
ÁÁ
ÁÁ
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
40
VDD = 10 V
35
30
25
20
VDD = 5 V
15
10
5
0
– 75
– 50
Figure 20
– 25
0
25
50
75
100
TA – Free-Air Temperature – °C
125
Figure 21
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS†
COMMON-MODE
INPUT VOLTAGE POSITIVE LIMIT
vs
SUPPLY VOLTAGE
10000
16
VDD = 10 V
VIC = 5 V
See Note A
ÌÌ
1000
VIC – Common-Mode Input Voltage – V
I IB and I IO – Input Bias and Offset Currents – pA
INPUT BIAS CURRENT AND INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
IIB
100
ÌÌ
ÌÌ
IIO
10
1
0.1
25
TA = 25°C
14
12
10
8
6
4
2
0
35
45 55 65 75 85 95 105 115 125
TA – Free-Air Temperature – °C
NOTE A: The typical values of input bias current and input
offset current below 5 pA were determined mathematically.
0
2
4
6
8
10
12
VDD – Supply Voltage – V
14
16
– 25
0
25
50
75
100
TA – Free-Air Temperature – °C
125
Figure 23
Figure 22
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
5
4
VO = VDD/2
No Load
3.5
VO = VDD/2
No Load
TA = – 55°C
4
3.5
ÌÌÌÌ
ÌÌÌÌ
3
TA = 25°C
2.5
2
1.5
ÌÌÌ
TA = 0°C
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
1
TA = 70°C
0.5
I DD – Supply Current – mA
I DD – Supply Current – mA
4.5
3
2.5
VDD = 10 V
2
1.5
VDD = 5 V
1
0.5
TA = 125°C
0
0
2
4
6
8
10
12
VDD – Supply Voltage – V
14
16
0
– 75
– 50
Figure 24
Figure 25
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
24
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TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS†
SLEW RATE
vs
FREE-AIR TEMPERATURE
SLEW RATE
vs
SUPPLY VOLTAGE
8
8
AV = 1
VIPP = 1 V
RL = 10 kΩ
CL = 20 pF
TA = 25°C
See Figure 1
6
7
5
4
3
3
1
1
0
4
6
8
10
12
VDD – Supply Voltage – V
14
VDD = 10 V
VIPP = 1 V
4
2
2
VDD = 10 V
VIPP = 5.5 V
5
2
0
VDD = 5 V
VIPP = 1 V
VDD = 5 V
VIPP = 2.5 V
0
– 75
16
– 50
NORMALIZED SLEW RATE
vs
FREE-AIR TEMPERATURE
VO(PP) – Maximum Peak-to-Peak Output Voltage – V
AV = 1
VIPP = 1 V
RL = 10 kΩ
CL = 20 pF
1.4
VDD = 10 V
Normalized Slew Rate
1.2
VDD = 5 V
1.0
0.9
0.8
0.7
0.6
0.5
– 75
– 50
– 25
0
25
125
MAXIMUM PEAK OUTPUT VOLTAGE
vs
FREQUENCY
1.5
1.1
– 25
0
25
50
75 100
TA – Free-Air Temperature – °C
Figure 27
Figure 26
1.3
AV = 1
RL = 10 kΩ
CL = 20 pF
See Figure 1
6
SR – Slew Rate – V/ µs
SR – Slew Rate – V/ µs
7
50
75
100
125
10
VDD = 10 V
9
8
TA = 125°C
TA = 25°C
TA = – 55°C
7
6
5
VDD = 5 V
4
3
RL = 10 kΩ
See Figure 1
2
1
0
10
TA – Free-Air Temperature – °C
100
1000
10000
f – Frequency – kHz
Figure 29
Figure 28
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS†
UNITY-GAIN BANDWIDTH
vs
SUPPLY VOLTAGE
UNITY-GAIN BANDWIDTH
vs
FREE-AIR TEMPERATURE
2.5
VDD = 5 V
VI = 10 mV
CL = 20 pF
See Figure 3
2.5
B1 – Unity-Gain Bandwidth – MHz
B1 – Unity-Gain Bandwidth – MHz
3.0
2.0
1.5
1.0
– 75
VI = 10 mV
CL = 20 pF
TA = 25°C
See Figure 3
2.0
1.5
1.0
– 50
– 25
0
25
50
75
100
0
125
2
4
6
8
10
12
14
VDD – Supply Voltage – V
TA – Free-Air Temperature – °C
Figure 31
Figure 30
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
107
Á
Á
VDD = 5 V
RL = 10 kΩ
TA = 25°C
10 5
0°
10 4
30°
AVD
10 3
60°
10 2
90°
Phase Shift
101
120°
1
150°
0.1
10
Phase Shift
AVD
AVD – Large-Signal Differential
Voltage Amplification
10 6
180°
100
1k
10 k
100 k
1M
10 M
f – Frequency – Hz
Figure 32
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
26
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TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS†
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
10 7
VDD = 10 V
RL = 10 kΩ
TA = 25°C
ÁÁ
ÁÁ
10 5
0°
10 4
30°
Phase Shift
AVD
AVD – Large-Signal Differential
Voltage Amplification
10 6
AVD
10 3
60°
10 2
90°
Phase Shift
101
120°
1
150°
0.1
100
10
1k
10 k
100 k
1M
180°
10 M
f – Frequency – Hz
Figure 33
PHASE MARGIN
vs
SUPPLY VOLTAGE
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
53°
50°
VDD = 5 V
VI = 10 mV
CL = 20 pF
See Figure 3
52°
48°
φm
m – Phase Margin
φm
m – Phase Margin
51°
50°
49°
48°
VI = 10 mV
CL = 20 pF
TA = 25°C
See Figure 3
47°
46°
2
4
6
8
10
12
14
44°
42°
45°
0
46°
16
40°
–75
–50
–25
0
25
50
75
100
125
TA – Free-Air Temperature – °C
VDD – Supply Voltage – V
Figure 34
Figure 35
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
CAPACITIVE LOAD
50°
VDD = 5 V
VI = 10 mV
TA = 25°C
See Figure 3
φm
m – Phase Margin
45°
40°
35°
30°
25°
VN
V n – Equivalent Input Noise Voltage – nV/ Hz
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
400
VDD = 5 V
RS = 20 Ω
TA = 25°C
See Figure 2
300
200
100
0
0
10
20
30
40
50
60
70
80
90 100
1
CL – Capacitive Load – pF
100
f – Frequency – Hz
Figure 36
28
10
Figure 37
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1000
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
APPLICATION INFORMATION
single-supply operation
While the TLC272 and TLC277 perform well using dual power supplies (also called balanced or split supplies),
the design is optimized for single-supply operation. This design includes an input common-mode voltage range
that encompasses ground as well as an output voltage range that pulls down to ground. The supply voltage
range extends down to 3 V (C-suffix types), thus allowing operation with supply levels commonly available for
TTL and HCMOS; however, for maximum dynamic range, 16-V single-supply operation is recommended.
Many single-supply applications require that a voltage be applied to one input to establish a reference level that
is above ground. A resistive voltage divider is usually sufficient to establish this reference level (see Figure 38).
The low input bias current of the TLC272 and TLC277 permits the use of very large resistive values to implement
the voltage divider, thus minimizing power consumption.
The TLC272 and TLC277 work well in conjunction with digital logic; however, when powering both linear devices
and digital logic from the same power supply, the following precautions are recommended:
1. Power the linear devices from separate bypassed supply lines (see Figure 39); otherwise, the linear
device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital
logic.
2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive
decoupling is often adequate; however, high-frequency applications may require RC decoupling.
VDD
R4
R1
R2
–
VI
VO
+
VREF
R3
V
REF
V
C
0.01 µF
O
+ V
+ (V
R3
DD R1 ) R3
REF
* V ) R4 ) V
REF
I R2
Figure 38. Inverting Amplifier With Voltage Reference
–
OUT
Logic
Logic
Logic
Power
Supply
+
(a) COMMON SUPPLY RAILS
–
Logic
Logic
Logic
+
OUT
Power
Supply
(b) SEPARATE BYPASSED SUPPLY RAILS (preferred)
Figure 39. Common vs Separate Supply Rails
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
APPLICATION INFORMATION
input characteristics
The TLC272 and TLC277 are specified with a minimum and a maximum input voltage that, if exceeded at either
input, could cause the device to malfunction. Exceeding this specified range is a common problem, especially
in single-supply operation. Note that the lower range limit includes the negative rail, while the upper range limit
is specified at VDD – 1 V at TA = 25°C and at VDD – 1.5 V at all other temperatures.
The use of the polysilicon-gate process and the careful input circuit design gives the TLC272 and TLC277 very
good input offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage drift
in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus
dopant implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate)
alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude.
The offset voltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of
operation.
Because of the extremely high input impedance and resulting low bias current requirements, the TLC272 and
TLC277 are well suited for low-level signal processing; however, leakage currents on printed-circuit boards and
sockets can easily exceed bias current requirements and cause a degradation in device performance. It is good
practice to include guard rings around inputs (similar to those of Figure 4 in the Parameter Measurement
Information section). These guards should be driven from a low-impedance source at the same voltage level
as the common-mode input (see Figure 40).
Unused amplifiers should be connected as grounded unity-gain followers to avoid possible oscillation.
noise performance
The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage
differential amplifier. The low input bias current requirements of the TLC272 and TLC277 result in a very low
noise current, which is insignificant in most applications. This feature makes the devices especially favorable
over bipolar devices when using values of circuit impedance greater than 50 kΩ, since bipolar devices exhibit
greater noise currents.
–
OUT
+
+
(b) INVERTING AMPLIFIER
OUT
VI
+
–
(a) NONINVERTING AMPLIFIER
–
VI
VI
OUT
(c) UNITY-GAIN AMPLIFIER
Figure 40. Guard-Ring Schemes
output characteristics
The output stage of the TLC272 and TLC277 is designed to sink and source relatively high amounts of current
(see typical characteristics). If the output is subjected to a short-circuit condition, this high current capability can
cause device damage under certain conditions. Output current capability increases with supply voltage.
All operating characteristics of the TLC272 and TLC277 are measured using a 20-pF load. The devices can
drive higher capacitive loads; however, as output load capacitance increases, the resulting response pole
occurs at lower frequencies, thereby causing ringing, peaking, or even oscillation (see Figure 41). In many
cases, adding a small amount of resistance in series with the load capacitance alleviates the problem.
30
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
APPLICATION INFORMATION
output characteristics (continued)
(b) CL = 130 pF, RL = NO LOAD
(a) CL = 20 pF, RL = NO LOAD
2.5 V
–
VO
+
VI
TA = 25°C
f = 1 kHz
VIPP = 1 V
CL
– 2.5 V
(d) TEST CIRCUIT
(c) CL = 150 pF, RL = NO LOAD
Figure 41. Effect of Capacitive Loads and Test Circuit
Although the TLC272 and TLC277 possess excellent high-level output voltage and current capability, methods
for boosting this capability are available, if needed. The simplest method involves the use of a pullup resistor
(RP) connected from the output to the positive supply rail (see Figure 42). There are two disadvantages to the
use of this circuit. First, the NMOS pulldown transistor N4 (see equivalent schematic) must sink a comparatively
large amount of current. In this circuit, N4 behaves like a linear resistor with an on resistance between
approximately 60 Ω and 180 Ω, depending on how hard the operational amplifier input is driven. With very low
values of RP, a voltage offset from 0 V at the output occurs. Second, pullup resistor RP acts as a drain load to
N4 and the gain of the operational amplifier is reduced at output voltage levels where N5 is not supplying the
output current.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
31
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
APPLICATION INFORMATION
output characteristics (continued)
VDD
VI
+
IP
RP
VO
–
C
IF
R2
R1
IL
RL
–
VO
VDD – VO
IF + IL + IP
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
+
Rp =
Ip = Pullup current required by
the operational amplifier
(typically 500 µA)
Figure 42. Resistive Pullup to Increase VOH
Figure 43. Compensation for Input Capacitance
feedback
Operational amplifier circuits almost always employ feedback, and since feedback is the first prerequisite for
oscillation, some caution is appropriate. Most oscillation problems result from driving capacitive loads
(discussed previously) and ignoring stray input capacitance. A small-value capacitor connected in parallel with
the feedback resistor is an effective remedy (see Figure 43). The value of this capacitor is optimized empirically.
electrostatic discharge protection
The TLC272 and TLC277 incorporate an internal electrostatic discharge (ESD) protection circuit that prevents
functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2. Care should be
exercised, however, when handling these devices as exposure to ESD may result in the degradation of the
device parametric performance. The protection circuit also causes the input bias currents to be temperature
dependent and have the characteristics of a reverse-biased diode.
latch-up
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC272 and
TLC277 inputs and outputs were designed to withstand –100-mA surge currents without sustaining latch-up;
however, techniques should be used to reduce the chance of latch-up whenever possible. Internal protection
diodes should not, by design, be forward biased. Applied input and output voltage should not exceed the supply
voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators.
Supply transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the
supply rails as close to the device as possible.
The current path established if latch-up occurs is usually between the positive supply rail and ground and can
be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply
voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the
forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of
latch-up occurring increases with increasing temperature and supply voltages.
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
APPLICATION INFORMATION
10 kΩ
10 kΩ
0.016 µF
0.016 µF
10 kΩ
–
10 kΩ
5V
10 kΩ
1/2
TLC272
–
1/2
TLC272
–
VI
1/2
TLC272
Low Pass
+
+
+
High Pass
5 kΩ
Band Pass
R = 5 kΩ(3/d-1) (see Note A)
NOTE A: d = damping factor, 1/Q
Figure 44. State-Variable Filter
12 V
VI
+
1/2
TLC272
H.P.
5082-2835
+
1/2
TLC272
–
0.5 µF
Mylar
N.O.
Reset
VO
–
100 kΩ
Figure 45. Positive-Peak Detector
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
APPLICATION INFORMATION
VI
(see Note A)
100 kΩ
1.2 kΩ
0.47 µF
4.7 kΩ
–
TL431
20 kΩ
1/2
TLC272
0.1 µF
1 kΩ
TIP31
15 Ω
+
TIS193
250 µF,
25 V
+
–
VO
(see Note B)
10 kΩ
47 kΩ
0.01 µF
110 Ω
22 kΩ
NOTES: A. VI = 3.5 to 15 V
B. VO = 2 V, 0 to 1 A
Figure 46. Logic-Array Power Supply
VO (see Note A)
9V
10 kΩ
0.1 µF
9V
C
100 kΩ
–
1/2
TLC272
R2
10 kΩ
1/2
TLC272
VO (see Note B)
+
100 kΩ
fO +
R1
47 kΩ
R3
NOTES: A. VO(PP) = 8 V
B. VO(PP) = 4 V
Figure 47. Single-Supply Function Generator
34
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
[ ]
1
R1
4C(R2) R3
TLC272, TLC272A, TLC272B, TLC272Y, TLC277
LinCMOS PRECISION DUAL OPERATIONAL AMPLIFIERS
SLOS091E – OCTOBER 1987 – REVISED FEBRUARY 2002
APPLICATION INFORMATION
5V
VI –
+
10 kΩ
1/2
TLC277
100 kΩ
–
–
1/2
TLC277
VO
+
10 kΩ
–
10 kΩ
1/2
TLC277
95 kΩ
R1,10 kΩ
(see Note A)
+
VI +
–5 V
NOTE B: CMRR adjustment must be noninductive.
Figure 48. Low-Power Instrumentation Amplifier
5V
–
R
10 MΩ
R
10 MΩ
1/2
TLC272
VO
+
VI
2C
540 pF
f NOTCH +
R/2
5 MΩ
C
270 pF
1
2pRC
C
270 pF
Figure 49. Single-Supply Twin-T Notch Filter
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
35
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
5962-89494022A
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
-55 to 125
TLC272ACD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
272AC
TLC272ACDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
272AC
TLC272ACDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
272AC
TLC272ACDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
272AC
TLC272ACP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC272ACP
TLC272ACPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC272ACP
TLC272AID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
272AI
TLC272AIDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
272AI
TLC272AIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
272AI
TLC272AIDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
272AI
TLC272AIP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLC272AIP
TLC272AIPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLC272AIP
TLC272BCD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
272BC
TLC272BCDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
272BC
TLC272BCDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
272BC
TLC272BCDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
272BC
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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11-Apr-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TLC272BCP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC272BCP
TLC272BCPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC272BCP
TLC272BID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
272BI
TLC272BIDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
272BI
TLC272BIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
272BI
TLC272BIDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
272BI
TLC272BIP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLC272BIP
TLC272BIPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLC272BIP
TLC272CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
272C
TLC272CDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
272C
TLC272CDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
272C
TLC272CDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
272C
TLC272CP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC272CP
TLC272CPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TLC272CP
TLC272CPSR
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P272
TLC272CPSRG4
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P272
TLC272CPW
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P272C
TLC272CPWG4
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P272C
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TLC272CPWLE
OBSOLETE
TSSOP
PW
8
TBD
Call TI
Call TI
0 to 70
TLC272CPWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P272C
TLC272CPWRG4
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
P272C
TLC272ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
272I
TLC272IDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
272I
TLC272IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
272I
TLC272IDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
272I
TLC272IP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLC272IP
TLC272IPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 85
TLC272IP
TLC272MFKB
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
-55 to 125
TLC272MJG
OBSOLETE
CDIP
JG
8
TBD
Call TI
Call TI
-55 to 125
TLC272MJGB
OBSOLETE
CDIP
JG
8
TBD
Call TI
Call TI
-55 to 125
TLC272P-M
PREVIEW
PDIP
P
8
TBD
Call TI
Call TI
TLC277CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
277C
TLC277CDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
277C
TLC277CDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
277C
TLC277CDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
277C
TLC277CP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLC277CP
TLC277CPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLC277CP
TLC277CPSR
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 3
P277
Samples
PACKAGE OPTION ADDENDUM
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11-Apr-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TLC277CPSRG4
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
P277
TLC277ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
277I
TLC277IDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
277I
TLC277IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
277I
TLC277IDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
277I
TLC277IP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLC277IP
TLC277IPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLC277IP
TLC277MFKB
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
-55 to 125
TLC277MJG
OBSOLETE
CDIP
JG
8
TBD
Call TI
Call TI
-55 to 125
TLC277MJGB
OBSOLETE
CDIP
JG
8
TBD
Call TI
Call TI
-55 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 4
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLC272ACDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC272AIDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC272BCDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC272BIDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC272CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC272CPWR
TSSOP
PW
8
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
TLC272IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC277CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TLC277CPSR
SO
PS
8
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
TLC277IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jul-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLC272ACDR
SOIC
D
8
2500
340.5
338.1
20.6
TLC272AIDR
SOIC
D
8
2500
340.5
338.1
20.6
TLC272BCDR
SOIC
D
8
2500
340.5
338.1
20.6
TLC272BIDR
SOIC
D
8
2500
340.5
338.1
20.6
TLC272CDR
SOIC
D
8
2500
340.5
338.1
20.6
TLC272CPWR
TSSOP
PW
8
2000
367.0
367.0
35.0
TLC272IDR
SOIC
D
8
2500
340.5
338.1
20.6
TLC277CDR
SOIC
D
8
2500
340.5
338.1
20.6
TLC277CPSR
SO
PS
8
2000
367.0
367.0
38.0
TLC277IDR
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
0.063 (1,60)
0.015 (0,38)
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP1-T8
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