TC74VHCV245FT/FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHCV245FT,TC74VHCV245FK Octal Schmitt Bus Transceiver The TC74VHCV245 is an advanced high speed CMOS OCTAL BUS TRANSCEIVER fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. It is intended for two-way asynchronous communication between data busses. The direction of data transmission is determined by the level of the DIR input. The enable input ( G ) can be used to disable the device so that the busses are effectively isolated. Input pin and bus terminal have hysteresis between the positive-going and negative-going thresholds. Thus the TC74VHCV245 is capable of squaring up transitions of slowly changing input signals and provides an improved noise immunity. Input protection and output circuit ensure that 0 to 5.5 V can be applied to the input and output (Note) pins without regard to the supply voltage. These structure prevents device destruction due to mismatched supply and input/output voltages such as battery back up, etc. Note: Output in off-state. TC74VHCV245FT TC74VHCV245FK Weight TSSOP20-P-0044-0.65A VSSOP20-P-0030-0.50 Features (Note) • High speed: tpd = 3.8 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = 2 μA (max) at Ta = 25°C • Wide operating voltage range: VCC (opr) = 1.8 V to 5.5 V • Ouput current: |IOH|/IOL = 16 mA (min) (VCC = 4.5 V) • Available in TSSOP and VSSOP (US) • Power-down protection provided on all inputs and outputs • Pin and function compatible with the 74 series : 0.08 g ( typ.) : 0.03 g ( typ.) (74AC/VHC/HC/F/ALS/LS etc.) 245 type Note: Do not apply a signal to any bus pins when it is in the output mode. Damage may result. All floating (high impedance) bus pins must have their input levels fixed by means of pull-up or pull-down resistors. 1 2010-07-09 TC74VHCV245FT/FK Pin Assignment DIR 1 20 VCC A1 2 19 G A2 3 18 B1 A3 4 17 B2 A4 5 16 B3 A5 6 15 B4 A6 7 14 B5 A7 8 13 B6 A8 9 12 B7 GND 10 11 B8 (top view) Truth Table Inputs Function Output G DIR A Bus B Bus L L Output Input A=B L H Input Output B=A H X Z Z X: Don’t care Z: High impedance 2 2010-07-09 TC74VHCV245FT/FK Absolute Maximum Ratings (Note 1) Characteristics Symbol Rating Unit Power supply voltage VCC −0.5 to 7.0 V DC iInput voltage (DIR, G ) VIN −0.5 to 7.0 V DC bus I/O voltage VI/O Input diode current IIK Output diode current IOK DC output current IOUT ±50 mA Power dissipation PD 180 mW ICC/IGND ±100 mA Tstg −65 to 150 °C DC VCC/ground current Storage temperature −0.5 to 7.0 (Note 2) -0.5 to VCC + 0.5 (Note 3) V −50 mA ±50 (Note 4) mA Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: off-state Note 3: High or low state. IOUT absolute maximum rating must be observed. Note 4: VOUT < GND, VOUT > VCC Operating Ranges (Note 1) Characteristics Symbol Rating Unit Power supply voltage VCC 1.8 to 5.5 V iInput voltage (DIR, G ) VIN 0 to 5.5 V Bus I/O voltage VI/O Operating temperature Topr −40 to 85 °C Input rise and fall time dt/dv 0 to 20(Vcc=3.3 ± 0.3V) 0 to 1(Vcc=5 ± 0.5V) ms/V 0 to 5.5 (Note 2) 0 to VCC (Note 3) V Note 1: The operating ranges are required to ensure the normal operation of the device. Unused inputs and bus inputs must be tied to either VCC or GND. Please connect both bus inputs and the bus outputs with VCC or GND when the I/O of the bus terminal changes by the function. In this case, please note that the output is not short-circuited. Note 2: off-state Note 3: High or low state 3 2010-07-09 TC74VHCV245FT/FK Electrical Characteristics DC Characteristics Test Condition Characteristics Positive threshold voltage Negative threshold voltage Hysteresis voltage High-level output voltage Low-level output voltage Symbol VP VN VH VOH VOL Ta = −40 to 85°C Ta = 25°C VCC (V) Min Typ. Max Min Max ― 1.8 2.3 3.0 4.5 5.5 ― ― ― ― ― ― ― ― ― ― 1.65 1.85 2.20 3.15 3.85 ― ― ― ― ― 1.65 1.85 2.20 3.15 3.85 ― 1.8 2.3 3.0 4.5 5.5 0.15 0.45 0.90 1.35 1.65 ― ― ― ― ― ― ― ― ― ― 0.15 0.45 0.90 1.35 1.65 ― ― ― ― ― ― 1.8 2.3 3.0 4.5 5.5 0.15 0.20 0.30 0.40 0.50 ― ― ― ― ― 1.05 1.10 1.20 1.40 1.60 0.15 0.20 0.30 0.40 0.50 1.05 1.10 1.20 1.40 1.60 1.8 3.0 4.5 1.7 2.9 4.4 1.8 3.0 4.5 ― ― ― 1.7 2.9 4.4 ― ― ― 3.0 4.5 2.58 3.94 ― ― ― ― 2.48 3.80 ― ― 1.8 3.0 4.5 ― ― ― 0.0 0.0 0.0 0.1 0.1 0.1 ― ― ― 0.1 0.1 0.1 3.0 4.5 ― ― ― ― 0.36 0.44 ― ― 0.44 0.55 IOH = −50 μA VIN = VIH or VIL IOH = −8 mA IOH = −16 mA IOL = 50 μA VIN = VIH or VIL IOL = 8 mA IOL = 16 mA Unit V V V 3-state output off-state current IOZ VIN = VIH or VIL VOUT = 0 to 5.5V 1.8 to 5.5 ― ― ±0.5 ― ±5.0 μA Power-off leakage current IOFF VIN/VOUT = 5.5 V 0 ― ― 0.5 ― 5.0 μA Input leakage current IIN VIN = 5.5 V or GND 0 to 5.5 ― ― ±0.1 ― ±1.0 μA Quiescent supply current ICC VIN = VCC or GND 5.5 ― ― 2.0 ― 20.0 μA 4 2010-07-09 TC74VHCV245FT/FK AC Characteristics (input: tr = tf = 3 ns) Characteristics Test Condition Symbol CL (pF) Min Typ. Max Min Max 15 ― 5.9 13.0 1.0 15.0 50 ― 8.7 15.9 1.0 18.0 15 ― 4.6 8.4 1.0 10.0 50 ― 6.9 11.9 1.0 13.5 15 ― 3.8 5.5 1.0 6.5 50 ― 5.4 7.5 1.0 8.5 15 ― 7.0 19.9 1.0 22.0 50 ― 9.6 22.7 1.0 26.0 15 ― 5.3 13.2 1.0 15.5 50 ― 7.4 16.7 1.0 19.0 15 ― 4.1 8.5 1.0 10.0 50 ― 5.7 10.6 1.0 12.0 2.5 ± 0.2 50 ― 15.0 23.1 1.0 25.0 3.3 ± 0.3 50 ― 11.6 15.8 1.0 18.0 5.0 ± 0.5 50 ― 9.3 9.7 1.0 11.0 2.5 ± 0.2 50 ― ― 2.0 ― 2.0 3.3 ± 0.3 50 ― ― 1.5 ― 1.5 5.0 ± 0.5 50 ― ― 1.0 ― 1.0 VCC (V) 2.5± 0.2 Propagation delay time tpLH tpHL ― 3.3 ± 0.3 5.0 ± 0.5 2.5 ± 0.2 3-state output enable time tpZL tpZH RL = 1 kΩ 3.3 ± 0.3 5.0 ± 0.5 3-state output disable time Output to output skew tpLZ tpHZ tosLH tosHL RL = 1 kΩ (Note1) Ta = −40 to 85°C Ta = 25°C Unit ns ns ns ns Input capacitance CIN DIR, G ― 4 10 ― 10 pF Bus input capacitance CI/O An, Bn ― 6 ― ― ― pF Power dissipation capacitance CPD (Note2) ― 26 ― ― ― pF Note 1: Parameter guaranteed by design. tosLH = |tpLHm − tpLHn|, tosHL = |tpHLm − tpHLn| Note 2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD·VCC·fIN + ICC/8 (per bit) 5 2010-07-09 TC74VHCV245FT/FK Noise Characteristics (input: tr = tf = 3 ns) Characteristics Ta = 25°C Test Condition Symbol VCC (V) Typ. Max Unit Quiet output maximum dynamic VOL VOLP CL = 50 pF 3.3 5.0 0.5 1.0 ― ― V Quiet output minimum dynamic VOL VOLV CL = 50 pF 3.3 5.0 −0.1 −0.3 ― ― V Minimum high level dynamic input VIHD voltage CL = 50 pF 5.0 ― 3.5 V Maximum low level dynamic input voltage CL = 50 pF 5.0 ― 1.5 V VILD 6 2010-07-09 TC74VHCV245FT/FK Package Dimensions Weight: 0.08 g (typ.) 7 2010-07-09 TC74VHCV245FT/FK Package Dimensions Weight: 0.03 g (typ.) 8 2010-07-09 TC74VHCV245FT/FK RESTRICTIONS ON PRODUCT USE • Toshiba Corporation, and its subsidiaries and affiliates (collectively “TOSHIBA”), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively “Product”) without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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