FAN7361, FAN7362 High-Side Gate Driver Features Description ! Floating Channel Designed for Bootstrap The FAN7361/FAN7362, a monolithic high-side gate drive IC, can drive MOSFETs and IGBTs that operate up to +600V. Fairchild’s high-voltage process and commonmode noise canceling techniques provide stable operation of the high-side driver under high dv/dt noise circumstances. An advanced level shift circuit offers high-side gate driver operation up to VS=-9.8V(typ.) for VBS=15V. ! ! ! ! ! ! Operation to +600V Typically 250mA/500mA Sourcing/Sinking Current Driving Capability Common-Mode dv/dt Noise Canceling Circuit VCC & VBS Supply Range from 10V to 20V UVLO Function for VBS Output In-phase with Input Signal 8-SOP Applications ! PDP Scan Driver ! Motor Control The UVLO circuit prevents malfunction when VBS is lower than the specified threshold voltage. Output drivers typically source/sink 250mA/500mA, respectively, which is suitable for fluorescent lamp ballast, PDP scan driver, motor control, and so on. ! SMPS ! Electronic Ballast 8-SOP Ordering Information Part Number Package Operating Temperature Range Eco Status Packing Method FAN7361M(1) Tube FAN7361MX(1) Tape & Reel FAN7362M(1) 8-SOP -40°C ~ 125°C (1) FAN7362MX RoHS Tube Tape & Reel Note: 1. These devices passed wave soldering test by JESD22A-111. For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2005 Fairchild Semiconductor Corporation FAN7361, FAN7362 Rev. 1.0.8 www.fairchildsemi.com FAN7361, FAN7362 High-Side Gate Driver November 2009 FAN7361, FAN7362 High-Side Gate Driver Typical Application Circuit 15V 600V RBOOT DBOOT 1 NC IN1 VB 8 IN 3 VCC Q1 R1 HO 7 2 R2 CBOOT VS 6 IN2 4 GND NC 5 Q2 R3 Load R4 FAN7361 Rev.04 Figure 1. Typical Application Circuit Internal Block Diagram VCC 3 8 VB 7 HO 6 VS UVLO GND 4 R DRIVER 2 PULSE GENERATOR IN NOISE CANCELLER R S Q Pin 1 and 5 are not connection FAN7361 Rev.04 Figure 2. Functional Block Diagram © 2005 Fairchild Semiconductor Corporation FAN7361, FAN7362 Rev. 1.0.8 www.fairchildsemi.com 2 FAN7361, FAN7362 High-Side Gate Driver Pin Assignments NC 1 IN 2 VCC 3 GND 4 FAN7361 FAN7362 8 VB 7 HO 6 VS 5 NC FAN7361 Rev.04 Figure 3. Pin Configuration (Top View) Pin Definitions Pin Name Function/ Description 1 NC No Connection 2 IN Logic Input for High-Side Gate Driver Output 3 VCC Supply Voltage 4 GND Logic Ground 5 NC No Connection 6 VS High-Voltage Floating Supply Return 7 HO High-Side Driver Output 8 VB High-Side Floating Supply © 2005 Fairchild Semiconductor Corporation FAN7361, FAN7362 Rev. 1.0.8 www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA=25°C, unless otherwise specified. Symbol Characteristics Min. Max. VB-25 VB+0.3 High-Side Floating Supply Voltage -0.3 625 VHO High-Side Floating Output Voltage VS-0.3 VB+0.3 VCC Logic Fixed Supply Voltage -0.3 25 VIN Logic Input Voltage -0.3 VCC+0.3 VS High-Side Offset Voltage VB dVS/dt PD(2)(3)(4) Unit V Allowable Offset Voltage Slew Rate ± 50 V/ns Power Dissipation 0.625 W θJA Thermal Resistance, Junction-to-Ambient 200 °C/W TJ Junction Temperature +150 °C TS Storage Temperature +150 °C TA Ambient Temperature +125 °C -40 Notes: 2. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material). 3. Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions - Natural convection JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages 4. Do not exceed PD under any circumstances. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. VB High-Side Floating Supply Voltage VS+10 VS+20 VS High-Side Floating Supply Offset Voltage 6-VCC 600 VHO High-Side Output Voltage VIN Logic Input Voltage VCC Logic Supply Voltage © 2005 Fairchild Semiconductor Corporation FAN7361, FAN7362 Rev. 1.0.8 VS VB GND VCC 10 20 Unit V www.fairchildsemi.com 4 FAN7361, FAN7362 High-Side Gate Driver Absolute Maximum Ratings VBIAS(VCC, VBS)=15.0V, TA = 25°C, unless otherwise specified. The VIN and IIN parameters are referenced to GND. The VO and IO parameters are referenced to VS and are applicable to the respective output HO. Symbol Characteristics Test Condition Min. Typ. Max. VBSUV+ VBS Supply Under-Voltage Positive Going VBS=Sweep Threshold FAN7361 8.2 9.2 10.2 FAN7362 7.6 8.6 9.6 VBSUV- VBS Supply Under-Voltage Negative Going Threshold VBS=Sweep FAN7361 7.4 8.6 9.2 FAN7362 7.2 8.2 9.2 VBSHYS VBS Supply Under-Current Lockout Hysteresis VBS=Sweep ILK Offset Supply Leakage Current VB=VS=600V FAN7361 0.5 FAN7362 0.4 Unit V 10 IQBS Quiescent VBS Supply Current VIN=0V or 5V 50 80 IQCC Quiescent VCC Supply Current VIN=0V 30 75 IPBS Operating VBS Supply Current CL=1nF, f=10kHz 420 550 VIH Logic "1" Input Voltage FAN7361 3.6 FAN7362 2.9 FAN7361 1.0 FAN7362 0.8 VIL Logic "0" Input Voltage VOH High Level Output Voltage, VB-VHO No load VOL Low Level Output Voltage, VHO No load IIN+ Logic "1" Input Bias Current VIN=5V 50 90 IIN- Logic "0" Input Bias Current VIN=0V 1.0 2.0 IO+ Output High Short Circuit Pulse Current VHO=0V, VIN=5V, PW ≤ 10µs 200 250 IO- Output Low Short Circuit Pulse Current VHO=15V, VIN=0V,PW ≤ 10µs 400 500 VS Allowable Negative VS Pin Voltage for IN Signal Propagation to HO µA V 0.1 0.1 µA mA -9.8 -7.0 V Typ. Max. Unit VS=0V 120 200 VS=0V or 600V Dynamic Electrical Characteristics VBIAS(VCC, VBS)=15.0V, VS=GND, CL=1000pF and TA = 25°C, unless otherwise specified. Symbol ton toff Characteristics Turn-on Propagation Delay Turn-off Propagation Delay (5) Test Condition Min. 90 180 tr Turn-on Rise Time 70 160 tf Turn-off Fall Time 30 100 ns Note: 5. This parameter guaranteed by design. © 2005 Fairchild Semiconductor Corporation FAN7361, FAN7362 Rev. 1.0.8 www.fairchildsemi.com 5 FAN7361, FAN7362 High-Side Gate Driver Electrical Characteristics 200 80 VCC=15V 150 50 IIN [μA] -40°C 25°C 125°C 60 IQCC [μA] -40°C 25°C 125°C IN=COM=0V 70 100 40 30 50 20 10 0 0 0 5 10 15 20 0 25 2 4 6 PROPAGATION DELAY TIME [nsec] 10.5 VBSUVP1 VBSUVP2 VBSUVN1 VBSUVN2 VBS [V] 9.5 9.0 8.5 8.0 7.5 -20 0 20 40 60 10 12 14 Figure 5. Input Bias Current vs. Input Voltage Figure 4. IQCC vs. Supply Voltage 10.0 8 VIN [V] VCC [V] 80 100 120 200 TON 180 TOFF 160 140 120 100 80 60 40 20 0 0 20 AMBIENT TEMPERATURE [°C] 40 60 80 100 120 AMBIENT TEMPERATURE [°C] Figure 6. VBS UVLO vs. Temp. Figure 7. Turn On/Off Propagation Time vs. Temp. 90 OUTPUT CAPABILITY [mA] TR 80 TF tr/tf [nsec] 70 60 50 40 30 20 10 -20 0 20 40 60 80 100 IOH+ IOH- 500 400 300 200 -20 120 AMBIENT TEMPERATURE [°C] 0 20 40 60 80 100 120 AMBIENT TEMPERATURE [°C] Figure 8. Rising/Falling Time vs. Temp. Figure 9. Output Sinking/Sourcing Current vs. Temp. © 2005 Fairchild Semiconductor Corporation FAN7361, FAN7362 Rev. 1.0.8 600 www.fairchildsemi.com 6 FAN7361, FAN7362 High-Side Gate Driver Typical Characteristics 5V 50% IN 50% VCC=15V VB 10μF 0.1μF 0.1μF 10μF HVIC GND IN tr 15V tf ton VS toff 90% CL HO-V S HO 10% 90% 10% FAN7361 Rev.02 FAN7361 Rev.03 Figure 10. Switching Time Test Circuit Figure 11. Input / Output Timing Diagram © 2005 Fairchild Semiconductor Corporation FAN7361, FAN7362 Rev. 1.0.8 www.fairchildsemi.com 7 FAN7361, FAN7362 High-Side Gate Driver Switching Time Definition 5.00 4.80 A 0.65 3.81 8 5 6.20 5.80 PIN ONE INDICATOR B 1.75 4.00 3.80 1 5.60 4 1.27 (0.33) 0.25 M 1.27 C B A LAND PATTERN RECOMMENDATION 0.25 0.10 SEE DETAIL A 1.75 MAX 0.25 0.19 C 0.10 0.51 0.33 0.50 x 45° 0.25 R0.10 C OPTION A - BEVEL EDGE GAGE PLANE R0.10 0.36 OPTION B - NO BEVEL EDGE NOTES: UNLESS OTHERWISE SPECIFIED 8° 0° 0.90 0.406 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 Figure 12. 8-Lead Small Outline Package (SOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2005 Fairchild Semiconductor Corporation FAN7361, FAN7362 Rev. 1.0.8 www.fairchildsemi.com 8 FAN7361, FAN7362 High-Side Gate Driver Physical Dimensions FAN7361, FAN7362 High-Side Gate Driver © 2005 Fairchild Semiconductor Corporation FAN7361, FAN7362 Rev. 1.0.8 www.fairchildsemi.com 9