FAN73933
Half-Bridge Gate Drive IC
Features
Description
Floating Channel for Bootstrap Operation to +600V
The FAN73933 is a half-bridge, gate-drive IC with programmable dead-time control functions that can drive
high-speed MOSFETs and IGBTs operating up to +600V.
It has a buffered output stage with all NMOS transistors
designed for high-pulse-current driving capability and
minimum cross-conduction.
Typically 2.5A/2.5A Sourcing/Sinking Current Driving
Capability
Extended Allowable Negative VS Swing to -9.8V for
Signal Propagation at VBS=15V
Output in Phase with Input Signal
3.3V and 5V Input Logic Compatible
Matched Propagation Delay for Both Channels
Built-in UVLO Functions for Both Channels
Built-in Common-Mode dv/dt Noise Cancelling Circuit
Programmable Dead-Time Control Function
Internal 220ns Minimum Dead Time at RDT=0Ω
Applications
High-Speed Power MOSFET and IGBT Gate Driver
Induction Heating
High-Power DC-DC Converter
Synchronous Step-Down Converter
Fairchild’s high-voltage process and common-mode
noise canceling techniques provide stable operation of
the high-side driver under high dv/dt noise circumstances. An advanced level-shift circuit offers high-side
gate driver operation up to VS=-9.8V (typical) for
VBS=15V.
The UVLO circuit prevents malfunction when VDD and
VBS are lower than the specified threshold voltage.
The high-current and low-output voltage drop feature
makes this device suitable for diverse half- and fullbridge inverters; motor drive inverters, switching mode
power supplies, induction heating, and high-power DCDC converter applications.
Motor Drive Inverter
14-SOP
Ordering Information
Part Number
Package
Operating
Temperature
Range
Eco
Status
FAN73933M
14-Lead, Small Outline Integrated
Circuit (SOIC), Non-JEDEC, .150
Inch Narrow Body, 225SOP
-40°C to +125°C
RoHS
FAN73933MX
Packing Method
Tube
Tape & Reel
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2009 Fairchild Semiconductor Corporation
FAN73933 • Rev. 1.0.0
www.fairchildsemi.com
FAN73933 — Half-Bridge Gate Driver
December 2009
FAN73933 — Half-Bridge Gate Driver
Typical Application Diagrams
Up to 600V
+15V
RBOOT DBOOT
FAN73933
Controller
HIN
1 HIN
NC 14
LIN
2 LIN
VB 13
3
HO 12
VSS
R1
R2
CBOOT
RDT
4 DT
VS 11
5 COM
NC 10
6 LO
NC 9
7 VDD
NC 8
Load
R3
R4
Figure 1. Typical Application Circuit
Internal Block Diagram
13 VB
UVLO
NOISE
CANCELLER
R
DRIVER
250K
PULSE
GENERATOR
HS(ON/OFF)
HIN 1
R
S
Q
11 VS
SCHMITT
TRIGGER INPUT
LIN
2
7 VDD
250K
SHOOT THOUGH
PREVENTION
UVLO
4
VSS
3
DEAD-TIME
{ DTMIN=220ns }
LS(ON/OFF)
VSS/COM
LEVEL
SHIFT
DELAY
DRIVER
RDTINT
DT
12 HO
6 LO
5
COM
Pin 8, 9, 10 and 14 are no connection
Figure 2. Functional Block Diagram
© 2009 Fairchild Semiconductor Corporation
FAN73933 • Rev. 1.0.0
www.fairchildsemi.com
2
FAN73933 — Half-Bridge Gate Driver
Pin Configuration
1
14
NC
LIN
2
13
VB
VSS
3
12
HO
DT
4
11
VS
COM
5
10
NC
LO
6
9
NC
VDD
7
8
NC
FAN73933
HIN
Figure 3. Pin Configurations (Top View)
Pin Definitions
Pin #
Name
1
HIN
Logic Input for High-Side Gate Driver Output
Description
2
LIN
Logic Input for Low-Side Gate Driver Output
3
VSS
Logic Ground
Dead-Time Control with External Resistor (Referenced to VSS)
4
DT
5
COM
6
LO
Low-Side Driver Return
7
VDD
Supply Voltage
8
NC
No Connection
9
NC
No Connection
10
NC
No Connection
11
VS
High-Voltage Floating Supply Return
12
HO
High-Side Driver Output
13
VB
High-Side Floating Supply
14
NC
No Connection
© 2009 Fairchild Semiconductor Corporation
FAN73933 • Rev. 1.0.0
Ground
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. TA=25°C unless otherwise specified.
Symbol
Characteristics
Min.
Max.
Unit
VB
High-Side Floating Supply Voltage
-0.3
625.0
V
VS
High-Side Floating Offset Voltage
VB-25.0
VB+0.3
V
VHO
High-Side Floating Output Voltage
VS-0.3
VB+0.3
V
VLO
Low-Side Output Voltage
-0.3
VDD+0.3
V
VDD
Low-Side and Logic Fixed Supply Voltage
-0.3
25.0
V
VIN
Logic Input Voltage (HIN and LIN)
-0.3
VDD+0.3
V
DT
Programmable Dead-Time Pin Voltage
-0.3
VDD+0.3
V
VSS
Logic Ground
VDD-25
VDD+0.3
V
± 50
V/ns
1
W
110
°C/W
+150
°C
+150
°C
dVS/dt
Allowable Offset Voltage Slew Rate
PD
Power Dissipation(1, 2, 3)
θJA
Thermal Resistance
TJ
Junction Temperature
TSTG
Storage Temperature
-55
Notes:
1 Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material).
2 Refer to the following standards:
JESD51-2: Integral circuits thermal test method environmental conditions - natural convection, and
JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages.
3 Do not exceed maximum PD under any circumstances.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Min.
Max.
Unit
VB
High-Side Floating Supply Voltage
VS+10
VS+20
V
VS
High-Side Floating Supply Offset Voltage
6-VDD
600
V
VS
VB
V
VHO
High-Side Output Voltage
VDD
Low-Side and Logic Fixed Supply Voltage
VLO
Low-Side Output Voltage
VIN
10
20
V
COM
VDD
V
Logic Input Voltage (HIN and LIN)
VSS
VDD
V
DT
Programmable Dead-Time Pin Voltage
VSS
VDD
V
VSS
Logic Ground
-5
+5
V
Operating Ambient Temperature
-40
+125
°C
TA
© 2009 Fairchild Semiconductor Corporation
FAN73933 • Rev. 1.0.0
www.fairchildsemi.com
4
FAN73933 — Half-Bridge Gate Driver
Absolute Maximum Ratings
VBIAS(VDD, VBS)=15.0V, VSS=COM=0V, DT=VSS and TA = 25°C, unless otherwise specified. The VIN and IIN
parameters are referenced to VSS/COM and are applicable to the respective input leads: HIN and LIN. The VO and IO
parameters are referenced to COM and are applicable to the respective output leads: HO and LO.
Symbol
Characteristics
Test Condition
Min. Typ. Max. Unit
POWER SUPPLY SECTION
IQDD
Quiescent VDD Supply Current
VIN=0V or 5V
0.9
1.5
mA
IQBS
Quiescent VBS Supply Current
VIN=0V or 5V
50
100
μA
IPDD
Operating VDD Supply Current
fIN=20KHz, No Load
1.3
1.9
mA
IPBS
Operating VBS Supply Current
CL=1nF, fIN=20KHz, rms
450
800
μA
Offset Supply Leakage Current
VB=VS=600V
10
μA
ILK
BOOTSTRAPPED SUPPLY SECTION
VDDUV+
VBSUV+
VDD and VBS Supply Under-Voltage
Positive-Going Threshold Voltage
VIN=0V, VDD=VBS=Sweep
8.0
9.0
10
V
VDDUVVBSUV-
VDD and VBS Supply Under-Voltage
Negative-Going Threshold Voltage
VIN=0V, VDD=VBS=Sweep
7.4
8.4
9.4
V
VDD and VBS Supply Under-Voltage Lockout
Hysteresis Voltage
VIN=0V, VDD=VBS=Sweep
VDDUVHVBSUVH
0.6
V
INPUT LOGIC SECTION
VIH
Logic “1” Input Voltage for HO & Logic “0” for LO
VIL
Logic “0” Input Voltage for HO & Logic “1” for LO
IIN+
Logic Input High Bias Current
VIN=5V
IIN-
Logic Input Low Bias Current
VIN=0V
RIN
Logic Input Pull-Down Resistance
2.5
V
20
0.8
V
50
μA
2
100
250
μA
KΩ
GATE DRIVER OUTPUT SECTION
VOH
High-Level Output Voltage (VBIAS - VO)
No Load
1.5
V
VOL
Low-Level Output Voltage
No Load
100
mV
IO+
Output High, Short-Circuit Pulsed Current(4)
VHO=0V, VIN=5V, PW
≤10µs
2.0
2.5
A
IO-
Output Low, Short-Circuit Pulsed Current(4)
VHO=15V,VIN=0V, PW
≤10µs
2.0
2.5
A
VS
Allowable Negative VS Pin Voltage for IN Signal
Propagation to HO
-9.8
-7.0
V
Note:
4. These parameters guaranteed by design.
© 2009 Fairchild Semiconductor Corporation
FAN73933 • Rev. 1.0.0
www.fairchildsemi.com
5
FAN73933 — Half-Bridge Gate Driver
Electrical Characteristics
VBIAS(VDD, VBS)=15.0V, VSS=COM=0V, CL=1000pF, DT=VSS and TA=25°C, unless otherwise specified.
Symbol
Typ.
Max.
Unit
tON
Turn-On Propagation Delay Time(5)
Parameter
VS=0V, RDT=0Ω
Conditions
Min.
160
230
ns
tOFF
Turn-Off Propagation Delay Time
VS=0V
160
230
ns
MtON
Delay Matching, HO & LO Turn-On
0
50
ns
0
50
ns
tR
Turn-On Rise Time
VS=0V
40
60
ns
tF
Turn-Off Fall Time
VS=0V
20
35
ns
DT
Dead Time: LO Turn-Off to HO Turn-On &
HO Turn-Off to LO Turn-On
RDT=0Ω
170
220
270
ns
RDT=300KΩ
400
MtOFF
MDT
Delay Matching, HO & LO Turn-Off
Dead-Time Matching=|DTLO-HO - DTHO-LO|
500
600
ns
RDT=0Ω
0
50
ns
RDT=300KΩ
0
100
ns
Note:
5 The turn-on propagation display does not include dead time.
© 2009 Fairchild Semiconductor Corporation
FAN73933 • Rev. 1.0.0
www.fairchildsemi.com
6
FAN73933 — Half-Bridge Gate Driver
Dynamic Electrical Characteristics
230
210
210
190
190
tOFF [ns]
tON [ns]
230
170
150
150
130
130
High-Side
Low-Side
110
90
-40
170
-20
0
20
40
60
80
100
High-Side
Low-Side
110
90
-40
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 4. Turn-On Propagation Delay
vs. Temperature
Figure 5. Turn-Off Propagation Delay
vs. Temperature
60
High-Side
Low-Side
50
tF [ns]
40
tR [ns]
High-Side
Low-Side
30
30
20
20
10
10
0
-40
-20
0
20
40
60
80
100
0
-40
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 6. Turn-On Rise Time
vs. Temperature
Figure 7. Turn-Off Fall Time
vs. Temperature
300
50
MDT [ns]
DT [ns]
25
250
0
200
-25
DT1
DT2
(RDT=0Ω)
150
-40
-20
0
20
40
60
80
100
(RDT=0Ω)
-50
-40
120
Temperature [°C]
-20
0
20
40
60
80
100
120
Temperature [°C]
Figure 8. Dead Time (RDT=0Ω) vs. Temperature
Figure 9. Dead Time Matching (RDT=0Ω)
vs. Temperature
© 2009 Fairchild Semiconductor Corporation
FAN73933 • Rev. 1.0.0
www.fairchildsemi.com
7
FAN73933 — Half-Bridge Gate Driver
Typical Characteristics
50
600
575
40
MDT [ns]
550
DT [ns]
525
500
30
20
475
450
400
-40
10
DT1
DT2
(RDT=300KΩ)
425
-20
0
20
40
60
80
100
(RDT=300KΩ)
0
-40
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 10. Dead Time (RDT=300KΩ) vs. Temperature
Figure 11. Dead Time Matching (RDT=300KΩ)
vs. Temperature
600
50
Delay Matching [ns]
40
500
30
DT [ns]
20
10
0
-10
300
-20
MTON
-30
200
MTOFF
-40
-50
-40
400
(RDT=0Ω)
-20
0
20
40
60
80
100
100
0
120
50
100
Figure 12. Delay Matching vs. Temperature
200
250
300
Figure 13. Dead Time vs. RDT
1500
100
1300
80
IQBS [μA]
IQDD [μA]
150
RDT [KΩ]
Temperature [°C]
1100
900
60
40
700
20
500
300
-40
-20
0
20
40
60
80
100
0
-40
120
Figure 14. Quiescent VDD Supply Current
vs. Temperature
© 2009 Fairchild Semiconductor Corporation
FAN73933 • Rev. 1.0.0
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 15. Quiescent VBS Supply Current
vs. Temperature
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8
FAN73933 — Half-Bridge Gate Driver
Typical Characteristics (Continued)
800
1900
700
1700
600
IPBS [μA]
IPDD [μA]
1500
1300
1100
400
300
900
700
-40
500
200
-20
0
20
40
60
80
100
100
-40
120
-20
0
10.0
9.5
9.5
9.0
9.0
8.5
80
100
120
8.0
-20
0
20
40
60
80
100
7.5
-40
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Figure 18. VDD UVLO+ vs. Temperature
Figure 19. VDD UVLO- vs. Temperature
10.0
9.5
9.5
9.0
VBSUV- [V]
VBSUV+ [V]
60
8.5
Temperature [°C]
9.0
8.5
8.0
8.5
8.0
-40
40
Figure 17. Operating VBS Supply Current
vs. Temperature
VDDUV- [V]
VDDUV+ [V]
Figure 16. Operating VCC Supply Current
vs. Temperature
8.0
-40
20
Temperature [°C]
Temperature [°C]
-20
0
20
40
60
80
100
7.5
-40
120
Figure 20. VBS UVLO+ vs. Temperature
© 2009 Fairchild Semiconductor Corporation
FAN73933 • Rev. 1.0.0
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 21. VBS UVLO- vs. Temperature
www.fairchildsemi.com
9
FAN73933 — Half-Bridge Gate Driver
Typical Characteristics (Continued)
0.4
2.0
High-Side
Low-Side
High-Side
Low-Side
0.2
VOL [V]
VOH [V]
1.5
1.0
0.0
-0.2
0.5
0.0
-40
-20
0
20
40
60
80
100
-0.4
-40
120
-20
0
Figure 22. High-Level Output Voltage
vs. Temperature
60
80
100
120
3.0
High-Side
Low-Side
High-Side
Low-Side
2.5
2.5
VIH [V]
VIH [V]
40
Figure 23. Low-Level Output Voltage
vs. Temperature
3.0
2.0
1.5
2.0
1.5
1.0
-40
-20
0
20
40
60
80
100
1.0
-40
120
-20
0
Temperature [°C]
20
40
60
80
100
120
Temperature [°C]
Figure 24. Logic High Input Voltage
vs. Temperature
Figure 25. Logic Low Input Voltage
vs. Temperature
-7
50
High-Side
Low-Side
-8
40
-9
VS [V]
IIN+ [μA]
20
Temperature [°C]
Temperature [°C]
30
-10
20
-11
10
0
-40
-12
-20
0
20
40
60
80
100
-13
-40
120
Figure 26. Logic Input High Bias Current
vs. Temperature
© 2009 Fairchild Semiconductor Corporation
FAN73933 • Rev. 1.0.0
-20
0
20
40
60
80
100
120
Temperature [°C]
Temperature [°C]
Figure 27. Allowable Negative VS Voltage
vs. Temperature
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10
FAN73933 — Half-Bridge Gate Driver
Typical Characteristics (Continued)
230
210
210
190
190
tOFF [ns]
tON [ns]
230
170
150
130
150
130
High-Side
Low-Side
110
90
10
170
12
14
16
18
High-Side
Low-Side
110
90
10
20
12
Supply Voltage [V]
Figure 28. Turn-On Propagation Delay
vs. Supply Voltage
16
18
20
Figure 29. Turn-Off Propagation Delay
vs. Supply Voltage
60
35
High-Side
Low-Side
50
High-Side
Low-Side
30
25
tF [ns]
40
tR [ns]
14
Supply Voltage [V]
30
20
15
20
10
10
0
10
5
12
14
16
18
0
10
20
12
Supply Voltage [V]
Figure 30. Turn-On Rise Time
vs. Supply Voltage
16
18
20
Figure 31. Turn-Off Fall Time
vs. Supply Voltage
1500
100
1300
80
IQBS [μA]
IQDD [μA]
14
Supply Voltage [V]
1100
900
60
40
700
20
500
300
10
12
14
16
18
0
10
20
Figure 32. Quiescent VDD Supply Current
vs. Supply Voltage
© 2009 Fairchild Semiconductor Corporation
FAN73933 • Rev. 1.0.0
12
14
16
18
20
Supply Voltage [V]
Supply Voltage [V]
Figure 33. Quiescent VBS Supply Current
vs. Supply Voltage
www.fairchildsemi.com
11
FAN73933 — Half-Bridge Gate Driver
Typical Characteristics (Continued)
0.4
2.0
High-Side
Low-Side
High-Side
Low-Side
0.2
VOL [V]
VOH [V]
1.5
1.0
-0.2
0.5
0.0
10
0.0
12
14
16
18
-0.4
10
20
Figure 34. High-Level Output Voltage
vs. Supply Voltage
© 2009 Fairchild Semiconductor Corporation
FAN73933 • Rev. 1.0.0
12
14
16
18
20
Supply Voltage [V]
Supply Voltage [V]
Figure 35. Low-Level Output Voltage
vs. Supply Voltage
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12
FAN73933 — Half-Bridge Gate Driver
Typical Characteristics (Continued)
FAN73933 — Half-Bridge Gate Driver
Switching Time Definitions
1
HIN
NC 14
LIN
2
LIN
VB 13
3
VSS
LO
FAN73933
HIN
+15V
HO 12
HO
1nF
4
DT
VS 11
5
COM
6
LO
NC
9
7
VDD
NC
8
10μF 100nF
NC 10
1nF
+15V
10μF
100nF
Figure 36. Switching Time Test Circuit
LIN
HIN
Shoot Though
Prevent
LO
Shoot Though
Prevent
HO
DT
DT
DT
DT
Figure 37. Input/Output Timing Diagram
LIN
50%
50%
More than dead-time
HIN
50%
More than dead-time
50%
50%
tOFF
tOFF
90%
90%
tON
LO
10%
tOFF
90%
tON
HO
10%
Figure 38. Switching Time Waveform Definitions
© 2009 Fairchild Semiconductor Corporation
FAN73933 • Rev. 1.0.0
www.fairchildsemi.com
13
Negative VS Transient
Figure 41. and Figure 42. show the commutation of the
load current between the high-side switch, Q1, and lowside freewheelling diode, D3, in same inverter leg. The
parasitic inductances in the inverter circuit from the die
wire bonding to the PCB tracks are jumped together in
LC and LE for each IGBT. When the high-side switch, Q1,
and low-side switch, Q4, are turned on; the VS1 node is
below DC+ voltage by the voltage drops associated with
the power switch and the parasitic inductances of the circuit due to load current is flows from Q1 and Q4, as
shown in Figure 41. When the high-side switch, Q1, is
turned off and Q4 remains turned on, the load current to
flows the low-side freewheeling diode, D3, due to the
inductive load connected to VS1 as shown in Figure 42.
The current flows from ground (which is connected to the
COM pin of the gate driver) to the load and the negative
voltage present at the emitter of the high-side switching
device.
The bootstrap circuit has the advantage of being simple
and low cost, but has some limitations. The biggest difficulty with this circuit is the negative voltage present at
the emitter of the high-side switching device when the
high-side switch is turned off in half-bridge applications.
If the high-side switch, Q1, turns-off while the load current is flowing to an inductive load; a current commutation occurs from high-side switch, Q1, to the diode, D2,
in parallel with the low-side switch of the same inverter
leg. Then the negative voltage present at the emitter of
the high-side switching device, just before the freewheeling diode, D2, starts clamping, causes load current to
suddenly flow to the low-side freewheeling diode, D2, as
shown in Figure 39.
DC+ Bus
Q2
Q1
D1
D2
In this case, the COM pin of the gate driver is at a higher
potential than the VS pin due to the voltage drops associated with freewheeling diode, D3, and parasitic elements, LC3 and LE3.
iLOAD
ifreewheeling
Load
VS1
VS2
DC+ Bus
Q4
Q3
D3
LC1
D4
LC2
VLC1
Q2
Q1
D1
D2
iLOAD
LE1
Figure 39. Half-Bridge Application Circuits
VLE1
ifreewheeling
This negative voltage can be trouble for the gate driver’s
output stage. There is the possibility to develop an overvoltage condition of the bootstrap capacitor, input signal
missing, and latch-up problems because it directly
affects the source VS pin of the gate driver, as shown in
Figure 40. This undershoot voltage is called “negative VS
transient.
LE2
Load
VS1
VS2
LC3
VLC4
LC4
Q4
Q3
D3
D4
LE3
VLE4
LE4
Figure 41. Q1 and Q4 Turn-On
DC+ Bus
Q1
GND
LC2
LC1
Q2
Q1
D1
D2
iLOAD
ifreewheeling
LE1
VS
LC3
GND
LE2
Load
VS1
VLC3
VS2
VLC4
Freewheeling
D3
LE3
LC4
Q4
Q3
VLE3
D4
VLE4
LE4
Figure 40. VS Waveforms During Q1 Turn-Off
Figure 42. Q1 Turn-Off and D3 Conducting
© 2009 Fairchild Semiconductor Corporation
FAN73933 • Rev. 1.0.0
www.fairchildsemi.com
14
FAN73933 — Half-Bridge Gate Driver
Application Information
The recommended selection of component is as follows:
Place a bypass capacitor between the VDD and VSS
pins. A ceramic 1µF capacitor is suitable for most
applications. This component should be placed as
close as possible to the pins to reduce parasitic elements.
The bypass capacitor from VCC to COM supports both
the low-side driver and bootstrap capacitor recharge.
A value at least ten times higher than the bootstrap
capacitor is recommended.
The bootstrap resistor, RBOOT, must be considered in
sizing the bootstrap resistance and the current developed during initial bootstrap charge. If the resistor is
needed in series with the bootstrap diode, verify that
VB does not fall below COM (ground). Recommended
use is typically 5 ~ 10Ω, which increases the VBS time
constant. If the votage drop of the bootstrap resistor
and diode is too high or the circuit topology does not
allow a sufficient charging time, a fast recovery or
ultra-fast recovery diode can be used.
The bootstrap capacitor, CBOOT, uses a low-ESR
capacitor, such as a ceramic capacitor.
-100
-90
-80
-70
VS [V]
-60
-50
-40
-30
-20
-10
0
0
100
200
300
400
500
600
700
800
900 1000
Pulse Width [ns]
Figure 43. Negative VS Transient Chracteristic
Even though the FAN73933 has been shown able to
handle these negative VS tranient conditions, it is
strongly recommended that the circuit designer limit the
negative VS transient as much as possible by careful
PCB layout to minimize the value of parasitic elements
and component use. The amplitude of negative VS voltage is proportional to the parasitic inductances and the
turn-off speed, di/dt, of the switching device.
It is stongly recommended that the placement of components is as follows:
Place components tied to the floating voltage pins (VB
and VS) near the respective high-voltage portions of
the device and the FAN73933. NC (not connected)
pins in this package maximize the distance between
the high-voltage and low-voltage pins (see Figure 3.).
Place and route for bypass capacitors and gate resistors as close as possible to gate drive IC.
Locate the bootstrap diode, DBOOT, as close as possible to bootstrap capacitor, CBOOT.
The bootstrap diode must use a lower forward voltage
drop and minimal switching time as soon as possible
for fast recovery or ultra-fast diode.
General Guidelines
Printed Circuit Board Layout
The layout recommended for minimized parasitic elements is as follows:
Direct tracks between switches with no loops or devia-
tion.
Avoid interconnect links. These can add significant
inductance.
Reduce the effect of lead-inductance by lowering
package height above the PCB.
Consider co-locating both power switches to reduce
track length.
To minimize noise coupling, the ground plane should
not be placed under or near the high-voltage floating
side.
To reduce the EM coupling and improve the power
switch turn-on/off performance, the gate drive loops
must be reduced as much as possible.
© 2009 Fairchild Semiconductor Corporation
FAN73933 • Rev. 1.0.0
www.fairchildsemi.com
15
FAN73933 — Half-Bridge Gate Driver
Placement of Components
The FAN73933 has a negative VS transient performance
curve, as shown in Figure 43.
8.76
8.36
0.65
A
7.62
14
8
B
5.60
6.00
4.15
3.75
B
1.70
B
#1
1.27
PIN ONE
INDICATOR
7
#1
1.27
(0.27)
TOP VIEW
0.51
0.36
0.20
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
1.80 MAX
1.65
1.45
(R0.20)
C
0.30
0.15
B
0.05MIN
1.27
SIDE VIEW
END VIEW
0.10 MAX C
NOTES:
A) THIS DRAWING COMPLIES WITH JEDEC MS-012
EXCEPT AS NOTED.
B) THIS DIMENSION IS OUTSIDE THE JEDEC MS-012 VALUE.
C) ALL DIMENSIONS ARE IN MILLIMETERS.
D) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS.
E) LANDPATTERN STANDARD: SOIC127P600X145-14M
F) DRAWING FILE NAME AND REVISION : M14CREV1
8°
GAGE
PLANE
(R0.10)
0.90
0.50
0.36
SEATING
PLANE
DETAIL A
Figure 44. 14-Lead, Small Outline Integrated Circuit (SOIC), Non-JEDEC, .150 Inch Narrow Body, 225SOP
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2009 Fairchild Semiconductor Corporation
FAN73933 • Rev. 1.0.0
www.fairchildsemi.com
16
FAN73933 — Half-Bridge Gate Driver
Physical Dimensions
FAN73933 — Half-Bridge Gate Driver
© 2009 Fairchild Semiconductor Corporation
FAN73933 • Rev. 1.0.0
www.fairchildsemi.com
17