LINER LTC4258

LTC4266
Quad IEEE 802.3at Power
over Ethernet Controller
DESCRIPTION
FEATURES
Four Independent PSE Channels
n Compliant with IEEE 802.3at Type 1 and 2
n 0.34Ω Total Channel Resistance
130mW/Port at 600mA
n Advanced Power Management
8-Bit Programmable Current Limit (I
LIM)
7-Bit Programmable Overload Currents (I
CUT)
Fast Shutdown of Preselected Ports
14.5-Bit Port Current/Voltage Monitoring
2-Event Classification
n Very High Reliability 4-Point PD Detection:
2-Point Forced Voltage
2-Point Forced Current
n High Capacitance Legacy Device Detection
n LTC4259A-1 and LTC4258 Pin and SW Compatible
n 1MHz I2C Compatible Serial Control Interface
n Midspan Backoff Timer
n Supports Proprietary Power Levels Above 25W
n Available in 38-Pin 5mm × 7mm QFN and 36-Pin
SSOP Packages
n
APPLICATIONS
High Power PSE Switches/Routers
n High Power PSE Midspans
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
The LTC®4266 is a quad PSE controller designed for use
in IEEE 802.3 Type 1 and Type 2 (high power) compliant
Power over Ethernet systems. External power MOSFETs
enhance system reliability and minimize channel resistance, cutting power dissipation and eliminating the need
for heatsinks even at Type 2 power levels. External power
components also allow use at very high power levels while
remaining otherwise compatible with the IEEE standard.
80V-rated port pins provide robust protection against
external faults.
The LTC4266 includes advanced power management
features, including current and voltage readback and programmable ICUT and ILIM thresholds. Available C libraries
simplify power-management software development; an
optional AUTO pin mode provides fully IEEE-compliant
standalone operation with no software required. Proprietary
4-point PD detection circuitry minimizes false PD detection while supporting legacy phone operation. Midspan
operation is supported with built-in 2-event classification
and backoff timing. Host communication is via a 1MHz
I2C serial interface.
The LTC4266 is available in a 5mm × 7mm QFN package
that significantly reduces board space compared with
competing solutions. A legacy-compatible 36-pin SSOP
package is also available.
TYPICAL APPLICATION
Complete 4-Port Ethernet High Power Source
3.3V
0.1µF
INT SHDN1 SHDN2 SHDN3 SHDN4
AUTO MSD RESET MID
VDD
SCL
SDAIN
SDAOUT
AD0
LTC4266
AD1
AD2
AD3
DGND AGND VEE SENSE1 GATE1 OUT1 SENSE2 GATE2 OUT2 SENSE3 GATE3 OUT3 SENSE4 GATE4 OUT4
0.22µF 100V
×4
S1B
×4
S1B
×4
–50V
PORT1
–50V
SMAJ58A
PORT2
1µF
PORT3
4266 TA01
PORT4
4266fb
1
LTC4266
ABSOLUTE MAXIMUM RATINGS
Supply Voltages (Note 1)
AGND – VEE............................................ –0.3V to 80V
DGND – VEE............................................ –0.3V to 80V
VDD – DGND.......................................... –0.3V to 5.5V
Digital Pins
SCL, SDAIN, SDAOUT, INT, SHDNn, MSD, ADn,
RESET, AUTO, MID............ DGND –0.3V to VDD + 0.3V
Analog Pins
GATEn, SENSEn, OUTn........... VEE –0.3V to VEE + 80V
Operating Temperature Range
LTC4266C................................................. 0°C to 70°C
LTC4266I..............................................–40°C to 85°C
Junction Temperature (Note 2).............................. 125°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................... 300°C
PIN CONFIGURATION
TOP VIEW
INT
3
34 OUT1
SCL
4
33 GATE1
SDAOUT
5
32 SENSE1
SDAIN
6
31 OUT2
OUT1
29 OUT2
30 GATE2
AD3 4
28 GATE2
27 SENSE2
AD2
8
29 SENSE2
AD1
9
28 VEE
AD1 6
27 OUT3
NC 11
26 GATE3
NC 12
25 SENSE3
NC 13
24 OUT4
NC 14
23 GATE4
22 SENSE3
21 OUT4
NC 11
20 GATE4
NC 12
SENSE4
AGND
SHDN4
13 14 15 16 17 18 19
SHDN3
19 SHDN3
23 GATE3
DGND 10
VDD
20 SHDN4
24 OUT3
NC 9
21 AGND
SHDN2 18
25 VEE
DNC 8
22 SENSE4
SHDN1 17
26 VEE
39
AD0 7
AD0 10
VDD 16
30 SENSE1
SDAIN 3
AD2 5
DGND 15
31 GATE1
NC 2
SHDN2
7
38 37 36 35 34 33 32
SDAOUT 1
SHDN1
AD3
AUTO
35 AUTO
MSD
2
RESET
MID
MID
36 MSD
INT
1
SCL
TOP VIEW
RESET
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
EXPOSED PAD IS VEE (PIN 39) MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 34°C/W
GW36 PACKAGE
36-LEAD PLASTIC WIDE SSOP
TJMAX = 125°C, θJA = 80°C/W
ORDER INFORMATION
LEAD FREE FINISH
LTC4266CGW#PBF
LTC4266IGW#PBF
LTC4266CUHF#PBF
LTC4266IUHF#PBF
TAPE AND REEL
LTC4266CGW#TRPBF
LTC4266IGW#TRPBF
LTC4266CUHF#TRPBF
LTC4266IUHF#TRPBF
PART MARKING*
LTC4266
LTC4266
4266
4266
PACKAGE DESCRIPTION
TEMPERATURE RANGE
36-Lead Plastic Wide SSOP
0°C to 70°C
36-Lead Plastic Wide SSOP
–40°C to 85°C
0°C to 70°C
38-Lead (5mm × 7mm) Plastic QFN
–40°C to 85°C
38-Lead (5mm × 7mm) Plastic QFN
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
4266fb
2
LTC4266
ELECTRICAL
CHARACTERISTICS
The
l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless
otherwise noted. (Notes 3, 4)
SYMBOL
PARAMETER
CONDITIONS
–48V Supply Voltage
AGND – VEE
For IEEE Type 1 Complaint Output
For IEEE Type 2 Complaint Output
Undervoltage Lock-out Level
VDD
VDD Supply Voltage
VDD – DGND
Undervoltage Lock-out
MIN
l
l
45
51
l
20
l
3.0
DGND – VEE
l
IEE
VEE Supply Current
(AGND – VEE) = 55V
l
IDD
VDD Supply Current
(VDD – DGND) = 3.3V
l
Detection Current – Force Current
First Point, AGND – VOUTn = 9V
Second Point, AGND – VOUTn = 3.5V
l
l
Detection Voltage – Force Voltage
AGND – VOUTn, 5µA ≤ IOUTn ≤ 500µA
First Point
Second Point
l
l
Detection Current Compliance
AGND – VOUTn = 0V
Detection Voltage Compliance
Detection Voltage Slew Rate
MAX
UNITS
57
57
V
V
25
30
V
3.3
4.3
2.2
l
Allowable Digital Ground Offset
TYP
25
V
V
57
V
–2.4
–5
mA
1.1
3
mA
220
140
240
160
260
180
µA
µA
7
3
8
4
9
5
V
V
l
0.8
0.9
mA
AGND – VOUTn, Open Port
l
10.4
12
V
AGND – VOUTn, CPORT = 0.15µF
l
Detection
VOC
0.01
V/µs
Min. Valid Signature Resistance
l
15.5
17
18.5
kΩ
Max. Valid Signature Resistance
l
27.5
29.7
32
kΩ
16.0
Classification
VCLASS
VMARK
Classification Voltage
AGND – VOUTn, 0mA ≤ ICLASS ≤ 50mA
l
20.5
V
Classification Current Compliance
VOUTn = AGND
l
53
61
67
mA
Classification Threshold Current
Class 0 – 1
Class 1 – 2
Class 2 – 3
Class 3 – 4
Class 4 – Overcurrent
l
l
l
l
l
5.5
13.5
21.5
31.5
45.2
6.5
14.5
23
33
48
7.5
15.5
24.5
34.9
50.8
mA
mA
mA
mA
mA
Classification Mark State Voltage
AGND – VOUTn, 0.1mA ≤ ICLASS ≤ 10mA
l
7.5
9
10
V
Mark State Current Compliance
VOUTn = AGND
l
53
61
67
mA
GATE Pin Pull-Down Current
Port Off, VGATEn = VEE + 5V
Port Off, VGATEn = VEE + 1V
l
l
0.4
0.08
0.12
Gate Driver
GATE Pin Fast Pull-Down Current
VGATEn = VEE + 5V
GATE Pin On Voltage
VGATEn – VEE, IGATEn = 1µA
l
8
Power Good Threshold Voltage
VOUTn – VEE
l
2
OUT Pin Pull-Up Resistance to AGND
0V ≤ (AGND – VOUTn) ≤ 5V
l
300
mA
mA
30
mA
14
V
2.4
2.8
V
500
700
kΩ
Output Voltage Sense
VPG
4266fb
3
LTC4266
The
l denotes the specifications which apply over the full operating
ELECTRICAL
CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless
otherwise noted. (Notes 3, 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Overcurrent Sense Voltage
VSENSEn – VEE, icut12 = icut34 = hpen = 00h
hpen = 0Fh, cutn[5:0] ≥ 4 (Note 12)
cutrng = 0
cutrng = 1
l
180
188
196
mV
l
l
9
4.5
9.38
4.69
9.75
4.88
mV/LSB
mV/LSB
Overcurrent Sense in AUTO pin mode
Class 0, Class 3
Class 1
Class 2
Class 4
l
l
l
l
90
26
49
152
94
28
52
159
98
30
55
166
mV
mV
mV
mV
Active Current Limit in 802.3af Compliant
Mode
VSENSEn – VEE, dblpwr = hpen = 00h
VEE = 55V (Note 12)
VEE < VOUT < AGND – 29V
AGND – VOUT = 0V
l
l
204
40
212
220
100
mV
mV
hpen = 0Fh, limn = C0h, VEE = 55V
VOUT – VEE = 0V to 10V
VEE + 23V < VOUT < AGND – 29V
AGND – VOUT = 0V
l
l
l
204
100
20
212
106
221
113
50
mV
mV
mV
VOUT – VEE = 0V to 10V, VEE = 55V
Class 0 to Class 3
Class 4
l
l
102
204
106
212
110
221
mV
mV
Current Sense
VCUT
VLIM
VLIM
VLIM
Active Current Limit in High Power Mode
Active Current Limit in AUTO pin mode
VMIN
DC Disconnect Sense Voltage
VSENSEn – VEE, rdis = 0
VSENSEn – VEE, rdis = 1
l
l
2.6
1.3
3.8
1.9
4.8
2.41
mV
mV
VSC
Short-Circuit Sense
VSENSEn – VEE – VLIM, rdis = 0
VSENSEn – VEE – VLIM, rdis = 1
l
l
160
75
200
100
255
135
mV
mV
Port Current ReadBack
Resolution
No missing codes, fast_iv = 0
14
bits
LSB Weight
VSENSEn – VEE
50-60Hz Noise Rejection
(Note 7)
30
dB
Resolution
No missing codes, fast_iv = 0
14
bits
LSB Weight
AGND – VOUTn
50-60Hz noise rejection
(Note 7)
30.5
µV/LSB
Port Voltage ReadBack
5.835
mV/LSB
30
dB
Digital Interface
VILD
Digital Input Low Voltage
(Note 6)
l
0.8
VIHD
Digital Input High Voltage
(Note 6)
l
Digital Output Low Voltage
ISDAOUT = 3mA, IINT = 3mA
ISDAOUT = 5mA, IINT = 5mA
l
l
Internal Pull-Up to VDD
ADn, SHDNn, RESET, MSD
50
kΩ
Internal Pull-Down to DGND
AUTO, MID
50
kΩ
2.2
V
V
0.4
0.7
V
V
4266fb
4
LTC4266
The
l denotes the specifications which apply over the full operating
ELECTRICAL
CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless
otherwise noted. (Notes 3, 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
290
310
ms
470
ms
Timing Characteristics
tDET
Detection Time
Beginning to End of Detection (Note 7)
l
270
tDETDLY
Detection Delay
From PD Connected to Port to Detection
Complete (Note 7)
l
300
tCLE1
First Class Event Duration
(Note 7)
l
11
12
13
ms
tME1
First Mark Event Duration
(Notes 7, 11)
l
6.8
8.6
10.3
ms
tCLE2
Second Class Event Duration
(Note 7)
l
11
12
13
ms
tME2
Second Mark Event Duration
(Note 7)
l
19
22
tCLE3
Third Class Event Duration
CPORT = 0.6µF (Note 7)
l
0.1
ms
tPON
Power On Delay in AUTO pin mode
From End of Valid Detect to Application of
Power to Port (Note 7)
l
60
ms
Turn On Rise Time
(AGND – VOUT): 10% to 90% of
(AGND – VEE), CPORT = 0.15µF (Note 7)
l
Turn On Ramp Rate
CPORT = 0.15µF (Note 7)
l
Fault Delay
From ICUT Fault to Next Detect
l
1.0
1.1
Midspan Mode Detection Backoff
Rport = 15.5kΩ (Note 7)
l
2.3
2.5
2.7
s
Power Removal Detection Delay
From Power Removal After tDIS to Next
Detect (Note 7)
l
1.0
1.3
2.5
s
15
ms
24
µs
10
V/µs
s
tSTART
Maximum Current Limit Duration During Port tSTART1 = 0, tSTART0 = 0 (Notes 7, 12)
Start-Up
l
52
62.5
66
ms
tLIM, tICUT
Maximum Current Limit Duration After Port
Start-Up
tICUT1 = 0, tICUT0 = 0 (Notes 7, 12)
l
52
62.5
66
ms
Maximum Current Limit Duty Cycle
(Note 7)
l
5.8
6.3
6.7
%
3.6
ms
380
ms
6.5
µs
6.5
µs
3
s
tMPS
Maintain Power Signature (MPS) Pulse Width Current Pulse Width to Reset Disconnect
Sensitivity
Timer (Notes 7, 8)
l
1.6
tDIS
Maintain Power Signature (MPS) Dropout
Time
tconf [1:0] = 00b (Notes 5, 12)
l
320
tMSD
Masked Shut Down Delay
(Note 7)
l
tSHDN
Port Shut Down Delay
(Note 7)
l
I2C Watchdog Timer Duration
l
1.5
350
2
Minimum Pulse Width for Masked Shut
Down
(Note 7)
l
3
µs
Minimum Pulse Width for SHDN
(Note 7)
l
3
µs
Minimum Pulse Width for RESET
(Note 7)
l
4.5
µs
4266fb
5
LTC4266
The
l denotes the specifications which apply over the full operating
ELECTRICAL
CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless
otherwise noted. (Notes 3, 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Clock Frequency
(Note 7)
l
t1
Bus Free Time
Figure 5 (Notes 7, 9)
l
480
ns
t2
Start Hold Time
Figure 5 (Notes 7, 9)
l
240
ns
t3
SCL Low Time
Figure 5 (Notes 7, 9)
l
480
ns
t4
SCL High Time
Figure 5 (Notes 7, 9)
l
240
ns
t5
Data Hold Time
Figure 5 (Notes 7, 9) Data into chip
Data out of chip
l
l
60
t6
Data Set-Up Time
Figure 5 (Notes 7, 9)
l
80
ns
t7
Start Set-Up Time
Figure 5 (Notes 7, 9)
l
240
ns
t8
Stop Set-Up Time
Figure 5 (Notes 7, 9)
l
240
ns
tr
SCL, SDAIN Rise Time
Figure 5 (Notes 7, 9)
l
120
ns
tf
SCL, SDAIN Fall Time
Figure 5 (Notes 7, 9)
l
60
ns
Fault Present to INT Pin Low
(Notes 7, 9, 10)
l
150
ns
Stop Condition to INT Pin Low
(Notes 7, 9, 10)
l
1.5
µs
ARA to INT Pin High Time
(Notes 7, 9)
l
1.5
µs
SCL Fall to ACK Low
(Notes 7, 9)
l
120
ns
I2C Timing
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 140°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative.
Note 4: The LTC4266 operates with a negative supply voltage (with respect
to ground). To avoid confusion, voltages in this data sheet are referred to
in terms of absolute magnitude.
Note 5: tDIS is the same as tMPDO defined by IEEE 802.3at.
1
120
MHz
ns
ns
Note 6: The LTC4266 digital interface operates with respect to DGND. All
logic levels are measured with respect to DGND.
Note 7: Guaranteed by design, not subject to test.
Note 8: The IEEE 802.3af specification allows a PD to present its
Maintain Power Signature (MPS) on an intermittent basis without being
disconnected. In order to stay powered, the PD must present the MPS for
tMPS within any tMPDO time window.
Note 9: Values measured at VILD(MAX) and VIHD(MIN).
Note 10: If fault condition occurs during an I2C transaction, the INT pin
will not be pulled down until a stop condition is present on the I2C bus.
Note 11: Load Characteristic of the LTC4266 during Mark:
7V < (AGND – VOUTn) < 10V or IOUT < 50µA
Note 12: See the LTC4266 Software Programming documentation for
information on serial bus usage and device configuration and status
registers.
4266fb
6
LTC4266
TYPICAL PERFORMANCE CHARACTERISTICS
Power On Sequence
in AUTO Pin Mode
10
0
GND
PORT VOLTAGE (V)
FORCED VOLTAGE
DETECTION
–40
PORT 1
VDD = 3.3V
VEE = –54V
–50
–60
VDD = 3.3V
VEE = –54V
PORT
VOLTAGE
20V/DIV
–10
–30
GND
GND
FORCED CURRENT DETECTION
–20
802.3af Classification
in AUTO Pin Mode
Powering Up into a 180µF Load
LOAD
FULLY
CHARGED
VEE
PORT
CURRENT
200 mA/DIV
802.3af
CLASSIFICATION
POWER ON
FOLDBACK
0mA
GATE
VOLTAGE
10V/DIV VEE
VEE
–70
–18.4
FET ON
VEE
5ms/DIV
100ms/DIV
5ms/DIV
4266 G02
4266 G01
4266 G03
Classification Transient Response
to 40mA Load Step
GND
PORT
CURRENT
20mA/DIV
–17.6
40mA
Classification Current Compliance
0
VDD = 3.3V
VEE = –54V
0mA
1ST CLASS EVENT
2ND CLASS EVENT
PORT 1
VDD = 3.3V
VEE = –55V
PD IS CLASS 4
PORT
VOLTAGE
1V/DIV
VEE
–20V
–8
–10
–12
–14
–16
2.4
1.5
1.3
1.2
1.1
1.0
0.9
2.7
2.9
3.1 3.3 3.5 3.7 3.9
VDD SUPPLY VOLTAGE (V)
4.1
4.3
4266 G07
20
30
40
50
60
CLASSIFICATION CURRENT
70
802.3at ILIM Threshold vs
Temperature
215
214
2.3
2.2
2.1
–40°C
25°C
85°C
2.0
–60 –55 –50 –45 –40 –35 –30 –25 –20
VEE SUPPLY VOLTAGE (V)
4266 G08
860
VDD = 3.3V
VEE = –54V
RSENSE = 0.25Ω
REG 48h = C0h
856
213
852
212
848
211
844
210
–40
0
40
–80
TEMPERATURE (°C)
ILIM (mA)
1.4
10
4266 G06
VEE Supply Current vs Voltage
VLIM (mV)
1.6
IEE SUPPLY CURRENT (mA)
–40°C
25°C
85°C
0
4266 G05
VDD Supply Current vs Voltage
1.7
IDD SUPPLY CURRENT (mA)
–6
–20
50µs/DIV
4266 G04
0.8
–4
–18
10ms/DIV
1.8
VDD = 3.3V
VEE = –54V
TA = 25°C
–2
CLASSIFICATION VOLTAGE (V)
2-Event Classification
in Auto Pin Mode
PORT
VOLTAGE
10V/DIV
PORT 1
VDD = 3.3V
VEE = –55V
PD IS CLASS 1
PORT
VOLTAGE
10V/DIV
425mA
CURRENT LIMIT
840
120
4266 G09
4266fb
7
LTC4266
TYPICAL PERFORMANCE CHARACTERISTICS
802.3af ILIM Threshold vs
Temperature
163
162
429
426
423
105.75
105.00
–40
0
420
120
40
80
TEMPERATURE (°C)
652
VDD = 3.3V
VEE = –54V
RSENSE = 0.25Ω
REG 47h = E2h
PORT 1
648
161
644
160
640
159
636
158
–40
0
40
80
TEMPERATURE (°C)
4266 G10
DC Disconnect Threshold vs
Temperature
384
2.0000
381
1.9375
378
93.75
375
93.00
–40
0
372
120
80
40
TEMPERATURE (°C)
8.00
VDD = 3.3V
VEE = –54V
RSENSE = 0.25Ω
REG 47h = E2h
PORT 1
7.75
1.8750
7.50
1.8125
7.25
1.7500
–40
0
80
40
TEMPERATURE (°C)
4266 G12
ADC Noise Histogram
Current Readback in Fast Mode
400
200
350
175
300
150
500
125
400
100
300
75
200
50
100
25
50
0
0
0
–54
–45
–36
–18
–27
VOUTn (V)
–9
0
4266 G14
BIN COUNT
600
VLIM (mV)
ILIM (mA)
700
225
ADC Integral Nonlinearity
Current Readback in Fast Mode
1.0
VSENSEn – VEE = 110.4mV
ADC INTEGRAL NONLINEARITY (LSBs)
VDD = 3.3V
VEE = –54V
RSENSE = 0.25Ω
REG 48h = C0h
800
7.00
120
4266 G13
Current Limit Foldback
900
IMIN (mV)
94.50
VMIN (mV)
VDD = 3.3V
VEE = –54V
RSENSE = 0.25Ω
REG 47h = D4h
PORT 1
ICUT (mA)
VCUT (mV)
95.25
630
120
4266 G11
802.3af ICUT Threshold vs
Temperature
96.00
ICUT (mA)
106.50
ILIM (mA)
VLIM (mV)
107.25
432
VDD = 3.3V
VEE = –54V
RSENSE = 0.25Ω
REG 48h = 80h
PORT 1
VCUT (mV)
108.00
802.3at ICUT Threshold vs
Temperature
250
200
150
100
191
192
193
194
ADC OUTPUT
195
196
4266 G15
0.5
0
–0.5
–1.0
0 50 100 150 200 250 300 350 400 450 500
CURRENT SENSE RESISTOR INPUT VOLTAGE (mV)
4266 G16
4266fb
8
LTC4266
TYPICAL PERFORMANCE CHARACTERISTICS
ADC Noise Histogram
Current Readback in Slow Mode
ADC INTEGRAL NONLINEARITY (LSBs)
250
BIN COUNT
200
150
100
50
6139
600
1.0
VSENSEn – VEE = 110.4mV
0
6141
6143
ADC OUTPUT
6145
6147
500
400
0
200
100
–1.0
BIN COUNT
400
300
200
–0.5
100
50
60
0
8533
8532
4266 G20
8534
8535
ADC OUTPUT
8536
0
–0.5
–1.0
0
10
20
40
30
PORT VOLTAGE (V)
GND
2
60
4266 G22
VDD = 3.3V
VEE = –54V
PORT
VOLTAGE
20V/DIV
2.5
50
MOSFET Gate Drive With Fast
Pull Down
3
PULL DOWN VOLTAGE (V)
265
0.5
4266 G21
INT and SDAOUT Pull Down Voltage
vs Load Current
VEE
FAST PULL DOWN
GATE
VOLTAGE
10V/DIV VEE
1.5
1
PORT
CURRENT
500mA/DIV 0mA
0.5
0
264
ADC Integral Nonlinearity
Voltage Readback in Slow Mode
ADC INTEGRAL NONLINEARITY (LSBs)
500
20
40
30
PORT VOLTAGE (V)
262
263
ADC OUTPUT
1.0
AGND – VOUTn = 48.3V
0.5
10
261
260
4266 G19
ADC Noise Histogram Port
Voltage Readback in Slow Mode
600
0
0
0 50 100 150 200 250 300 350 400 450 500
CURRENT SENSE RESISTOR INPUT VOLTAGE (mV)
4266 G18
1.0
–1.0
300
–0.5
ADC Integral Nonlinearity
Voltage Readback in Fast Mode
0
AGND – VOUTn = 48.3V
0.5
4266 G17
ADC INTEGRAL NONLINEARITY (LSBs)
ADC Noise Histogram Port
Voltage Readback in Fast Mode
BIN COUNT
300
ADC Integral Nonlinearity
Current Readback in Slow Mode
0
5
10 15 20 25 30
LOAD CURRENT (mA)
35
40
4266 G23
50Ω
FAULT
APPLIED
CURRENT LIMIT
50Ω FAULT REMOVED
100µs/DIV
4266 G24
4266fb
9
LTC4266
TEST TIMING DIAGRAMS
tDET
CLASSIFICATION
FORCED-CURRENT
VPORTn
FORCEDVOLTAGE
0V
tME1
tME2
VOC
VMARK
15.5V
VCLASS
20.5V
tCLE1
tCLE2
PD
CONNECTED
tCLE3
tPON
tDETDLY
VEE
INT
4266 F01
Figure 1. Detect, Class and Turn-On Timing in AUTO Pin or Semi-Auto Modes
VLIM
VCUT
VSENSEn TO VEE
0V
VSENSEn
TO VEE
VMIN
tSTART, tICUT
INT
INT
tMPS
tDIS
4266 F03
4266 F02
Figure 3. DC Disconnect Timing
Figure 2. Current Limit Timing
t3
VGATEn
tr
t4
tMSD
tSHDN
VEE
SCL
t2
MSD or
SHDNn
tf
t5
t6
t7
t8
SDA
4266 F04
Figure 4. Shut Down Delay Timing
t1
4266 F05
Figure 5. I2C Interface Timing
4266fb
10
LTC4266
I2C TIMING DIAGRAMS
SCL
SDA
0
1
0
AD3 AD2 AD1 AD0 R/W ACK A7
START BY
MASTER
A6
A5
A4
A3
A2
FRAME 1
SERIAL BUS ADDRESS BYTE
A0 ACK D7
A1
ACK BY
SLAVE
D6
D5
D4
D3
D2
ACK BY
SLAVE
D1
D0 ACK
STOP BY
MASTER
ACK BY
SLAVE
FRAME 2
REGISTER ADDRESS BYTE
FRAME 3
DATA BYTE
4266 F06
Figure 6. Writing to a Register
SCL
SDA
0
1
0
AD3 AD2 AD1 AD0 R/W ACK A7
START BY
MASTER
A6
A5
A4
A3
A2
ACK BY
SLAVE
FRAME 1
SERIAL BUS ADDRESS BYTE
A1
A0 ACK
0
1
ACK BY
SLAVE
0
AD3 AD2 AD1 AD0 R/W ACK D7
REPEATED
START BY
MASTER
D6
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
REGISTER ADDRESS BYTE
D5
D4
D3
ACK BY
SLAVE
D2
D1
D0 ACK
NO ACK BY
MASTER
FRAME 2
DATA BYTE
STOP BY
MASTER
4266 F07
Figure 7. Reading from a Register
SCL
SDA
0
1
0
AD3 AD2 AD1 AD0 R/W ACK D7
START BY
MASTER
D6
D5
D4
D3
ACK BY
SLAVE
D2
D1
D0 ACK
STOP BY
MASTER
NO ACK BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE
4266 F08
Figure 8. Reading the Interrupt Register (Short Form)
SCL
SDA
0
0
0
1
1
0
0
R/W ACK
START BY
MASTER
FRAME 1
ALERT RESPONSE ADDRESS BYTE
0
1
ACK BY
SLAVE
0
AD3 AD2 AD1 AD0
1
NO ACK BY
MASTER
FRAME 2
SERIAL BUS ADDRESS BYTE
ACK
STOP BY
MASTER
4266 F09
Figure 9. Reading from Alert Response Address
4266fb
11
LTC4266
PIN FUNCTIONS
RESET: Chip Reset, Active Low. When the RESET pin is
low, the LTC4266 is held inactive with all ports off and all
internal registers reset to their power-up states. When
RESET is pulled high, the LTC4266 begins normal operation. RESET can be connected to an external capacitor
or RC network to provide a power turn-on delay. Internal
filtering of the RESET pin prevents glitches less than 1µs
wide from resetting the LTC4266. Internally pulled up to
VDD.
MID: Midspan Mode Input. When high, the LTC4266 acts
as a midspan device. Internally pulled down to DGND.
INT: Interrupt Output, Open Drain. INT will pull low when
any one of several events occur in the LTC4266. It will
return to a high impedance state when bits 6 or 7 are set
in the Reset PB register (1Ah). The INT signal can be used
to generate an interrupt to the host processor, eliminating
the need for continuous software polling. Individual INT
events can be disabled using the Int Mask register (01h).
See LTC4266 Software Programming documentation for
more information. The INT pin is only updated between
I2C transactions.
SCL: Serial Clock Input. High impedance clock input for
the I2C serial interface bus. SCL must be tied high if not
used.
SDAOUT: Serial Data Output, Open Drain Data Output for
the I2C Serial Interface Bus. The LTC4266 uses two pins
to implement the bidirectional SDA function to simplify
optoisolation of the I2C bus. To implement a standard
bidirectional SDA pin, tie SDAOUT and SDAIN together.
SDAOUT should be grounded or left floating if not used.
See Applications Information for more information.
SDAIN: Serial Data Input. High impedance data input for
the I2C serial interface bus. The LTC4266 uses two pins
to implement the bidirectional SDA function to simplify
optoisolation of the I2C bus. To implement a standard
bidirectional SDA pin, tie SDAOUT and SDAIN together.
SDAIN must be tied high if not used. See Applications
Information for more information.
AD3: Address Bit 3. Tie the address pins high or low to set
the I2C serial address to which the LTC4266 responds. This
address will be 010A3A2A1A0b. Internally pulled up to VDD.
AD2: Address Bit 2. See AD3.
AD1: Address Bit 1. See AD3.
AD0: Address Bit 0. See AD3.
NC, DNC: All pins identified with “NC” or “DNC” must be
left unconnected.
DGND: Digital Ground. DGND is the return for the VDD
supply.
VDD: Logic Power Supply. Connect to a 3.3V power supply
relative to DGND. VDD must be bypassed to DGND near
the LTC4266 with at least a 0.1µF capacitor.
SHDN1: Shutdown Port 1, Active Low. When pulled low,
SHDN1 shuts down port 1, regardless of the state of the
internal registers. Pulling SHDN1 low is equivalent to setting the Reset Port 1 bit in the Reset Pushbutton register
(1Ah). Internal filtering of the SHDN1 pin prevents glitches
less than 1µs wide from reseting the port. Internally pulled
up to VDD.
SHDN2: Shutdown Port 2, Active Low. See SHDN1.
SHDN3: Shutdown Port 3, Active Low. See SHDN1.
SHDN4: Shutdown Port 4, Active Low. See SHDN1.
AGND: Analog Ground. AGND is the return for the VEE
supply.
SENSE4: Port 4 Current Sense Input. SENSE4 monitors
the external MOSFET current via a 0.5Ω or 0.25Ω sense
resistor between SENSE4 and VEE. Whenever the voltage
across the sense resistor exceeds the overcurrent detection
threshold VCUT, the current limit fault timer counts up. If
the voltage across the sense resistor reaches the current
limit threshold VLIM, the GATE4 pin voltage is lowered to
maintain constant current in the external MOSFET. See
Applications Information for further details. If the port is
unused, the SENSE4 pin must be tied to VEE.
4266fb
12
LTC4266
PIN FUNCTIONS
GATE4: Port 4 Gate Drive. GATE4 should be connected
to the gate of the external MOSFET for port 4. When the
MOSFET is turned on, the gate voltage is driven to 13V
(typ) above VEE. During a current limit condition, the
voltage at GATE4 will be reduced to maintain constant
current through the external MOSFET. If the fault timer
expires, GATE4 is pulled down, turning the MOSFET off
and recording a tCUT or tSTART event. If the port is unused,
float the GATE4 pin.
OUT4: Port 4 Output Voltage Monitor. OUT4 should be
connected to the output port. A current limit foldback
circuit limits the power dissipation in the external MOSFET
by reducing the current limit threshold when the drain-tosource voltage exceeds 10V. The port 4 Power Good bit is
set when the voltage from OUT4 to VEE drops below 2.4V
(typ). A 500k resistor is connected internally from OUT4
to AGND when the port is idle. If the port is unused, OUT4
pin must be floated.
SENSE3: Port 3 Current Sense Input. See SENSE4.
GATE3: Port 3 Gate Drive. See GATE4.
OUT3: Port 3 Output Voltage Monitor. See OUT4.
VEE: Main Supply Input. Connect to a –45V to –57V
supply, relative to AGND.
SENSE2: Port 2 Current Sense Input. See SENSE4.
GATE2: Port 2 Gate Drive. See GATE4.
OUT2: Port 2 Output Voltage Monitor. See OUT4.
SENSE1: Port 1 Current Sense Input. See SENSE4.
GATE1: Port 1 Gate Drive. See GATE 4.
OUT1: Port 1 Output Voltage Monitor. See OUT4.
AUTO: AUTO Pin Mode Input. AUTO pin mode allows the
LTC4266 to detect and power up a PD even if there is no
host controller present on the I2C bus. The voltage of the
AUTO pin determines the state of the internal registers
when the LTC4266 is reset or comes out of VDD UVLO
(see the Register map). The states of these register bits
can subsequently be changed via the I2C interface. The
real-time state of the AUTO pin is read at bit 0 in the Pin
Status register (11h). Internally pulled down to DGND.
Must be tied locally to either VDD or DGND.
MSD: Maskable Shutdown Input. Active low. When pulled
low, all ports that have their corresponding mask bit set
in the Misc Config register (17h) will be reset, equivalent
to pulling the SHDN pin low. Internal filtering of the MSD
pin prevents glitches less than 1µs wide from resetting
ports. Internally pulled up to VDD.
4266fb
13
LTC4266
OPERATION
Overview
Power over Ethernet, or PoE, is a standard protocol for
sending DC power over copper Ethernet data wiring.
The IEEE group that administers the 802.3 Ethernet data
standards added PoE powering capability in 2003. This
original PoE spec, known as 802.3af, allowed for 48V DC
power at up to 13W. This initial spec was widely popular,
but 13W was not adequate for some requirements. In
2009, the IEEE released a new standard, known as 802.3at
or PoE+, increasing the voltage and current requirements
to provide 25W of power.
The IEEE standard also defines PoE terminology. A device
that provides power to the network is known as a PSE, or
power sourcing equipment, while a device that draws power
from the network is known as a PD, or powered device.
PSEs come in two types: Endpoints (typically network
switches or routers), which provide data and power; and
Midspans, which provide power but pass through data.
Midspans are typically used to add PoE capability to existing
non-PoE networks. PDs are typically IP phones, wireless
access points, security cameras, and similar devices, but
could be nearly anything that runs from 25W or less and
includes an RJ45-style network connector.
The LTC4266 is a third-generation quad PSE controller
that implements four PSE ports in either an endpoint or
midspan design. Virtually all necessary circuitry is included
to implement a IEEE 802.3at compliant PSE design, requiring only an external power MOSFET and sense resistor per
PSE
RJ45
4
DGND
3.3V
INTERRUPT
I2C
1µF
100V
X7R
–48V
PoE Basics
Common Ethernet data connections consist of two or four
twisted pairs of copper wire (commonly known as CAT-5
cable), transformer-coupled at each end to avoid ground
loops. PoE systems take advantage of this coupling arrangement by applying voltage between the center-taps
of the data transformers to transmit power from the PSE
to the PD without affecting data transmission. Figure 10
shows a high-level PoE system schematic.
To avoid damaging legacy data equipment that does not
expect to see DC voltage, the PoE spec defines a protocol
that determines when the PSE may apply and remove
power. Valid PDs are required to have a specific 25k common mode resistance at their input. When such a PD is
connected to the cable, the PSE detects this signature
resistance and turns on the power. When the PD is later
disconnected, the PSE senses the open circuit and turns
power off. The PSE also turns off power in the event of a
current fault or short circuit.
When a PD is detected, the PSE optionally looks for a
classification signature that tells the PSE the maximum
power the PD will draw. The PSE can use this information
to allocate power among several ports, police the current
consumption of the PD, or to reject a PD that will draw
CAT 5
20Ω MAX
ROUNDTRIP
0.05µF MAX
5
GND
SMAJ58A
channel; these minimize power loss compared to alternative designs with on-board MOSFETs and increase system
reliability in the event a single channel is damaged.
AGND
VDD
INT
1/4
SCL
LTC4266
SDAIN
SDAOUT
VEE
SENSE GATE OUT
PD
RJ45
4
5
1N4002
×4
SPARE PAIR
0.22µF
100V
X7R
1
1
Tx
DATA PAIR
3
2
3
Rx
0.1µF
Tx
6
DATA PAIR
6
1N4002
×4
IRFM120A
S1B
GND
RCLASS
S1B
0.25Ω
5µF ≤ CIN
≤ 300µF
SMAJ58A
58V
Rx
2
PWRGD
LTC4265
7
7
8
8
–48VIN
–48VOUT
DC/DC
CONVERTER
+
VOUT
–
SPARE PAIR
4266 F10
Figure 10. Power Over Ethernet System Diagram
4266fb
14
LTC4266
OPERATION
more power that the PSE has available. The classification
step is optional; if a PSE chooses not to classify a PD, it
must assume that the PD is a 13W (full 802.3af power)
device.
compatible) devices can be substituted with the LTC4266
without software or PCB layout changes; only minor BOM
changes are required to implement a fully compliant
802.3at design.
New in 802.3at
Because of the backwards compatibility features, some of
the internal registers are redundant or unused when the
LTC4266 is operated as recommended. For more details
on usage in compatibility mode, refer to the LTC4258/
LTC4259A device datasheets.
The newer 802.3at standard supersedes 802.3af and brings
several new features:
• A PD may draw as much as 25.5W. Such PDs (and the
PSEs that support them) are known as Type 2. Older
13W 802.3af equipment is classified as Type 1. Type 1
PDs will work with all PSEs; Type 2 PDs may require
Type 2 PSEs to work properly. The LTC4266 is designed
to work in both Type 1 and Type 2 PSE designs, and
also supports non-standard configurations at higher
power levels.
• The Classification protocol is expanded to allow Type 2
PSEs to detect Type 2 PDs, and to allow Type 2 PDs to
determine if they are connected to a Type 2 PSE. Two
versions of the new Classification protocol are available: an expanded version of the 802.3af Class Pulse
protocol, and an alternate method integrated with the
existing LLDP protocol (using the Ethernet data path).
The LTC4266 fully supports the new Class Pulse protocol
and is also compatible with the LLDP protocol (which
is implemented in the data communications layer, not
in the PoE circuitry).
• Fault protection current levels and timing are adjusted
to reduce peak power in the MOSFET during a fault;
this allows the new 25.5W power levels to be reached
using the same MOSFETs as older 13W designs.
BACKWARDS COMPATIBILITY
The LTC4266 is designed to be backward compatible with
earlier PSE chips in both software and pin functions. Existing systems using either the LTC4258 or LTC4259A (or
Special Compatibility Mode Notes
• The LTC4266 can use either 0.5Ω or 0.25Ω sense
resistors, while the LTC425x chips always used 0.5Ω.
To maintain compatibility, if the AUTO pin is low when
the LTC4266 powers up it assumes the sense resistor
is 0.5Ω; if it is high at power up, the LTC4266 assumes
0.25Ω. The resistor value setting can be reconfigured
at any time after power up. In particular, systems that
use 0.25Ω sense resistors and have AUTO tied low
must reconfigure the resistor settings after power up.
• The LTC4259A included both AC and DC disconnect
sensing circuitry, but the LTC4266 has only DC disconnect sensing. For the sake of compatibility, register
bits used to enable AC disconnect in the LTC4259A are
implemented in the LTC4266, but they simply mirror
the bits used for DC disconnect.
• The LTC4258 and LTC4259A required 10k resistors
between the OUTn pins and the drains of the external
MOSFETs. These resistors must be shorted or replaced
with zero ohm jumpers when using the LTC4266.
• The LTC4258 and LTC4259A included a BYP pin, decoupled to AGND with 0.1µF. This pin changes to the MID
pin on the LTC4266. The capacitor should be removed
for Endspan applications, or replaced with a zero ohm
jumper for Midspan applications.
4266fb
15
LTC4266
APPLICATIONS INFORMATION
Operating Modes
Reset and the AUTO/MID Pins
The LTC4266 includes four independent ports, each of
which can operate in one of four modes: manual, semiauto, AUTO pin or shutdown.
The initial LTC4266 configuration depends on the state
of the AUTO and MID pins during reset. Reset occurs at
power-up, or whenever the RESET pin is pulled low or the
global Reset All bit is set. Note that the AUTO pin is only
sampled when a reset occurs. Changing the state of AUTO
or MID after power-up will not change the port behavior
of the LTC4266 until a reset occurs.
Table 1. Operating Modes
MODE
AUTO Pin
AUTO
PIN OPMD
1
11b
DETECT/
CLASS
POWER-UP
Enabled at Automatically
Reset
AUTOMATIC
ICUT/ILIM
ASSIGNMENT
Yes
Reserved
0
11b
N/A
N/A
N/A
Semi-auto
0
10b
Host
Enabled
Upon
Request
No
Manual
0
01b
Once Upon
Request
Upon
Request
No
Shutdown
0
00b
Disabled
Disabled
No
• In manual mode, the port waits for instructions from the
host system before taking any action. It runs a single
detection or classification cycle when commanded to
by the host, and reports the result in its Port Status
register. The host system can command the port to turn
on or off the power at any time. This mode should only
be used for diagnostic and test purposes.
• In semi-auto mode, the port repeatedly attempts to
detect and classify any PD attached to it. It reports the
status of these attempts back to the host, and waits for
a command from the host before turning on power to
the port. The host must enable detection (and optionally
classification) for the port before detection will start.
Although typically used with a host controller, the LTC4266
can also be used in a standalone mode with no connection
to the serial interface. If there is no host present, the AUTO
pin should be tied high so that, at reset, all ports will be
configured to operate automatically. Each port will detect
and classify repeatedly until a PD is discovered, set ICUT
and ILIM according to the classification results, apply power
after successful detection, and remove power when a PD
is disconnected. Similarly, if the standalone application
is a midspan, the MID pin should be tied high to enable
correct midspan detection timing.
Table 2 shows the ICUT and ILIM values that will be automatically set in AUTO pin mode, based on the discovered class.
Table 2. ICUT and ILIM Values in AUTO pin mode
CLASS
ICUT
ILIM
Class 1
112mA
425mA
Class 2
206mA
425mA
Class 3 or Class 0
375mA
425mA
Class 4
638mA
850mA
• AUTO pin mode operates the same as semi-auto mode
except that it will automatically turn on the power to the
port if detection is successful. In AUTO pin mode, ICUT
and ILIM values are set automatically by the LTC4266. The
AUTO pin must be high at reset to ensure proper AUTO
pin mode operation.
The automatic setting of the ICUT and ILIM values only occurs if the LTC4266 is reset with the AUTO pin high.
• In shutdown mode, the port is disabled and will not
detect or power a PD.
To avoid damaging network devices that were not designed
to tolerate DC voltage, a PSE must determine whether the
connected device is a real PD before applying power. The
IEEE specification requires that a valid PD have a common
mode resistance of 25k ±5% at any port voltage below 10V.
The PSE must accept resistances that fall between 19k and
26.5k, and it must reject resistances above 33kΩ or below
15k (shaded regions in Figure 11). The PSE may choose to
Regardless of which mode it is in, the LTC4266 will remove
power automatically from any port that generates a current
limit fault. It will also automatically remove power from
any port that generates a disconnect event if disconnect
detection is enabled. The host controller may also command the port to remove power at any time.
16
DETECTION
Detection Overview
4266fb
LTC4266
APPLICATIONS INFORMATION
PD
10k
20k
150Ω (NIC)
PSE
15k
30k
23.75k
26.25k
19k
26.5k
33k
275
4266 F11
Figure 11. IEEE 802.3af Signature Resistance Ranges
accept or reject resistances in the undefined areas between
the must-accept and must-reject ranges. In particular, the
PSE must reject standard computer network ports, many
of which have 150Ω common mode termination resistors
that will be damaged if power is applied to them (the black
region at the left of Figure 11).
4-Point Detection
The LTC4266 uses a 4-point detection method to discover
PDs. False-positive detections are minimized by checking for signature resistance with both forced-current and
forced-voltage measurements. Initially, two test currents
are forced onto the port (via the OUTn pin) and the resulting
voltages are measured. The detection circuitry subtracts
the two V-I points to determine the resistive slope while
removing offset caused by series diodes or leakage at
the port (see Figure 12). If the forced-current detection
yields a valid signature resistance, two test voltages are
then forced onto the port and the resulting currents are
measured and subtracted. Both methods must report
valid resistances for the port to report a valid detection.
PD signature resistances between 17k and 29k (typically)
are detected as valid and reported as Detect Good in the
corresponding Port Status register. Values outside this
range, including open and short circuits, are also reported.
If the port measures less than 1V at the first forced-current
test, the detection cycle will abort and Short Circuit will
be reported. Table 3 shows the possible detection results.
Table 3. Detection Status
MEASURED PD SIGNATURE
Incomplete or Not Yet Tested
<2.4k
Capacitance > 2.7µF
2.4k < RPD < 17k
17k < RPD < 29k
>29k
>50k
Voltage > 10V
DETECTION RESULT
Detect Status Unknown
Short Circuit
CPD too High
RSIG too Low
Detect Good
RSIG too High
Open Circuit
Port Voltage Outside Detect Range
CURRENT (µA)
RESISTANCE 0Ω
25kΩ SLOPE
165
VALID PD
0V-2V
OFFSET
FIRST
DETECTION
POINT
SECOND
DETECTION
POINT
VOLTAGE
4266 F12
Figure 12. PD Detection
Operating Modes
The port’s operating mode determines when the LTC4266
runs a detection cycle. In manual mode, the port will
idle until the host orders a detect cycle. It will then run
detection, report the results, and return to idle to wait for
another command.
In semi-auto mode, the LTC4266 autonomously polls a port
for PDs, but it will not apply power until commanded to do
so by the host. The Port Status register is updated at the
end of each detection cycle. If a valid signature resistance
is detected and classification is enabled, the port will classify the PD and report that result as well. The port will then
wait for at least 100ms (or 2 seconds if midspan mode is
enabled), and will repeat the detection cycle to ensure that
the data in the port status register is up-to-date.
If the port is in semi-auto mode and high power operation is enabled, the port will not turn on in response to
a power-on command unless the current detect result is
Detect Good. Any other detect result will generate a tSTART
fault if a power-on command is received. If the port is not
in high power mode, it will ignore the detection result and
apply power when commanded, maintaining backwards
compatibility with the LTC4259A.
Behavior in AUTO pin mode is similar to semi-auto; however,
after Detect Good is reported and the port is classified (if
classification is enabled), it is automatically powered on
without further intervention. In AUTO pin mode, the ICUT
and ILIM thresholds are automatically set; see the Reset
and the AUTO/MID Pins section for more information.
4266fb
17
LTC4266
APPLICATIONS INFORMATION
Detection of Legacy PDs
Proprietary PDs that predate the original IEEE 802.3af
standard are commonly referred to today as legacy devices. One type of legacy PD uses a large common mode
capacitance (>10μF) as the detection signature. Note that
PDs in this range of capacitance are defined as invalid, so
a PSE that detects legacy PDs is technically noncompliant
with the IEEE spec.
The LTC4266 can be configured to detect this type of legacy
PD. Legacy detection is disabled by default, but can be
manually enabled on a per-port basis. When enabled, the
port will report detect good when it sees either a valid IEEE
PD or a high-capacitance legacy PD. With legacy mode
disabled, only valid IEEE PDs will be recognized.
CLASSIFICATION
802.3af Classification
A PD can optionally present a classification signature to
the PSE to indicate the maximum power it will draw while
operating. The IEEE specification defines this signature
as a constant current draw when the PSE port voltage
is in the VCLASS range (between 15.5V and 20.5V), with
the current level indicating one of 5 possible PD classes.
Figure 14 shows a typical PD load line, starting with the
slope of the 25kΩ signature resistor below 10V, then
transitioning to the classification signature current (in
this case, Class 3) in the VCLASS range. Table 4 shows the
possible classification values.
Table 4. Classification Values
CLASS
RESULT
Class 0
No Class Signature Present; Treat Like Class 3
Class 1
3W
Class 2
7W
Class 3
13W
Class 4
25.5W (Type 2)
60
PSE LOAD LINE
OVER
CURRENT
50
48mA
CURRENT (mA)
The signature detection circuitry is disabled when the port
is initially powered up with the AUTO pin low, in shutdown
mode, or when the corresponding detect enable bit is
cleared.
40
CLASS 4
30
CLASS 3
23mA
20
TYPICAL
CLASS 3
PD LOAD
LINE
10
0
33mA
0
5
CLASS 2
CLASS 1
CLASS 0
10
15
VOLTAGE (VCLASS)
14.5mA
6.5mA
20
25
4266 F13
Figure 13. PD Classification
If classification is enabled, the port will classify the PD
immediately after a successful detection cycle in semi-auto
or AUTO pin modes, or when commanded to in manual
mode. It measures the PD classification signature by applying 18V for 12ms (both values typical) to the port via
the OUTn pin and measuring the resulting current; it then
reports the discovered class in the port status register. If
the LTC4266 is in AUTO pin mode, it will additionally use
the classification result to set the ICUT and ILIM thresholds.
See the Reset and the AUTO/MID Pins section for more
information.
The classification circuitry is disabled when the port is
initially powered up with the AUTO pin low, in shutdown
mode, or when the corresponding class enable bit is
cleared.
802.3at 2-Event Classification
The 802.3at spec defines two methods of classifying a
Type 2 PD.
One method adds extra fields to the Ethernet LLDP data
protocol; although the LTC4266 is compatible with this
classification method, it cannot perform classification
directly since it doesn’t have access to the data path.
LLDP classification requires the PSE to power the PD as
a standard 802.3af (Type 1) device. It then waits for the
host to perform LLDP communication with the PD and
update the PSE port data. The LTC4266 supports changing the ILIM and ICUT levels on the fly, allowing the host
to complete LLDP classification.
4266fb
18
LTC4266
APPLICATIONS INFORMATION
The second 802.3at classification method, known as
2-event classification or ping-pong, is fully supported by
the LTC4266. A Type 2 PD that is requesting more than
13W will indicate Class 4 during normal 802.3af classification. If the LTC4266 sees Class 4, it forces the port to a
specified lower voltage (called the mark voltage, typically
9V), pauses briefly, and then re-runs classification to
verify the Class 4 reading (Figure 1). It also sets a bit in
the High Power Status register to indicate that it ran the
second classification cycle. The second cycle alerts the
PD that it is connected to a Type 2 PSE which can supply
Type 2 power levels.
2-event ping-pong classification is enabled by setting a bit
in the port’s High Power Mode register. Note that a pingpong enabled port only runs the second classification cycle
when it detects a Class 4 device; if the first cycle returns
Class 0 to 3, the port assumes it is connected to a Type
1 PD and does not run the second classification cycle.
Invalid Type 2 Class Combinations
The 802.3at spec defines a Type 2 PD class signature as
two consecutive Class 4 results; a Class 4 followed by a
Class 0-3 is not a valid signature. In AUTO pin mode, the
LTC4266 will power a detected PD regardless of the classification results, with one exception: if the PD presents
an invalid Type 2 signature (Class 4 followed by Class 0
to 3), the LTC4266 will not provide power and will restart
the detection process. To aid in diagnosis, the Port Status
register will always report the results of the last class pulse,
so an invalid Class 4–Class 2 combination would report
a second class pulse was run in the High Power Status
register (which implies that the first cycle found Class 4),
and Class 2 in the Port Status register.
POWER CONTROL
External MOSFET, Sense R Summary
The primary function of the LTC4266 is to control the
delivery of power to the PSE port. It does this by controlling the gate drive voltage of an external power MOSFET
while monitoring the current via an external sense resistor and the output voltage at the OUT pin. This circuitry
serves to couple the raw VEE input supply to the port in
a controlled manner that satisfies the PD’s power needs
while minimizing power dissipation in the MOSFET and
disturbances on the VEE backplane.
The LTC4266 is designed to use 0.25Ω sense resistors to
minimize power dissipation. It also supports 0.5Ω sense
resistors, which are the default when LTC4258/LTC4259A
compatibility is desired.
Inrush Control
Once the command has been given to turn on a port, the
LTC4266 ramps up the GATE pin of that port’s external
MOSFET in a controlled manner. Under normal power-up
circumstances, the MOSFET gate will rise until the port
current reaches the inrush current limit level (typically
450mA), at which point the GATE pin will be servoed to
maintain the specified IINRUSH current. During this inrush
period, a timer (tSTART) runs. When output charging is
complete, the port current will fall and the GATE pin will
be allowed to continue rising to fully enhance the MOSFET
and minimize its on-resistance. The final VGS is nominally
13V. If the tSTART timer expires before the inrush period
completes, the port will be turned back off and a tSTART
fault reported.
Current Limit
Each LTC4266 port includes two current limiting thresholds
(ICUT and ILIM), each with a corresponding timer (tCUT
and tLIM). Setting the ICUT and ILIM thresholds depends
on several factors: the class of the PD, the voltage of the
main supply (VEE), the type of PSE (1 or 2), the sense
resistor (0.5Ω or 0.25Ω), the SOA of the MOSFET, and
whether or not the system is required to implement class
enforcement.
Per the IEEE spec, the LTC4266 will allow the port current to exceed ICUT for a limited period of time before
removing power from the port, whereas it will actively
control the MOSFET gate drive to keep the port current
below ILIM. The port does not take any action to limit the
current when only the ICUT threshold is exceeded, but
does start the tCUT timer. The tLIM timer starts when the
ILIM threshold is exceeded and current limit is active. If
the current drops below the ICUT current threshold before
its timer expires, the tCUT timer counts back down, but
4266fb
19
LTC4266
APPLICATIONS INFORMATION
1.0
09
372
8B
425
00
478
8E
531
92
584
CB
638
10
90
744
D2
9A
850
40
C0
956
4A
CA
1063
50
D0
1169
5A
DA
1275
60
E0
1488
52
25
sA
m
0.3
802.3af FOLDBACK
0.2
0.1
0.0
89
49
1700
40
1913
4A
2125
50
2338
5A
2550
60
2975
52
60
4266 F14
1.0
25
°C
0.9
T
75
m
sA
0.8
A
0.7
T
sA
SO
8A
10
30
40
50
20
PD VOLTAGE (V) AT VPSE = 58V
Figure 14. Turn On Currents vs FET Safe Operating
Area at 90°C Ambient
PSE CURRENT (A)
80
SOA DC AT 90°C
0
OLDB
ACK
319
0.4
0.6
m
A
0.5
SO
0.4
0.3
75
°C
90
266 F
8A
0.5
LTC4
266
08
FO
80
75
213
A
89
af
159
88
2.3
08
SO
106
80
88
0.7
0.6
2x
53
RSENSE = 0.25Ω
PSE CURRENT (A)
RSENSE = 0.5Ω
T
0.8
INTERNAL REGISTER SETTING (hex)
ILIM (mA)
°C
0.9
Table 5. Example Current Limit Settings
CK
Per the IEEE specification, the LTC4266 will automatically
set ILIM to 425mA (shown in bold in Table 5) during inrush at port turn-on, and then switch to the programmed
ILIM setting once inrush has completed. To maintain IEEE
compliance, ILIM should kept at 425mA for all Type 1 PDs,
and 850mA if a Type 2 PD is detected. ILIM is automatically
reset to 425mA when a port turns off.
The LTC4266 features a two-stage foldback circuit that
reduces the port current if the port voltage falls below the
normal operating voltage. This keeps MOSFET power dissipation at safe levels for typical 802.3af MOSFETs, even at
extended 802.3at power levels. Current limit and foldback
behavior are programmable on a per-port basis. Figure
14 shows MOSFET power dissipation with 802.3af-style
foldback compared with a typical MOSFET SOA curve;
Figure 15 demonstrates how two-stage foldback keeps
the FET within its SOA under the same conditions. Table 5
gives examples of recommended ILIM register settings.
BA
ICUT is typically set to a lower value than ILIM to allow the
port to tolerate minor faults without current limiting.
ILIM Foldback
LD
at 1/16 the rate that it counts up. This allows the current
limit circuitry to tolerate intermittent overload signals with
duty cycles below about 6%; longer duty cycle overloads
will turn the port off.
802.3af FOLDBACK
0.2
0.1
0.0
SOA DC AT 90°C
0
10
30
40
50
20
PD VOLTAGE (V) AT VPSE = 58V
60
4266 F15
Figure 15. LTC4266 Foldback vs FET Safe Operating
Area at 90°C Ambient
4266fb
20
LTC4266
APPLICATIONS INFORMATION
The LTC4266 will support current levels well beyond the
maximum values in the 802.3at specification. The shaded
areas in Table 5 indicate settings that may require a larger
external MOSFET, additional heat sinking, or a reduced
tLIM setting.
MOSFET Fault Detection
LTC4266 PSE ports are designed to tolerate significant
levels of abuse, but in extreme cases it is possible for
the external MOSFET to be damaged. A failed MOSFET
may short source to drain, which will make the port appear to be on when it should be off; this condition may
also cause the sense resistor to fuse open, turning off
the port but causing the LTC4266 SENSE pin to rise to
an abnormally high voltage. A failed MOSFET may also
short from gate to drain, causing the LTC4266 GATE pin
to rise to an abnormally high voltage. The LTC4266 SENSE
and GATE pins are designed to tolerate up to 80V faults
without damage.
If the LTC4266 sees any of these conditions for more than
180μs, it disables all port functionality, reduces the gate
drive pull-down current for the port and reports a FET Bad
fault. This is typically a permanent fault, but the host can
attempt to recover by resetting the port, or by resetting
the entire chip if a port reset fails to clear the fault. If the
MOSFET is in fact bad, the fault will quickly return, and
the port will disable itself again. The remaining ports of
the LTC4266 are unaffected.
An open or missing MOSFET will not trigger a FET Bad
fault, but will cause a tSTART fault if the LTC4266 attempts
to turn on the port.
Voltage and Current Readback
The LTC4266 measures the output voltage and current
at each port with an internal A/D converter. Port data is
only valid when the port power is on. The converter has
two modes:
• Slow mode: 14 samples per second, 14.5 bits resolution
• Fast mode: 440 samples per second, 9.5 bits resolution
In fast mode, the least significant 5 bits of the lower byte are
zeroes so that bit scaling is the same in both modes.
Disconnect
The LTC4266 monitors the port to make sure that the PD
continues to draw the minimum specified current. A disconnect timer counts up whenever port current is below
7.5mA (typ), indicating that the PD has been disconnected.
If the tDIS timer expires, the port will be turned off and
the disconnect bit in the fault event register will be set.
If the current returns before the tDIS timer runs out, the
timer resets and will start counting from the beginning
if the undercurrent condition returns. As long as the PD
exceeds the minimum current level more often than tDIS,
it will stay powered.
Although not recommended, the DC disconnect feature can
be disabled by clearing the corresponding DC Disconnect
Enable bits. Note that this defeats the protection mechanisms built into the IEEE spec, since a powered port will
stay powered after the PD is removed. If the still-powered
port is subsequently connected to a non-PoE data device,
the device may be damaged.
The LTC4266 does not include AC disconnect circuitry, but
includes AC disconnect enable bits to maintain compatibility with the LTC4259A. If the AC Disconnect Enable bits
are set, DC disconnect will be used.
Shutdown Pins
The LTC4266 includes a hardware SHDN pin for each port.
When a SHDN pin is pulled to DGND, the corresponding
port will be shut off immediately. The port remains shut
down until re-enabled via I2C or a device reset in AUTO
pin mode.
Masked Shutdown
The LTC4266 provides a low latency port shedding feature to quickly reduce the system load when required. By
allowing a pre-determined set of ports to be turned off,
the current on an overloaded main power supply can be
reduced rapidly while keeping high priority devices powered. Each port can be configured to high or low priority;
all low-priority ports will shut down within 6.5μs after
the MSD pin is pulled low. If multiple ports in a LTC4266
device are shut down via MSD, they are staggered by at
least 0.55μs to help reduce voltage transients on the main
4266fb
21
LTC4266
APPLICATIONS INFORMATION
supply. If a port is turned off via MSD, the corresponding
detection and classification enable bits are cleared, so
the port will remain off until the host explicitly re-enables
detection.
SERIAL DIGITAL INTERFACE
Overview
The LTC4266 communicates with the host using a standard
SMBus/I2C 2-wire interface. The LTC4266 is a slave-only
device, and communicates with the host master using
the standard SMBus protocols. Interrupts are signaled to
the host via the INT pin. The timing diagrams (Figures 5
through 9) show typical communication waveforms and
their timing relationships. More information about the
SMBus data protocols can be found at www.smbus.org.
The LTC4266 requires both the VDD and VEE supply rails
to be present for the serial interface to function.
Bus Addressing
The LTC4266’s primary serial bus address is 010xxxxb, with
the lower four bits set by the AD3-AD0 pins; this allows up
to 16 LTC4266s on a single bus. All LTC4266s also respond
to the address 0110000b, allowing the host to write the
same command (typically configuration commands) to
multiple LTC4266s in a single transaction. If the LTC4266
is asserting the INT pin, it will also respond to the alert
response address (0001100b) per the SMBus spec.
Interrupts and SMBALERT
Most LTC4266 port events can be configured to trigger
an interrupt, asserting the INT pin and alerting the host to
the event. This removes the need for the host to poll the
LTC4266, minimizing serial bus traffic and conserving host
CPU cycles. Multiple LTC4266s can share a common INT
line, with the host using the SMBALERT protocol (ARA)
to determine which LTC4266 caused an interrupt.
Register Description
For information on serial bus usage and device configuration and status, refer to the LTC4266 Software Programming documentation.
EXTERNAL COMPONENT SELECTION
Power Supplies and Bypassing
The LTC4266 requires two supply voltages to operate. VDD
requires 3.3V (nominally) relative to DGND. VEE requires a
negative voltage of between –44V and –57V for Type  1 PSEs,
or –50V to –57V for Type 2 PSEs, relative to AGND. The
relationship between the two grounds is not fixed; AGND
can be referenced to any level from VDD to DGND, although
it should typically be tied to either VDD or DGND.
VDD provides power for most of the internal LTC4266 circuitry, and draws a maximum of 3mA. A ceramic decoupling
cap of at least 0.1μF should be placed from VDD to DGND,
as close as practical to each LTC4266 chip.
Figure 16 shows a three component low dropout regulator
for a negative supply to DGND generated from the negative
VEE supply. VDD is tied to AGND and DGND is negative
referenced to AGND. This regulator drives a single LTC4266
device. In Figure 17, DGND is tied to AGND in this boost
converter circuit for a positive VDD supply of 3.3V above
AGND. This circuit can drive multiple LTC4266 devices
and opto couplers.
VEE is the main supply that provides power to the PDs.
Because it supplies a relatively large amount of power and
is subject to significant current transients, it requires more
design care than a simple logic supply. For minimum IR
loss and best system efficiency, set VEE near maximum
amplitude (57V), leaving enough margin to account for
transient over- or undershoot, temperature drift, and the line
regulation specs of the particular power supply used.
AGND
D1
CMHZ4687-4.3V
AGND
VDD
C1
0.1µF
LTC4266
DGND
Q2
CMPTA92
R5
750k
VEE
4266 F16
VEE
Figure 16. Negative LDO to DGND
4266fb
22
LTC4266
APPLICATIONS INFORMATION
L3
100µH
SUMIDA CDRH5D28-101NC
C77
0.22µF
100V
C76
10µF
63V
+
C78
0.22µF
100V
R60
10Ω
C74
100µF
6.3V
C75
10µF
16V
R53
4.7k
1%
5
VCC
1
R58
10Ω
VEE
R51
4.7k
1%
R54
56k
C79
2200pF
ITH/RUN
L4
10µH
SUMIDA CDRH4D28-100NC
D28
B1100
C73
10µF
6.3V
R52
3.32k
1%
Q13
FMMT723
NGATE
6
3.3V AT 400mA
Q14
FMMT723
Q15
FDC2512
LTC3803
3
VFB
SENSE
4
GND
2
R57
1k
R55
806Ω
1%
R59
0.100Ω
1%, 1W
R56
47.5k
1%
4266 F17
Figure 17. Positive VDD Boost Converter
Bypass capacitance between AGND and VEE is very important for reliable operation. If a short circuit occurs at
one of the output ports it can take as long as 1μs for the
LTC4266 to begin regulating the current. During this time
the current is limited only by the small impedances in the
circuit and a high current spike typically occurs, causing a
voltage transient on the VEE supply and possibly causing
the LTC4266 to reset due to a UVLO fault. A 1μF, 100V
X7R capacitor placed near the VEE pin is recommended
to minimize spurious resets.
If the device is part of a larger system, contains additional
external non-Ethernet ports, or must be referenced to
protective ground for some other reason, the Power over
Ethernet subsystem (including all LTC4266s) must be
electrically isolated from the rest of the system. Figure 18
shows a typical isolated serial interface. The SDAOUT pin
of the LTC4266 is designed to drive the inputs of an optocoupler directly. Standard I2C/SMBus devices typically
cannot drive opto-couplers, so U1 is used to buffer the
signals from the host controller side.
Isolating the Serial Bus
External MOSFET
The LTC4266 includes a split SDA pin (SDAIN and SDAOUT)
to ease opto-isolation of the bidirectional SDA line.
Careful selection of the power MOSFET is critical to system
reliability. LTC recommends either Fairchild IRFM120A,
FDT3612, FDMC3612 or Philips PHT6NQ10T for their
proven reliability in Type 1 and Type 2 PSE applications.
Non-standard applications that provide more current than
the 850mA IEEE maximum may require heat sinking and
other MOSFET design considerations. Contact LTC Applications before using a MOSFET other than one of these
recommended parts.
IEEE 802.3 Ethernet specifications require that network
segments (including PoE circuitry) be electrically isolated
from the chassis ground of each network interface device.
However, network segments are not required to be isolated
from each other, provided that the segments are connected
to devices residing within a single building on a single
power distribution system.
For simple devices such as small PoE switches, the isolation requirement can be met by using an isolated main
power supply for the entire device. This strategy can be
used if the device has no electrically conducting ports
other than twisted-pair Ethernet. In this case, the SDAIN
and SDAOUT pins can be tied together and will act as a
standard I2C/SMBus SDA pin.
Sense Resistor
The LTC4266 is designed to use either 0.5Ω or 0.25Ω
current sense resistors. For new designs 0.25Ω is recommended to reduce power dissipation; the 0.5Ω option is
intended for existing systems where the LTC4266 is used
as a drop-in replacement for the LTC4258 or LTC4259A.
The lower sense resistor values reduce heat dissipation.
4266fb
23
LTC4266
APPLICATIONS INFORMATION
0.1µF
0.1µF
I2C ADDRESS
VDD LTC4266
INT
SCL
SDAIN
SDAOUT
AD0
AD1
AD2
AD3
DGND
AGND
0100000
VDD LTC4266
INT
SCL
SDAIN
SDAOUT
AD0
AD1
AD2
AD3
DGND
AGND
0100001
VDD LTC4266
INT
SCL
SDAIN
SDAOUT
AD0
AD1
AD2
AD3
DGND
AGND
0100010
0.1µF
VDD CPU
2k
U2
200Ω
U1
SCL
2k
200Ω
SDA
0.1µF
HCPL-063L
TO
CONTROLLER
U3
200Ω
200Ω
SMBALERT
0.1µF
0.1µF
GND CPU
U1: FAIRCHILD NC7WZ17
U2, U3: AGILENT HCPL-063L
HCPL-063L
0.1µF
ISOLATED
3.3V
10µF
+
ISOLATED
GND
•
•
•
LTC4266
VDD
INT
SCL
SDAIN
SDAOUT
AD0
AD1
AD2
AD3
DGND
AGND
0101110
VDD LTC4266
INT
SCL
SDAIN
SDAOUT
AD0
AD1
AD2
AD3
DGND
AGND
0101111
4266 F18
Figure 18. Opto-Isolating the I2C Bus
4266fb
24
LTC4266
APPLICATIONS INFORMATION
Four commonly available 1Ω resistors (0402 or larger
package size) can be used in parallel in place of a single
0.25Ω resistor. In order to meet the ICUT and ILIM accuracy
required by the IEEE specification, the sense resistors
should have ±1% tolerance or better, and no more than
±200ppm/°C temperature coefficient.
Output Cap
Each port requires a 0.22μF cap across its outputs to keep
the LTC4266 stable while in current limit during startup
or overload. Common ceramic capacitors often have significant voltage coefficients; this means the capacitance
is reduced as the applied voltage increases. To minimize
this problem, X7R ceramic capacitors rated for at least
100V are recommended.
ESD/Cable Discharge Protection
Ethernet ports can be subject to significant ESD events
when long data cables, each potentially charged to thousands of volts, are plugged into the low impedance of the
RJ45 jack. To protect against damage, each port requires a
pair of clamp diodes; one to AGND and one to VEE (Figure
10). An additional surge suppressor is required for each
LTC4266 chip from VEE to AGND. The diodes at the ports
steer harmful surges into the supply rails, where they are
absorbed by the surge suppressor and the VEE bypass
capacitance. The surge suppressor has the additional
benefit of protecting the LTC4266 from transients on the
VEE supply.
S1B diodes work well as port clamp diodes, and an
SMAJ58A or equivalent is recommended for the VEE surge
suppressor.
LAYOUT GUIDELINES
Standard power layout guidelines apply to the LTC4266:
place the decoupling caps for the VDD and VEE supplies
near their respective supply pins, use ground planes, and
use wide traces wherever there are significant currents.
The main layout challenge involves the arrangement of
the current sense resistors, and their connections to
the LTC4266. Because the sense resistor values are very
low, layout parasitics can cause significant errors. Care is
required to achieve specified accuracy, particularly with
disconnect currents.
Figure 19 illustrates the problem. In the example on the
left, two ports have load currents I1 and I2 that return to
the VEE power supply through a mutual resistance RM.
RM represents the combined resistances of any traces,
planes, and vias in the PCB that I1 and I2 share as they
return to the VEE supply. The LTC4266 measures the voltage difference between its SENSE and VEE pins to sense
the voltage drop across RS1, but as the example shows,
RM introduces errors.
The example on the right shows how errors can be
minimized with a good layout. The circuit is rearranged
so that RM no longer affects VS, and the VEE connection
to the LTC4266 is used as a Kelvin sense trace. VEE is not
I1 I2
I1 I2
LTC4266
LTC4266
GATE
GATE
SENSE +
VS
VEE
–
IEE
RM
I1 + I2 + IEE
RS1
RS2
MUTUAL RESISTANCE
SENSE +
VS
VEE
–
IEE
RK
KELVIN SENSE LINE
VS = I1RS1 + I1RM + I2RM
SIGNAL
SCALE ERROR
CROSSTALK ERROR
RS1
RS2
RM
I1 + I2 + IEE
VS = I1RS1 – IEERK
SIGNAL
SMALL OFFSET ERROR
4266 F19
Figure 19. Layout Affects Current Readback Accuracy
4266fb
25
LTC4266
APPLICATIONS INFORMATION
a perfect Kelvin connection because all four ports controlled by the LTC4266 share the same sense trace, and
because the current through the trace (IEE) is not zero.
However, as the equation shows, the remaining error is a
small offset term.
Figure 20 shows two LTC4266 chips controlling eight ports
(A though H). The ports are separated into two groups
of four; each has its own trace on the top PCB layer that
connects to the VEE plane with a via. Currents from the U1
sub-circuit are effectively isolated from the U2 sub-circuit,
reducing the layout problem down to 4-port chunks; this
arrangement can be expanded for any number of ports.
Figure 21 shows an example of good 4-port layout. Each
0.25Ω sense resistor consists of four 1Ω resistors in
parallel. The four groups of resistors are arranged to
minimize the overlap in their current flows, which minimizes mutual resistance. The horizontal slits cut in the
copper help to keep the currents separate. Wide copper
paths connect each group of resistors to the vias at the
center, so the resistance is very low.
Proper connection of the sense line is also important. In
Figure 21, U1 is not connected directly to the VEE plane
but is connected instead to a Kelvin sense trace that
leads to the sense resistor array. Similarly, the via at the
center of the sense resistor array has a matching hole
in the VEE plane. This arrangement prevents the mutual
resistance of the four large vias from influencing the
current measurements.
PORTS A THROUGH D
U1
LTC4266
PORTS E THROUGH H
U2
LTC4266
SENSE1
SENSE2
SENSE3
SENSE4
SENSE1
SENSE2
SENSE3
SENSE4
VEE
VEE
THIS TRACE PROVIDES VEE TO U1
BUT ALSO ACTS AS A KELVIN
SENSE LINE FOR PORTS A-D
VIA
RSENSE
VIA
RETURN TO
VEE POWER SUPPLY
VEE COPPER FILL ON SURFACE LAYER
VEE PLANE ON INNER LAYER
BY KEEPING THESE COPPER FILLS SEPARATE ON
THE SURFACE, MUTUAL RESISTANCE BETWEEN
PORTS A-D AND E-H IS ELIMINATED
4266 F20
Figure 20. Layout Strategy to Reduce Mutual Resistance
4266fb
26
LTC4266
APPLICATIONS INFORMATION
EDGE OF VEE PLANE (ON SOME INNER LAYER)
KELVIN SENSE TRACE CONNECTS U1
TO VEE THROUGH THE VIAS ON THE RIGHT
PORT A RSENSE
PORT B RSENSE
PIN 1
FOUR LARGE VIAS
TO VEE PLANE
HOLE IN VEE PLANE
U1
PORT C RSENSE
THE PADDLE IS
CONNECTED TO
VEE PINS
PORT D RSENSE
VIAS TO SOURCE PIN OF
THE PORT D MOSFET
LOCATED ON THE OPPOSITE
SIDE OF THE BOARD
4266 F21
Figure 21. Good PCB Layout Example
PACKAGE DESCRIPTION
GW Package
36-Lead Plastic SSOP (Wide .300 Inch)
(Reference LTC DWG # 05-08-1642)
36
19
1.40 ±0.127
10.804 MIN
15.291 – 15.545*
(.602 – .612)
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
7.75 – 8.258
10.11 – 10.55
(.398 – .415)
1
0.520 ±0.0635
18
0.800 BSC
RECOMMENDED SOLDER PAD LAYOUT
7.417 – 7.595**
(.292 – .299)
0.254 – 0.406 × 45°
(.010 – .016)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
0.355
REF
2.286 – 2.388
(.090 – .094)
2.44 – 2.64
(.096 – .104)
0° – 8° TYP
0.231 – 0.3175
(.0091 – .0125)
0.40 – 1.27
(.015 – .050)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
0.800
(.0315)
BSC
0.28 – 0.51
(.011 – .02)
TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
0.1 – 0.3
(.004 – .0118)
GW36 SSOP 0204
4266fb
27
LTC4266
PACKAGE DESCRIPTION
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)
0.70 ± 0.05
5.50 ± 0.05
5.15 ± 0.05
4.10 ± 0.05
3.00 REF
3.15 ± 0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
5.5 REF
6.10 ± 0.05
7.50 ± 0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 ± 0.10
0.75 ± 0.05
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
3.00 REF
37
0.00 – 0.05
38
0.40 ±0.10
PIN 1
TOP MARK
(SEE NOTE 6)
1
2
5.15 ± 0.10
5.50 REF
7.00 ± 0.10
3.15 ± 0.10
(UH) QFN REF C 1107
0.200 REF 0.25 ± 0.05
0.50 BSC
R = 0.125
TYP
R = 0.10
TYP
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
4266fb
28
LTC4266
REVISION HISTORY
(Revision history begins at Rev B)
REV
DATE
DESCRIPTION
PAGE NUMBER
B
3/11
Revised AGND and DGND pin references throughout data sheet.
1 to 6, 9, 13
Revised auto mode to AUTO pin mode throughout data sheet.
1 to 26
Added text to Operating Modes and made minor text edits throughout Applications Information section.
19 to 26
4266fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
29
LTC4266
TYPICAL APPLICATION
ISOLATED
3.3V
ISOLATED
GND
0.1µF
DGND AGND
2k
U2
200Ω
VDD CPU
FB1
SCL
1/4
SDAIN LTC4266
SDAOUT
INT
U1
SCL
VEE
2k
200Ω
TO
CONTROLLER
0.22µF
100V
X7R
VDD
1µF
100V
X7R
SENSE GATE OUT
FB2
S1B
RS
0.25Ω
SDA
Q1
HCPL-063L
U3
SMAJ58A
200Ω
–48V
ISOLATED
S1B
RJ45
CONNECTOR
T1
•
200Ω
INTERRUPT
•
•
•
•
0.01µF
200V
75Ω
0.01µF
200V
75Ω
75Ω
75Ω
1
2
3
4
5
6
7
8
•
PHY
HCPL-063L
DTSS: DIODES INC SMAJ58A
Q1: FAIRCHILD IRFM120A OR PHILIPS PHT6NQ10T
U1: FAIRCHILD NC7WZ17
U2, U3: AGILENT HCPL-063L
FB1, FB2:TDK MPZ2012S601A
T1: PULSE H6096NL OR COILCRAFT ETH1-230LD
(NETWORK
PHYSICAL
LAYER
CHIP)
•
•
•
GND CPU
•
•
0.1µF
0.01µF
200V
0.01µF
200V
•
4266 F22
1000pF
2000V
Figure 22. One Complete Isolated Powered Ethernet Port
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4266fb
30 Linear Technology Corporation
LT 0311 REV B • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507 ● www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2009